US3717849A - Communication and control system - Google Patents

Abstract

A communication and control system, as for example for underwater petroleum wells, utilizing a minimum number of connections between the surface and subsurface units and employing integrated circuit logic components.

Description

United States Patent 1191 Thornton, Jr. 1 1 Feb. 20, 1973 s41 COMMUNICATION AND CONTROL 3,516,063 6/1970 Arkin Clal ..340 151 x SYSTEM 3,146,456 8/1964 Silliman et a1... ..340/ 163 3,559,177 1/1971 Benson ..340/163 [75] Inventor: Roland L. Thornton, Jr., Severn, 3,551,885 12/1970 Henzel ...340/l63 X 3,518,628 6/1970 Gie1eta1..... ..340/163 x 3,350,687 10/1967 Gabrielson et a1. ..340/l63 [73] Assignee: Cameron Iron Works, Inc.,

Houston, Tex. Primary Examiner-Donald J. Yusko I Attorney-W. F. Hyer, Marvin B. Eickenroht, [22] March 1970 Jennings B. Thompson and Robert W. Turner [21] Appl. No.: 22,536

[57] ABSTRACT [52] 11.8. C1 ..340/l63, 340/151 A communication and control System, as for example Int. Cl. "H04q for underwater petroleum wells utilizing a mini Field Search 151 number of connections between the surface and subsurface units and employing integrated circuit logic [56] References Cited mp UNITED STATES PATENTS 12 Claims, 10 Druwing Figures 3,397,386 8/1968 Bishup et a1. .340 151 x 3 a s9 99 29 99-- li """'1 97 :1 so, {I JIAI't/J Jun/4' iner-60 CWAMVEL Cfl/M/A/EL i {I I: 1 "*,i,% I f, 20 v, 95 1 I l \24 //3 2 .11. J J 15 1 r 1 4 1' OT 24A 211 671.7

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A770 EV CROSS REFERENCES AND BACKGROUND In the offshore petroleum industry, various types of underwater control equipment are used. This equipment includes blowout preventer controls, wellhead controls, pipe-line valve controls, and underwater storage facility controls. The control system presently in use to operate such underwater equipment generally require the use of a large plurality of electrical cables in addition to hydraulic lines and other physical connections from the surface to the underwater equipment. Obviously, such control lines and electrical cables are handicaps to the subsea operation inasmuch as they frequently interfere with drilling operations and are subject to being damaged by boats, storms, or the like. These systems are well known in the art and are practiced throughout the world.

Recently, attempts have been made to communicate from the surface to the subsurface equipment via acoustic links or coupling or the like. However, the acoustic systems have experienced difficulty and, as

yet, are unreliable.

It would thus be desirable to provide a communications and control system which utilizes a minimum number of electrical wires and cables from the surface to subsurface unit. When a minimum number of wires is utilized, the electrical cable can be more easily provided so as to be relatively free from damage or the like.

SUMMARY or INVENTION In order to minimize the number of interconnecting lines between the surface and subsurface units, the instant system is provided. The surface system includes an operators console or the like wherein appropriate control elements, such as push buttons or the like, are utilized to initiate operation of the system. The signals produced by the console are supplied to a code generator as well as to related control circuitry. The code generator is connected to a plurality of logic circuits via a coding network. The coding network provides signals representative of the code generator output which signals will selectively activate the logic circuits.

The code signal from the coding network is supplied to a further code device in the subsurface unit. The second code device is, in essence, a duplicate of the original or surface unit. Additional logic circuitry an decoding networks are provided at the subsurface unit. These logic circuits are of the command or interrogate type. The command type logic circuits supply signals to the subsurface equipment to effect operation thereof. The interrogation type circuits are also connected to the subsea equipment but the signals produced by this type circuit are representative of the status or operation of the subsurface equipment.

The interrogate type circuits are connected as inputs to the surface circuits. Thus, when the appropriate signal is given to the decode circuit, the interrogate signal from the subsurface unit is operated upon by the surface logic circuits and an appropriate output signal is produced.

Consequently, it is an object of this invention to provide a communication and control system that can communicate with and control remote equipment from a control station.

Another object of this invention is to provide a communication and control system that can communicate with underwater equipment from a control station which is above the water surface.

Another object of this invention is to provide a communication and control system which has high reliability, relatively simple construction and a small space requirement.

These and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the attached drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of the communications and control system of the instant invention.

FIG. 2 is a schematic and block diagram of the surface control circuitry of the system and is directed to the switching and coding portion of the circuit.

FIG. 3 is a schematic diagram of error detection circuits which prevent improper operation of the system connected to the control circuitry shown in FIG. 2.

FIG. 4 is a logic circuit diagram for a status receiver circuit.

FIG. 5 is a logic circuit diagram for a status checking circuit.

FIG. 6 is a logic circuit diagram for an analog signal detector circuit.

FIG. 7 is a schematic and block diagram of the subsurface control circuitry of the system and is directed to the switching and coding portion of the subsurface circuit.

FIG. 8 is a logic circuit diagram for a status indicator circuit and a status check indicator circuit and is controlled by the circuitry shown in FIG. 7A.

FIG. 9 is a logic circuit diagram for an analog signal indicator circuit.

DESCRIPTION OF PREFERRED EMBODIMENT Referring now to FIG. 1, there is shown a schematic block diagram of the communications and control system of the instant invention. Operators console 10 is mounted at the control point above the surface of the water. Console 10 includes, for example, a plurality of switches which are controlled by the operator. The switches are connected to master code generator transmitter 21 by means of diodes 11, 12, and 13. Each of the diodes is connected to different functional switches at console 10 as will be explained relative to FIG. 2. Diodes 11, 12 and 13 prevent various signals from being transmitted from the console to the code generator 21. In addition, diodes ll, 12 and 13 prevent interaction of the several switches included in console 10.

Delay element 16 is connected to the anode of diode l3 and receives a signal when one of the switches in console 10 is activated. Similarly, delay element 15 is connected to the anode of diode 12 and receives a signal when another one functional switch in console 10 is activated. Delay element 14 is connected in common to the cathodes of each of diodes ll, 12 and 13 to receive a signal when any one of the diodes is rendered operative by the application of a signal thereto from console 10.

The outputs of delay elements 14, and 16 are supplied to one-shot circuit 20. The output of one-shot is connected to code generator 21. As will be seen hereinafter, a signal from one-shot 20 causes the coded signal arrangement in master code generator 21 to be stored in a memory section thereof. False code detector 22 is connected to master code generator 21. False code detector 22 includes a logic network which produces a signal when an improper code is provided at code generator 21. The output of false code detector gate 17 are connected to the input of delay elements 14 and 15.'Thus, an inhibit signal is supplied to one-shot 20 when signals are concurrently applied to the inputs of delay elements 14 and 15 and 16 or when a false code is detected by false code detector 22.

The desirability of preventing one-shot 20 from effecting the storage of a coded signal arrangement in the memory section of code generator 21 when a false code is detected is obvious. As will become apparent hereinafter, it is desirable to inhibit, the operation of one'shot 20 when two mutually exclusive signals are produced at console 10. For example, in the event that the operator closes two switches requiring repugnant operations, gate 17 produces a signal via diode 18 which inhibits the operation of one-shot 20 as well as the operation of delay elements 15 and 16.

A timing network is also utilized to provide an inhibit signal. to prevent the operator from activating more than one ormore switches too rapidly. That is, attempting, even inadvertently, to initiate one function before the completion of a prior function is prohibited. The anodes of diodes 98 and 99 are connected to the anodes of diodes 12 and 13 to receive signals from console 10. Diodes 98 and 99 form an OR gate to supply signals to delay element 97. Delay element 97 is'connected to flip-flop 96. One output of flip-flop 96 is connected to timer 95. An output of timer 95 is connected to another input of flip-flop 96 to return flip-flop 96 to its original condition prior to the application of the signal from delay element 97. The output of flipflop 96 is connected to inhibit inputs of one-shot 20 and delay elements15 and 16.

The output of master code generator 21 is connected to output cable 24. Cable 24 comprises N conductors where the number N is determined by the number of functions which are to be transmitted. Since the signals produced by code generator 21 are binary in format, the value of N is determined by the formula 2"l P where F equals the number of functions. Thus for example, four conductors (N 4) will permit control of 15 functions.

Cable 24 is connected, via cable portion 24A to the surface units: In particular, cable 24A is connected to a decoder in each of the signal channels. The channels may be identical or may perform different functions. If the channels perform different functions, then the logic circuitry included therein will differ. For example, in logic circuit 26, decoder 25 is connected to cable 24A. Decoder 25 operates to interpret and decode the signals supplied thereto by code generator 21 via cable 24A. In accordance with the internal connections of decoder 25, an activating signal representative of the input signals is produced at the output thereof. The output signal produced by decoder 25 is supplied to an input of logic circuit 26. Another input of logic circuit 26 is connected to a status line connected to cable 67 which is connected to the subsea units as described hereinafter.

The outputs of logic circuit 26 of the status channel receiver are connected to driver circuits 27 and 28. Driver circuits 27 and 28 are typical amplifier circuits and logical .circuitry to produce compatible voltage levels and polarities. The driver circuits are connected to indicators 29 and 30, respectively. Typically, indicators 29 and 30 are pilot lights or the like which are selectively energized by application of a voltage signal thereto by the associated driver circuit.

For purposes of example, it is assumed that channels 2 and 3, additional status channel receiver circuits, are

identical to the status channel 1 receiver. For convenience, the internal circuitry therein is not repeated. However, each of these status channels would include a decoder 25 and a logic circuit 26 as well 'as driver circuits and output indicating means. The decoder in each of these channels is connected to cable 24A to receive coded selection signals. In addition, the logic circuit in each of the channels is connected to status line 678 which is connected to status line cable 67 and operative to receive status signals from the subsurface equip- 'ment.

In addition, a go, no-go status receiver channel is shown. This channel includes decoder 31 which is connected to cable 24A and logic circuit 32 which is connected to cable 678 and to an output of decoder 31. Decoder 31 selects the channel in response to the coded signals on cable 24A and logic circuit 32 operates on the status signal supplied on cable 67A.

receiver channel 2 is indicated and is identical to the i go, no.-go status receiver channel previously described. As is the case in any of the channel descriptions, the number of channels is illustrative only and not meant to be limitative.

Analog receiver channel 1 includes decoder 37 and switching circuit 38 connected to indicator 39. In the analog receiver channel, decoder 37 is connected to cable 24A to receive the coded selection signals whereby the channel is selected. The output of decoder 37 is supplied to switching circuit 38 as an enabling input thereto along with another input supplied along analog line 66 from the subsea equipment. Indicator 39 may be a light or meter or the like. Analog receiver channel 2 is substantially similar to analog receiver channel 1.

As noted supra, this system includes a plurality of 7 identical channels or, as suggested, a plurality of channels serving different functions may be utilized. The numbers and types of channels will, of course, influence the number of lines which are required between the surface and subsurface units. For example, if the analog receiver channels were replaced by status channel receivers or the like, the analog lines 66 could be eliminated. This would reduce the number of lines connected between the surface and subsurface units.

The subsea portion of the control system includes slave code generator 21'. This code generator is substantially similar to master code generator transmitter 21 in the surface unit. Code generators 21 and 21 are connected via cable 24 which, as noted, includes a plurality of N conductors. The output of code generator 21' is connected to cables 40 and 40A. Cable 40 is connected to circuitry which produces command signals to remote output equipment. The remote equipment is represented by block 76 and receives signals from command receiver channels, numbers 1, 2 and 3. Receiver channel 1, represented by dashed outline 73, includes decoder 69 which is connected to cable 40. Decoder 69 may be similar to decoder networks 25 and 31 in the surface unit. The output of decoder 70 is connected as an enabling input to logic circuit 70. Another input to logic circuit 70 is supplied by cable 68 which is connected to the output of gate circuit 19 in the surface unit. Cable 68 is connected via cable 68A to other command channels including command receiver channels 2 and 3 represented by dashed outline'74 and 75. The channel represented by block 74 included decoder 71 which is connected to cable 40 and logic circuit 72 which is connected to cable 68A. The output of decoder 71 is also connected as an input to logic circuit 72. The circuitry contained in the receiver channel represented by block 75 is substantially similar to the other receiver channels. The output signals supplied by logic circuits 70, 72 and the like are supplied directly to the remote equipment. Generally, a separatelogic circuit signal is supplied to a separate piece of equipment located at the subsurface location.

Through suitable means, represented by block 49, status signals from the remote equipment are supplied to status channel transmitters. Status channel transmitters, numbers 1, 2 and 3 are represented by blocks 50, 51 and 52 in dashed outline. Status channel transmitter 50 includes a signal process circuit 42 which receives the status signal from the remote equipment and operates thereon to make the signal compatible to the remainder of the circuitry. The output from signal process circuit 42 is connected to gate circuit 43. Another input of gate circuit 43 is connected to the output of decoder 41. Decoder 41 is connected to cable 40A to detect and decode the signal supplied thereto by slave code generator 21 The output of gate circuit 43 is connected via diode 44 to status line 67 which is connected to logic circuits in the surface unit.

Likewise, the circuitry in status channel transmitter 51 receives a signal at signal process circuit 46 from status signal circuitry 49. The output of signal process circuit 46 is connected to an input of gate circuit 47. Another input of gate circuit 47 is connected to the output of decoder 45. Decoder 45 is connected to cable 40A and detects and decodes the signal supplied on cable 40A. The output of gate circuit 47 is connected via diode 48 to cable 67. Diodes 44 and 48 prevent interaction of signals from one channel with the operation of another channel.

Status channel transmitter 3 represented by block 52 operates similarly to channel transmitters 50 and 51 and includes similar circuit components. Status channel transmitter 52 and other status channel transmitters (not shown) are connected to supply signals to cable 67.

Go, no-go signals from remote equipment are supplied by suitable means 60. The signals are supplied ,from circuit 60 to signal process circuit 55. The output of signal process circuit 55 is connected to an input of gate circuit 57. Another input of gate circuit 57 is supplied by the output of decoder 56. Decoder 56 has the input thereof connected to cable 40A and detects and decodes the signals supplied on the cable. The output of gate 57 is connected via isolation diode 58 and cable 67A to cable 67. Go, no-go status channel transmitters 53 and 54 are substantially identical. In addition, additional status channel transmitters may be provided.

Analog status signals from remote equipment are supplied by suitable means 61. Signals from analog status signal circuit 61 are supplied to analog channel transmitters 59 and 62. Analog channel transmitter 62 includes analog signal process circuit 63 which receives a signal directly from the remote equipment 61. The output of analog signal process circuit 63 is connected to switching circuit 65. Another input of switching circuit 65 is connected to decoder 64. The input of decoder 64 is connected to cable 40A to permit detection and decoding of signals supplied on cable 40A. The output of switching circuit 65 is connected to cable 66 which is returned to the surface unit. Analog channel transmitter 59 and other channels are connected to cable 66 via cable 66A.

Thus, the operation of the system shown in FIG. 1 is controlled by console 10. The operator activates the appropriate switches whereby signals are applied to the master code generator transmitter 21. Assuming that a false code is not detected and that an improper operation of switches has not been made by the operator, code generator 21 produces a signal on cable 24. The signal on cable 24 is supplied to code generator 21 and, via cable 24A to decoders 25, 31 and 37 in the surface unit. Slave code generator 21', in response to the signal on cable 24 produces a coded output on lines 40 and 40A which is identical to (or at least functionally equivalent to) the signals supplied on line 24A. As noted, the signals supplied on lines 24A, 40 and 40A represent the particular channel which has been selected by the operator at console 10. The decoders, both surface and subsurface, are arranged to detect the signals supplied on the associated cable. Thus, the signal on the code cables will cause one specific circuit loop to be completed. For example, if a command has been given by operator action at console 10, a signal will be supplied along line 68 and cable 68A to the command channels. The appropriate signal will also be provided by code generators 21 and 21' so that the code signal can be detected and decoded. The combination of a command signal and a decode signal operating in concert will cause the logic circuit in one of the command receiver channels to operate and produce a command signal to the remote equipment.

Likewise, if a status or analog signal was desired, the coded signal would be applied along cables 24A and 40A and would activate the appropriate decoder networks. The status signals from the subsurface remote equipment would then be transmitted via the appropriate analog line 66 or status line 67 to the surface unit. The decode signal at the appropriate surface receiver channel would enable the appropriate circuitry in the surface unit and the associated indicator or output device would be rendered operative.

Thus, it is seen that a plurality of subsurface units can be'controlled by and monitored by surface units while requiring a minimal number of interconnections between the surface and subsurface units.

Referring now to FIG. 2 there is shown a more detailed schematic diagram of the switching and coding portion of the control circuitry for the instant invention. The control circuitry is defined as including the operator console, the code generator and the associated circuitry. It does not include the subsurface control circuitry nor does it include the logic circuitry related to the remote equipment or the indicating means associated therewith. It should further be noted that this description is for purposes of convenience in describing the circuitry rather than for the purpose of defining the circuit or its function.

In FIG. 2, as well as in all of the figures, similar components bear similar reference numerals. Thus, console 10 is shown connected to master code generator transmitter 21. In the embodiment shown, console 10 includes a plurality of pushbutton switches 100 which represent the operator controls. EAch of the pushbutton switches 100 is a ganged switch some of which may have more contacts than others in order to effect control over certain functions of the system. For example, each switch 100A is-a single ganged switch having two pairs of contacts and which is utilized to determine the status of a particular function, for example, annulus pressure. When the switch is closed, an electrical connection is effected between a particular reference signal, in.thi's case ground potential and an associated terminal of code generator 21. Simultaneously, a connection is effected between another reference signal, for example, volts and one-shot circuit via delay circuit 14. EAch of the switches similar to switch 100A effect similar connections between reference signals and delay circuit 14 or an input terminal of code generator 21.

Additional switches 1008 are similar to switches 100A except that each switch 1008 has six pairs of contacts and is related to a system function which requires more than a single operation to be controlled by a single switch. For example, each switch 1008 can be connected to a master valve or a cross-over valve or the like. In operation of the valve, it is desirable to be able 15 (FIG. 1). Thus, the upper pair of connections of switch B controls the OPEN function.

On the contrary, closure of the CLOSED portion of switch 100B (e.g. the middle pair of connections) connects a +15 volt signal source to delay circuit 14, an input of gate 17, an input of delay circuit 97 and the input of the CLOSED circuit 16. Closure of the STATUS portion of switch 100B (e.g. the bottom pair of connections) provides a +15 volt signal to delay circuit 14 only. Furthermore, closure of any of these switch portions provides a ground level signal to input line 21B of code generator 21.

Referring now to code generator 21, there is shown a v typical diode matrix circuit. This diode matrix requires a concurrency of signals on lines associated with each diode to render the diode conductive and to affect a signal selection thereby. Each of the input lines 21A, 21B, 21C and so forth is connected to the cathode of a plurality of the diodes which form the matrix. The anodes of the diodes are connected to a +15 volt source via resistors 101. Resistors 101 limit the current flow when the matrix diodes are conductive. Additionally, the resistors supply a suitable voltage to the J K inputs of flip-flops A-D to assure a distinct binary voltage level at the inputs except when a matrix diode is conductive.

The anodes of the diodes in the matrix are further connected to output lines 218, 21T, 2lU and the like. Output lines 218, 21T and the like through to 212 are connected in related pairs to the K, .I inputs of flip-flop circuits which will be described hereinafter. The flipflop circuits provide a memory for storing the information supplied thereto by the diode switching matrix. In addition, the output lines 218 21Z are connected to inputs of false code detector circuit 22 which will be described hereinafter but which functions to inhibit operation if an improper signal is generated by the matrix.

The operation of the diode switching matrix is typical. That is, closure of a switch inconsole 10 will effect a signal selection by rendering certain diodes operative. For example, consider switch 100R which is typical. of any switch 100A. Closure of switch 100R will supply a +15 volt signal to delay circuit 14 (see FIG. 3) via diode 11. In addition, a ground potential signal will be supplied via input line 21H to the cathodes of the diodes connected to line 21H. Inasmuch as a +l5 volt signal is supplied to the anodes of these diodes via output lines 21?, 21V, 21X and 21Y, these diodes will be rendered conductive. In essence, forward conduction of these diodes effectively clamps output lines 21T, 21V, 21X, and 21Y to ground. The remaining output lines 218, 21U, 21W and 21Z are not affected and continue to exhibit a +15 volt output signal. It will be further observed that the output lines may be considered as operative pairs, namely 21S and 21T, 21U and 21V and the like. It is seen that the matrix is arranged so that operation of any switch 100 will cause at least one line of each operative pair of output lines to be clampedat ground potential while the other line of the operative pair remains at the +15 volt level. Thus, a binary coding is effected by the diode switching matrix.

As suggested supra, output lines 218 through 212 are connected to false code detector circuit 22. False code detector circuit 22 includes a plurality of logic gates. A

first level of logic includes a plurality of gates 102. Gates 102 are, in fact, inverters which invert the volt signal (or the ground signal) which is applied to the particular gate 102 to produce an output signal representative thereof. A second level of logic includes a plurality of gates 103. Gates 103 are NAND gates which have two inputs. Each input of a NAND gate 103 is connected to an output of a different one of gates 102. Thus, an operative pair of output lines, for example 21Z and 21Y is connected individually to a separate one of inverters 102. The outputs of inverters 102 are connected, in operative pairs, to the inputs of NAND gates 103. In operation NAND gates 103 require two high inputs to produce a low output signal. A low level output signal is supplied to the input of inverters 104 which represent another level of logic. The output of each of inverters 104 is connected to the anode of one of diodes 105. The outputs of diodes 105 are connected together and supplied to the anode of diode 23 (see FIG. 3). In fact, diodes 105 may be considered to be a further level of logic and to represent a single OR gate.

In operation, the signals supplied by the diode matrix are supplied to the false code detector 22 via output lines 218 through 21Z. These signals are inverted by the first level of logic represented by inverter gates 102. The second level of logic, namely gates 103, operates on the inverted signals produced by gates 102 in operative pairs. Thus, if a false code has not been generated, each of the gates in logic level 103 will receive both a high and low level signal and will produce a high level output signal. The high level signal produced by gates 103 will be inverted by inverter gates 104. The output signals from the inverters of logic level 104 will normally be low level signals whereby diodes 105 will be rendered non-conductive.

However, in the event that a false code is generated by the diode matrix, one of the operative pairs of output signals will have two identical signals supplied thereby. This condition will produce an output error signal. If the two input signals supplied on an operative diode 105 conductive. Conduction by diode 105 will producean error signal. The error signal will be supplied along the inhibit line via diode-23 to inhibit operation of OPEN circuit 15, CLOSE circuit 16 and DELAY circuit 14 (see FIG. 3). By suitable logic circuitry, a condition of two binary 1 inputs can produce an error signal.

An error or inhibit signal by false code detector 22 causes a signal to be supplied to OPEN control circuit 15, CLOSE control circuit 16 and DELAY circuit 14 to inhibit the operation thereof. That is, if a malfunction is detected by false code detector 22, the operation of the circuits will be inhibited whereby erroneous operation will be prevented.

. In addition, other inhibit type signals are provided to prevent improper operation of the system. For the circuits involved, reference is made to' FIG. 3. For example, gate 17 has two inputs connected to console 10.

EAch of the inputs of gate 17 is connected to a common connector associated with the function control switches 1008. For example, one input of gate 17 is connected to a common connection on the CLOSE portion of switches 1008. Thus, whenever any of the function switches 10013 is operated so that the CLOSE operation is initiated, the +15 volt signal applied thereacross, in addition to being supplied to delay circuit 14, is also applied to an input of gate 17.

The other input of gate 17 is connected to a similar common conductor connected to all of the switch portions which relate to the OPEN function. Thus, when the OPEN switch is operated, a +15 volt signal is applied to the other input of gate 17.

Referring to gate 17 in detail, it is seen that each of the inputs is connected to the anode of diode 108 or 109 via current limiting resistors 106 or 107 respectively. The cathodes of diodes 108 and 1 09are connected to the base electrodes of NPN transistors Q12 and Q13, respectively. More particularly, the base of transistor Q12 is connected to the CLOSE conductor while the base of transistor Q13 is connected to the OPEN conductor of console 10. v

The emitter electrode of the transistor Q13 is con.- nected to ground while the collector of transistor Q13 is connected to the emitter electrode of transistor Q12. The collector electrode of transistor Q12 is connected via resistor 110 to asuitable source, for example +15 volts regulated. The collector of transistor Q12 is further connected via resistor 111 to the base of NPN transistor Q11. The emitter of transistor 011 is connected to ground while the collector thereof is connected, via resistor 112, to the +15 volt source. The collector of transistor Q11 is further connected to the anode of output diode 18 which has the cathode thereof connected to the cathode of diode 23 from false code detector 22 (see FIG. 2).

In operation, the input end of input resistor 106 is connected to the common line interconnecting the OPEN portions of switches 1008. Similarly, the input end of input resistor 107 is connected to the common connector which connects the CLOSE portion of switches 1008. As noted supra, closure of one of these portions of switches B supplies a +15 volt signal to the respective common line. In the event that normal operation occurs, for example, one OPEN or one CLOSE switch portion is operated, a +15 volt signal is applied via input resistor 106 or 107 and the appropriate blocking diode 108 or 109 to the base of transistor Q12 or 013. However, application of a positive signal to the base of only transistor Q12 or Q13, individually, is insufficient to cause current flow through this circuit branch inasmuch as transistors Q12 and Q13 are connected in series and non-conduction of either one of them causes an open circuit. With either transistor Q12 or Q13 inoperative, the potential supplied at the base of transistor 011 via resistors 110 and 1 1 l is sufficiently positive to render transistor Q11 operative. When transistor Q1 1 is operative, the collector thereof is, effectively, clamped at ground potential.

The ground potential is supplied to the anode of diode 18 wherein diode 18 is effectively cutoff and an inhibit signal is not produced. This output condition is indicative of the appropriate operation of a single OPEN or CLOSE switch portion.

On the contrary, if an OPEN and a CLOSE switch portion are inadvertently operated simultaneously, the volt signal will be supplied, via the appropriate input circuits, to the bases of transistors Q12 and Q13 simultaneously. The application of the relatively positive signal to the bases of these two transistors will render the transistors operative wherein the collector or transistor Q12 is effectively clamped to ground potential. With the collector of transistor Q12 clamped to effective ground potential, transistor Q11 is rendered non-conductive. When transistor Q11 is nonconductive, the output voltage detected at the collector thereof rises to +15 volts (applied by the 15 volt source) whereupon a positive signal is supplied to and conducted by diode 18. This positive signal is effective to provide an inhibit signal to the other circuitry.

This, it is shown that error detecting circuits are provided to detect a malfunction in the diode matrix to eliminate a false code (detection by false code detector 22) and to detect the inaccurate operation of both an OPEN and a CLOSE switch portion substantially simultaneously (detection by gate 17). These circuits detect errors in both the electronic components and, as well,

in operator techniques.

Another inhibit signal is selectively produced by I timer 95. Timer 95 is ultimately controlled by signals applied when the OPEN or CLOSE portion of any switch 1008 is operated. Thus, the common connector on the OPEN portions of switches 1003 is connected to theanode of diode 99. Similarly, the common connector connected to the CLOSE portions of switches 1008 is connected to the anode of diode 98. The cathodes of diodes 98 and 99 are connected together and to a delay circuit comprising resistor 114 and a capacitor 115 via input resistor 116. One end of the delay circuit is connected to the cathode of zener diode 117 while the other end of the delay circuit is connected to ground. The anode of diode 117 is connected to the base of NPN transistor Q10 which has the emitter thereof connected to ground. The collector of transistor Q10 is connected via resistor 118 to the base of transistor Q14 which has its emitter connected to ground. The collector of transistor Q10 is further connected to a +15 volt source via resistor 119 along with the collector of transistor Q14 which is connected to the +15 volt source via resistor 120. It will be seen from this configuration, that transistors Q10 and 014 form a flipflo 'Fhe base of transistor 010 is connected via resistor 121 to the cathode of diode 122 and the anode of diode 113. The cathode of diode 113 is connected to the cathodes of diodes 23 and 18 whereby it is connected to the inhibit line. The anode of diode 122 is returned to the collector of transistor Q14 and selectively supplies a signal to the base of transistor Q10 and to the anode of diode 113 as will be seen hereinafter. The base of transistor Q14 is further connected to the anode of coupling diode 123 via resistor 124. The anode of diode 123 is connected to one base (B1) of unijunction transistor 015. This base electrode of unijunction transistor Q15 is further connected to ground via resistor 125. The other base electrode of transistor Q15 is returned to the +15 volt source via resistor 126. The emitter of unijunction transistor Q15 is connected to ground via capacitor 127 andto the collector of transistor 014 via resistor-128.

In operation, a positive signal is supplied to the anode of diodes 98 or 99 which operate as an OR gate. This circuit is not discriminatory against the application of both open and close signals simultaneously. The signal from the appropriate switch in console 10 supplies a signal of +15 volts to the RC network 97 comprising resistor 114 in capacitor 115. When capacitor 115 has charged sufficiently, reverse diode or zener diode 117 breaks down and conducts therethrough. Thus, a relatively positive signal is applied to the base of previously non-conductive transistor Q10. This positive signal is sufficient to render transistor Q10 conductive. When transistor Q10 is conductive, the collector thereof is clamped at substantially ground potential whereby this potential is provided at the base of transistor Q14 via resistor 118. The substantially ground potential at the base electrode of transistor Q14 causes this transistor to become non-conductive. When transistor Q14 is non-conductive, the potential at the collector thereof switches from substantially ground to a positive voltage. This positive signal is applied at the emitter electrode of unijunction transistor Q15 across capacitor 127. Consequently, the potential at the emitter electrode of transistor Q15 rises exponentially. When the potential at the emitter electrode of transistor Q15 reaches the threshold value thereof, transistor Q15 conducts. Conduction occurs from the emitter electrode to the B1 base electrode. Thus, capacitor 127 is effectively discharged through transistor Q15 and resistor and the discharge time period for capacitor 127 is determined.

Immediately upon transistor Q15 being rendered conductive, a relatively positive voltage signal is applied via diode 123 to the base of transistor Q14. This positive signal renders transistor Q14 conductive whereby the collector thereof is effectively clamped at ground. Thus, the emitter electrode of transistor Q15 is also clamped to ground potential whereby transistor Q15 is rendered non-conductive. Furthermore, the positive potential at the base of transistor Q14 is applied to the collector of transistor Q10. Furthermore, the ground potential at the collector of transistor Q14 is applied tothe base of transistor Q10 via diode 122 and resistor 121. In actuality, diode 122 is effectivelynon-conductive due to the relatively negative potential at the anode thereof but the positive signal applied to the base of transistor 010 by diode 122 is terminated.

As the potential at the base of transistor 010 is reduced due to the termination of the input signal applied via diodes 98 and 99 as well as the removal of the positive signal which had been supplied at the collector of transistor Q14, transistor Q10 is rendered non-conductive. Thus, the flip-flop networkassumes its initial condition. Clearly, delay unit 97 permits flip-flop 96 to be set or reset at a time somewhat subsequent to the operation-of the detector circuits which can detect an improper signal. Consequently, the error detector circuits can inhibit the operation of the circuit if an error is detected. Moreover, flip-flop 96 effectively controls an inhibit signal which can be provided via diode 113 to inhibit the OPEN and CLOSE circuits 15 and 16, respectively, to prevent the application of a second signal prior to the completion of the action required by the first signal. Timer 95 controls the status of flip-flop 96 and automatically resets flip-flop 96 to its initial condition after a pre-determined time. At that time,

and only at that time, the operator may initiate a new operation.

Another control circuit includes delay circuit 14 and one-shot or clock circuit 20. The input of delay circuit 14 is supplied via diodes 11, 12 and 13 (see FIG. 2). The anodes of diodes 11, 12 and 13 are connected to the common busses associated with the OPEN, CLOSE or STATUS lines of the respective switches. When the switches are closed, a +15 volt signal is applied to the anode of diode 11, 12 or 13. The cathodes of these diodes are connected together as an OR gate. The RC delay network comprising resistor 131 and the parallel combination of resistor 129 and capacitor 130 is connected to the cathodes of diodes 11, 12 and 13. The RC network is further connected to ground. The junction between input resistor 131 and the parallel combination is connected to the base of NPN transistor Q4. The collector of transistor O4 is connected to a +15 volt regulated supply via resistor 132. The emitter electrode of transistor Q4 is connected to ground via Zener diode 133. Zener diode 133 is designed to effectively clamp the emitter of transistor Q4 at an offset voltage which is equivalent to the threshold voltage of the Zener diode. The emitter of transistor Q4 is further connected to a +15 volt source via resistor 135.

The collector of transistor O4 is connected via resistor 134 to the base of transistor Q3. PNP transistor Q3 has the emitter thereof connected directly to the +15 volt source. The collector of transistor Q3 is connected to ground via the series connected resistors 136 and 137.

The junction of resistors 136 and 137 is connected to ground via the series connected combination of resistor 138 and capacitor 139. The junction of resistor 138 and capacitor 139 is connected to the cathode of Zener diode 140. The anode of Zener diode 140 is connected to the base of transistor Q16. The emitter of NPN transistor Q16 is connected to ground while the collector of transistor Q16 is connected via resistor 141 and capacitor 142 to the junction between resistors 136 and 137. A further delay network is connected across the emitter-collector circuit of transistor Q16. This time delay circuit includes resistor 143 and capacitor 144 connected in parallel. The delay circuit is connected between ground and. the junction between resistor 141 and capacitor 142.

The base of transistor O2 is also connected to the common junction of resistors 141 and 143. The emitter of NPN transistor Q2 is connected to ground while the collectorthereof is connected to the +15 volt source via resistor 145. The collector of transistor O2 is further connected to the base of transistor Q1 via resistor 146. The emitter of transistor Q1 is connected directly to ground while the collector of NPN transistor Q1 is connected to the +15 volt source via resistor 147. The collector of transistor 01 is further connected, as an output terminal of clock circuit 20, to the clock input of the memory associated with the diode matrix and described hereinafter.

The purpose of clock circuit 20 is to provide a synchronized clock signal to the memory portion of code generator 21 so that a synchronized operation thereof can occur. The synchronization is required in order to provide operation of the system which is not dependent upon the operators dexterity or the, like.

Moreover, the delay circuit prevents the clock circuit from operating until all contact bounce of the console switches is eliminated.

When any of the switches in console 10 are operated, a +15 volt signal will be passed therethrough and connected to the anode of diode l1, 12 or 13. The output of the OR gate comprising the diodes is connected to the RC delay network comprising resistors 129 and 131 and capacitor 130. After the typical exponential charging period of capacitor 130, a substantially positive signal is applied at the base of transistor Q4. The substantially positive signal is operative to render transistor Q4 conductive. When transistor O4 is conductive, a signal of approximately 6.2 volts (the threshold value of Zener diode 133) is applied to the base of transistor Q3 via resistor 134. The signal supplied to the base of transistor O3 is negative relative to the emitter voltage. Thus, transistor Q3 is conductive and a positive voltage is applied across resistor 137. The positive voltage is also applied across the series combination of resistor 138 and capacitor 139 to cause a spike-like signal to be applied via Zener diode 140 to the base of transistor Q16. This spike-like signal will render transistor Q16 conductive for the duration of the signal. With transistor Q16 conductive, the base of transistor Q2 is effectively clamped at ground potential whereby transistor O2 is rendered non-conductive. When transistor Q2 is non-conductive, a relatively positive potential is applied to the base of transistor Q1 whereby transistor Q1 is conductive and a substantially ground potential signal is supplied to the memory portion of code generator 21. The signal normally supplied to the memory circuit is ground potential. A positive signal is supplied to the memory only to indicate the operation of a switch at console 10.

When transistor Q3 is rendered conductive by application of a signal due to operation of a switch at console 10, a positive signal is applied to the base of transistor Q2 via capacitor 142. This signal is passed through the delay circuit comprising resistor 143 and capacitor 144 and renders transistor Q2 conductive. When transistor Q2 is conductive, ground potential is applied to the base of transistor Q1 which becomes non-conductive. When transistor Q1 is non-conductive, a positive signal is supplied to the clock terminal of the memory.

However, when transistor Q3 is conductive, the +15 volt signal at the collector thereof produces a positive signal at the base of transistor Q16 as described supra. When transistor Q16 is rendered conductive, the base of transistor Q2 is clamped to ground potential thereby making this transistor non-conductive. Thus, it is seen that a positive signal applied to the base of transistor Q4 will produce a spike signal (or a signal with a very small duration, for example 50 milliseconds) at the output of clock circuit 20, namely the collector of transistor Q1. The output signal has both relatively short rise time and fall time as controlled by transistor Q16 and the associated delay network.

The open and close control circuitry is comprised of two substantially identical circuits. The OPEN circuit 15 is connected to the common buss for the OPEN portions of switches 1003 by means of coupling resistor 148. Resistor 148 is connected to a delay network comprising resistor 148 and the parallel combination of resistor 149 and capacitor 150. The other end of the delay network is connected to ground. The junction between resistor 148 and resistor 149 is connected to the cathode of Zener diode 151. The anode of diode 151 is connected to the base of transistor 05. The emitter electrode of transistor O is returned to ground. The collector electrode of transistor O5 is connected via resistor 152 to a volt source. In addition, the collector electrode of transistor O5 is connected to an OPEN control line which is connected to the subsurface unit as described hereinafter.

In the CLOSE circuit 16, the common buss connected to the CLOSE portions of switches 100B is connected via coupling resistor 153 to a delay network comprising resistor 153 and the parallel combination of resistor 154 and capacitor 155. The opposite end of the delay network is connected to ground. The junction between resistors- 153 and 154 is connected to the cathode of Zener diode 156. The anode of diode 156 is connected to the base of transistor Q6. The emitter electrode oftransistor O6 is connected to ground. The collector electrode of transistor O6 is connected to a +15 volt power supply via resistor 157. In addition, the collector of transistor O6 is connected to the CLOSE control line which is connected to subsea circuitry as described hereinafter.

In operation, the OPEN and CLOSE circuits are substantially identical. A signal is supplied upon the OPEN or CLOSE line to the associated input coupling resistor 148 or 153. For purposes of discussion, OPEN circuit 15 will'be described. However, it is understood that operation of CLOSE circuit 16 is substantially identical. The application of an input signal, namely a +15 volt signal, produces a signal at the cathode of diode 151 after a short delay controlled by the RC time constant ofthe delay network comprising resistors 148 and 149 and capacitor 150. When the. threshold level of diode 151 is achieved, it conducts in the reverse direction and a relatively positive signal is applied to the base of transistor Q5. When transistor Q5 is rendered operative by the application of a positive signal to the'base thereof, a ground'potential signal is supplied to the collector of transistor Q5 and, ultimately, to the subsea unit/ As noted, the operation of CLOSE circuit 16 is identical and, with the application of a +15 volt signal at the input thereof, a low level or ground potential output signal will be supplied to the subsurface unit.

A plurality of inhibit circuits are connected to receive inhibit signals from diodes 23, 18- and 113 described supra and connected to error detecting circuits or inhibiting circuits. The inhibit circuit for OPEN circuit 15 comprises input resistor 158 which is connected to the base of transistor 07. The emitter of NPN transistor 07 is connected to ground while the collec- The inhibit circuit related to delay circuit 14 or clock 20 comprises input resistor 162 which is connected to the base of transistor 09. The emitter of transistor 09 is connected to ground while the collector thereof is connected via resistor 163 directly to the base of transistor Q4.

In operation, each of the inhibit circuits operates identically. In the absence of an inhibit signal, a low level signal is applied to the base of transistors Q7, Q8 and Q9. Consequently, these NPN transistors are rendered non-conductive and ineffective. However, with the application of a positive signal via any one of diodes 23, 18 or 113, a positive signal is applied to the base of transistors 07, Q8 and Q9. These transistors are then rendered conductive whereby the input lines are effectively clamped to ground and input signals supplied on.the OPEN or CLOSE input lines are ineffectual. Since the positive signal at diodes 23, 18 or 113 is representative of an error condition or' another operation in effect, it is desirable to inhibit operation of circuits 15, 16 and 20.

Referring again to FIG. 2, the memory associated withcode generator 21 comprises four .IK flip-flops. Each of these .IK flip-flops has the clock input terminal thereof connected to the output of clock circuit 20, viz, the collector of transistor Q1. In addition, each of the flip-flops has the J-K inputs thereof connected to an operative pair of output lines of the diode matrix. For example, flip-flop A has the K input connected to output line 215 while the J input is connected to output line 21T. Similarly, flip-flop B has the K input connected to output line 21U while the J input is connected to output line 21V. Flip-flop C has the K input connected to output line 21W while the J input is connected to output line 21. Finally, flip-flop D has the K input connected to output line 21Y and the J input is connected to output line 212. In addition, suitable input signal sources are supplied whereby operating potential is provided to the flip flops.

Th e outputs of flip-flops A, B, C and D are labeled Q and Q. However, for convenience, the outputs are given the designation of the flip-flop with the barred and unbartgd symbol. For example, flip-flop A has output A and A. The outputs of flip-flops A through D are the output lines of code generator 21. These outputs are connected to each of the individual logic circuits in the surface or above surface unit. However, in order to reduce the number of lines which are connected between the surface and subsurface units (and thereby reduce the number of wires which are required to interconnect the control and the remote unit), only the unbarred output signals, viz, signals A, B, C and Bare carried to the remote or subsurface unit.

In operation, the operator will manipulate one of the switches thereby initiating anoperation or function. Each of the switches is labeled so that the operator will understand and know which function he is performing. The operator can open, close, or detect the status of a valve located at the remote or subsea area. Other functions can be performed with other pieces of equipment at the remote locations.

As discussed above, closing of a switch 100 will supply a +15 volt signal via diode 11 to the input of delay circuit 14 which will initiate operation of clock circuit 20 under normal conditions. In addition, operation of a switch 100 will supply a ground signal to the cathodes of the diodes connected to the specific input lines of the diode matrix contained in code generator 21. Thus, the operation of a switch simultaneously initiates operation of delay circuit 14 and produces a coded signal arrangement at the J-K inputs of flip-flops A through D. Immediately upon entering the coded signal by the application of the ground signal on an input line, false code detector 22 determines whether or not an improper code exists. If the code is proper, no error signal is produced and an inhibit signal is not generated by false code detector 22 via diode 23.

Likewise, gate 17 is immediately effective to detect the impropriety of an OPEN and CLOSE switch being operated simultaneously. Again, if no error exists an inhibit is not generated via diode 18. In the event that either of these circuits generate an output signal indicative of a malfunction, the inhibit signal will inhibit the application of a signal to OPEN circuit 15 or CLOSE circuit 16 or 'to clock 20. If the unit is operating properly and there is no malfunction, delay circuit 14 completes its operation and supplies a signal to clock circuit 20. Clock circuit 20 produces a signal which is supplied via clock line to the clock input of flip-flops A, B, C and D of the memory in code generator 21. With the application of the clock signal, the inputs at the K and J input terminals are effectively switches into the flip-flops and the outputs A, A and the like are produced and available. That is, the K and J input terminals have the signals applied thereto by the diode.

matrix. However, these signals are not actually stored in the flip-flop memory until the application of a clock signal by clock circuit 20.

In the event that the switch 100 which was activated is merely a STATUS signal, the operation of the control circuit is substantially complete. That is, the code signals generated by the diode matrix are stored i1 1 the flip-flops AD and the appropriate code signals A, A, B, B and the like are now available to be applied to the remainder of the circuit to select the appropriate remote signal and to select the appropriate indicating circuit so that the remote equipment is monitored and the monitored signal is returned to the surface and displayed.

In the event that switch 100B was operated to perform the OPEN or CLOSE function, additional operations occur. The OPEN or CLOSE signal, as the case may be, is applied to gate 17 delay circuit 97 and the OPEN or CLOSE circuits l and 16, respectively. The operation of gate 17 has been described as an error detection circuit. It will be assumed that no error exists and the remainder of the circuit functions properly.

The OPEN or CLOSE signal is applied to the appropriate circuit and produces an output signal therefrom. This output signal is connected to the travelling conductors or lines which extend from the control to the remote equipment. It will be noted that the OPEN and CLOSE circuits include delay elements. The RC delay circuit in these channels is designed to produce a longer delay period than the delay period exhibited by delay 14 which is associated with the clock signal. This delay relationship assures that the clock signal will have been supplied to the code generator 21 to effect a storage of the code signal in the memory prior to the application of an OPEN or CLOSE signal to the remote equipment. Thus, there will be avoided any ambiguity which could occur if the clock signal and the control signal were supplied substantially simultaneously. In other words, the specific circuit to be operated has been selected prior to the control signal being applied thereto. This timing arrangement can be rather critical to avoid an ambiguity or an anomalous situation relative to the logic circuit operation.

Additionally, the OPEN and/or CLOSE signal is supplied to delay circuit 97. Delay circuit 97 operates to provide a signal to flip-flop 96 which controls timer 95. Delay circuit 97 is designed to have a longer delay than the delay exhibited by OPEN and CLOSE circuits 15 and 16 whereby these circuits will have been operative prior to the application of a signal to flip-flop 96. The application of a signal from delay circuit 97 to flip-flop 96 is effective to change the status of flip-flop 96 whereby an output signal is supplied via diode 113 which inhibits the operation of OPEN circuit 15, CLOSE circuit 16 and clock circuit 20. Thus, if the operator inadvertently manipulates an additional switch while a command is being processed, the subsequent input signal will be ineffective inasmuch as these circuits will have been inhibited due to the signal supplied by flip-flop 96. Moreover, flip-flop 96 is connected to timer circuit which is designed to reverse the condition of flip-flop 96 and to remove the inhibit signal from OPEN circuit 15, CLOSE circuit 16 and clock circuit 20 after a suitable delay period. Thus, the operator can manipulate the switches at console 10 to effect a second command or status check, but only after a first command sequence has been fully processed. This timing arrangement avoids ambiguity and overlapping of signals.

Referring now to FIG. 4, there is shown a schematicblock diagram of the logic circuitry included in one of the status receiver channels. This circuit includes decoder 25 and logic circuit 26 shown in FIG. 1. In the diagram, the gate circuits are, for the most part, NAND or NOR gates. The standard symbols are utilized for' NAND and NOR gates which may be integrated circuitry or discrete components.

Gate 300, a NAND gate, includes four input terminals. These input terminals are connected to the output lines of flip-flops A, B, C and D in the memory associated with diode matrix in code generator 21 (see FIG. 2). In the case of gate 300, t l ie inputs are connected to output lines A,E, C and D. The operation of gate 300 causes a binary 0 signal to be produced at the output thereof in response to binary I signals being supplied on all of the input lines thereof. A binary 0 at any input of gate 300 will cause a binary 1 to be produced thereby. Referring to the memory associated with code generator 21, it may be stated that the output I signals produced thereby are such that the following conditions exist:

It is to be emphasized of course, that the connections of gate 300 could be varied to detect any suitable coding arrangement. For example, in other channels in the plurality of status channel receivers, the gate similar to gate 300 will be connected to different input lines thereby to be activated or energized by different code combinations. In essence, gate 300 operates as a decoder.

The output of gate 300 is connected to both inputs of gate 301. TI-lus, gate 301 acts substantially as an inverter. That is, if each of the input signals supplied to gate 300 is a binary l a binary is produced at the output thereof. The application of a binary 0 to both inputs of gate 301 produces a binary l at the output thereof. Obviously, since the inputs of gate 301 are connected together, an inversion must take place relative to the input signal applied thereto.

Gates 302 and 303 are NOR gates. Each gate has a single .input connected to a separate valve position reply line which is connected to the subsurface unit. The inputs to gates 302 and 303 form a portion of the cable 67 (see FIG. 1) and represent the status lines whereby status signals from the subsurface equipment are transmitted to the surface unit. Again, the NOR gates operate as inverters. The output of gate 302 is connected to an input of each of gates 304 and 305. The output of gate 303 is connected to an input of each of gates 305 and 306. The output of gate 301 is connected to an input of each of gates 304, 305 and 306. Thus, operation of gate 304 is a function of the output signals produced by gates 301 and 302 while operation of gate 306 is a function of the outputs of gates 301 and 303. Operation of gate305 is a function of the output signals produced by gates 301, 302 and 303.

The outputs of gates 304, 305 and 306 are connected to the inputs of gates 307, 308 and 309, respectively. Gates 307, 308 and 309 are connected to operate as inverting NAND gates. That is, the inputs of each of gates 307, 308 and 309 are connected together and to the respective outputs of gates 304, 305 and 306 as discussed supra. Since the inputs of each of gates 307, 308 and 309 are connected together,.application of an input signal to gate 307 inherently supplies the identical signal to each of the inputs of this gate. Likewise, 7

identical signals are supplied to each of the inputs of gate 308 by gate 305. In addition, gate 309 has a common signal supplied to each of the inputs thereof from the output of gate 306.

The outputs of gates 307, 308 and 309 are connected to the cathodes of reverse diodes 326, 327 and 328, respectively. The anode of diode 327 is connected directly to one input of NOR gate 311. The anode of diode 326 is connected directly to one input of NOR gate 310 and one input of NOR gate 312. The anode of diode 328 .is connected to one input of each of NOR gates 312 and 313. Another input of gate 310 is connectedto the output of gate 313. The output of gate 311 is connected directly to an input of gate 312. The output of gate 312 is connected to one input of each of gates 313, 311 and 310. The output of gate 310 is further connected to an input of gate 313.

In addition, the output of gate 313 is connected to the base of transistor Q18 via a series circuit comprising inverters 317 and 318 and isolating resistor 319. Similarly, the output of gate 310 is connected to the base of transistor Q17 via inverters 314 and 315 and isolating resistor 316. The emitter electrodes of transistors Q17 and Q18 are connected to ground. The

collector electrode of transistor Q17 is connected to source 325 via indicator 321. In addition, the collector electrode of transistor Q17 is connected to ground via diode 322 and switch 324.

The collector electrode of transistor Q18 is connected to source 325 via indicator 320. In addition, the

collector electrode of transistor Q18 is connected to switch 324 via diode 323.

Switch 324 is a normally open switch which is used to test indicators 320 and 321 which may be pilot lights or the like. That is, when switch 324 isclosed, a circuit is completed from source 325, via the indicators and the associated diode 323 and 322 and switch 324 to ground. In this manner, each of the indicators can be checked for operability without applying any signal to the logic circuitry.

In standard operation, switch 324, as noted, is normally open whereby no signal is applied to the indicator lamps. With the application of a low level (binary 0) signal to the base electrodes, transistors Q17 and 018 are rendered non-conductive and lamps 320 and 321 remain inoperative. However, with the application of a high level (binary 1) signal to the base of either transistor Q17 or transistor Q18, the respective transistor is rendered conductive and a complete circuit is provided from source 325, respective indicator 321 or 320 and the associated transistor Q17 or Q18 to ground. Thus, when a binary 1 signal is supplied to the base of the switching transistor, at least one of indicators 320 and 321 is operated (i.e. illuminated) to indicate a particular system operation. The signals applied to the base of transistors Q17 and Q18 represent the signals supplied to the input of the logic circuitry.

As background to the understanding of this invention, it should be understood that a valve at the subsea equipment includes limit switches thereon. The limit switches are associated with the ends of travel of the valve. For example, when the valve is fully open or fully closed, a limit switch is operated to indicate the position of the valve. When the valve is in the fully open condition, a limit switch is triggered and causes a connection between indicating circuitry and ground.

Similarly, a limit switch is operated when the valve is in binary 1. With each of the signals supplied. to the decoder being a binary 1, the output of gate 300 is a binary 0. Since a binary 0 is applied to each of theinputs of gate 301, a binary 1 signal is produced at the output thereof. This binary 1 signal is supplied to the inputs of each of gates 304, 305 and 306 and operates as an enable signal. The output signal produced by these gates is dependent upon the signal supplied by gates 302 and 303. It is initially assumed that a binary 1 is supplied to the input of gate 302 and a binary O is supplied to the input of gate 303. Since gates 302 and 303 operate as inverters, the outputs therefrom area binary 0 and a binary 1, respectively. The binary 0 produced by gate 302 is applied to the inputs of gates 304 and 305. The binary 1 produced by gate 303 is supplied to inputs of gates 305 and 306, respectively.

The. binary 0 signal applied to the inputs of gate 304 and 305 causes these gates to produce binary 1 output signals. Gate 306 produces a binary 0 output signal inasmuch as each of the inputs supplied thereto is a binary Gates 307 and 308 produce binary output signals inasmuch as these gates have a binary l signal supplied to each of the inputs thereof. Conversely, gate 309 produces a binary 1 output signal inasmuch as at least one of the inputs receives a binary 0 signal.

The output signals from gates 307, 308 and 309 are applied to the inputs of gates 310,311, 312 and 313 via diodes 326, 327 and 328 as described supra. Thus, a binary 1 signal is supplied to an input of gate 312 and 313 via diodes 328. Similarly, a binary 0 signal is supplied to an input of gate 311 via diode 327. A binary 0 is supplied to an input of gates 310 and 312 via diode 326. Gates 312 and 313 produce binary 0 output signals in response to the application ofa binary 1 input signal. Gate 312 supplies the binary 0 output signal to an input of each of gates 313, 311 and 310. Gate 313 also supplies a binary 0 output signal to an input of gate 310. Thus, gates 310 and 311 receive all binary 0 input signals and, therefore, produce binary l signals. The binary 1 signal produced by gate 311 is returned as a latching signal to an input of gate 312. That is, the binary l signal supplied to the input of gate 312 from gate 311 continues the binary 0 output thereof. This signal,

in combination with the signal supplied to gate 311 from gate 308 causes gate 311 to remain locked in the condition of producing a binary 1 output signal.

Gate 310 also produces a binary 1 output signal. This output signal is supplied, ultimately, to transistor Q17 and'renders the transistor conductive. Conversely, gate 313, in response to a binary 1 input signal supplied thereto by both gates 309 and 310, produces a binary 0 output signal which is, ultimately, supplied to transistor Q18 whereby transistor Q18 remains non-conductive.

When transistor Q17 is rendered conductive, indicator 321 is rendered operative and indicates that the valve being monitored is in the OPEN condition. By a similar analysis of the logic circuit, it can be shown that indicator 320 will be rendered operative when the signals supplied to gates 302 and 303 are reversed. That is, when a binary 1 signal is supplied to the input of gate .303 and a binary 0 signal is supplied to the input of gate 302, transistor Q18, is, ultimately, rendered conductive to energize indicator 320.

In the event that the signals supplied on the decoder lines are not the appropriate signals for decoder gate 300, the indicators will not be operative. Thus, it can be shown that regardless of the input signals supplied to gates 302 and 303 an input signal of the improper code applied to gate 300 will produce a binary l at the output thereof inasmuch as at least one binary 0 will be supplied to the input thereof. A binary l at the output of gate 300 will produce a binary 0 at the output of gate 301. This binary signal is supplied to an input of each of gates 304, 305 and 306. Obviously, with the application of at least one binary 0 input signal, each of these gates must produce a binary 1 output signal. Following the same analogy, each of gates 307, 308 and 309 must produce binary 0 output signals. The binary 0 signals are supplied to gates 310, 311, 312 and 313. However, due to past operation a binary 1 signal was produced by either gate 310 or 313. This binary 1 signal is returned to the other of these gates thereby causing a latching of the flip-flop created by the cross-coupling of the gates. Consequently, these gates tend not to be switched in the absence of the application of a binary 1 signal. Therefore, indicators 320 or 321 will remain in the previous operative condition.

Referring now to FIG. 5, there is shown another type of logic circuit which is utilized to control indicator lights which relate to standard status checking channels. In FIG. 5, a decoder network is connected to a logic control circuit which decodes signals supplied thereto and selectively causes operation of indicators which indicate whether the system is in an abnormal or a normal condition. More particularly, decoder gate 31 has the four inputs thereof connected to selected ones of the output lines of code generator 21 (see FIG. 2). In particular, in the embodiment shown the inputs of gate 31 are connected to the A,, C and D lines of the code signal conducting cable. NOR gate 400 has the input thereof connected to the subsea equipment to receive signals produced thereby. Obviously, a plurality of receiver channels are connected in parallel. Therefore, the subsea equipment signal is supplied to the inputs of each of the input gates 400. However, unless the decoding gate such as gate 31 is also energized, no signal is propagated through the receiver channel.

The output of decoder gate 31. is connected to each of the inputs of gate 402. The output of gate 400 is connected to each of the inputs of gate 401 and, as well, to one input of gate 404. The output of gate 402 is connected to another input of gate 404 as well as to an input of gate 403. The output of gate 401 is connected to an input of gate 403 as well. The output of gate 403 is connected to both inputs of gate 405. The output of gate'405 is connected via diode 407 to an input of gate 409 which forms one portion of a flip-flop. The output of gate 404 is connected to both inputs of gate 406, the output of which is connected via diode 408 to one input of gate 410 which forms another portion of the aforesaid flip-flop. The output of gate 410 is connected to another input of gate 409 while the output of gate 409 is connected to another input of gate 410.

In addition, the output of gate 409 is connected to the base of transistor Q19 via inverting drivers 411 and 412 and isolating resistor 415. Similarly, the output of gate 410 is connected to the base of transistor Q20 via inverting drivers 413 and 414 connected in series with isolating resistor 410.

The emitter electrode of each of transistors Q19 and Q20 is connected to ground potential. The collector of transistor Q19 is connected to one side of indicator 36. The other side of indicator 36 is connected to source 420. The collector electrode of transistor Q20 is connected to one side of indicator 35 the other side of which is also connected to source 420. In addition, the collector electrodes of transistors Q19 and Q20 are connected via diodes 417 and 418, respectively, to switch 419. Another contact of switch 419 is connected to ground potential. As in the case of switch 324 in FIG. 4, switch 419 provides a means for determining the operability of indicators 35 and 36 without affecting the remainder of the circuit. That is, when switch 419 is closed, a complete circuit exists from source 420 via indicators 35 and 36, via the respective diodes 417 and 418, and to ground. When switch 419 is open (the normal situation) the indicators are operated selectively as determined by logic circuitry 32.

The application of the correct coding signal arrangement to gate 31 via the code signal lines causes gate31 to produce a binary output signal. Conversely, an improper input code (i.e. at least one of the input signals is a binary 0) causes a binary 1 signal to be produced by gate 31. The binary 0 signal is applied to both inputs of gate 402. Gate 402 produces a binary 1 output in response to a binary O at the output of gate 31. Gate 400 operates as a driving network whereby the signal supplied to the input thereof is produced at the output thereof as well. The operation of the other gates in the network are inherently obvious and are well known in the art. A detailed analysis of the operation of this circuit is, therefore, unnecessary. Ultimately, a binary 1 signal will be supplied to one of the inputs of either gate 409 or 410. This gate will produce a binary 0 output signal in response to the binary 1 output. The binary 0 signal will be applied to other input of the other gate whereby the second gate will produce a binary 1 output. These signals are supplied ultimately via the inverter pairs to the bases of transistors Q19 and Q20. Whichever. transistor Q19 or Q20 receives the binary 1 input signal will be rendered conductive. Conduction by one of the transistors will cause the associated indicator 35 or 36 to operate. This type of operation is similar to the operation of the circuit shown in FIG. 4.

As will be seen, by tracing the circuit, if an improper code signal is applied to the inputs of gate 31, a binary 0 signal will be applied to an input of each of gates 403 and 404. Thus, binary 0 signals will be applied to one of the inputs of each of gates 409 and 410. With a binary 0 input applied to an input of each of the circuits of the flip- flop comprising gates 409 and 410, the output thereof tends to remain in the previous condition.

Referring now to FIG. 6, there is shown a schematic diagram of the circuit for analog, signal detection. Again, decoder gate 37 has the four inputs thereof connected to receive the. coded output signal from code generator 21. In particular, gate 37 has the inputs connected to the RE, C and D lines of the code cable. The output of gate, 37 is connected to both inputs of gate 425. The output of gate 425 is connected .via limiting resistor 426.. and driver 427'to switching circuit 38. Switching circuit 38 comprises a relay coil K2 which is connected to source 428. Isolating diode 431 isconnected across relay coil K2 to prevent reverse current flow to the coil.

The contacts K2 associated-with the relay coil K2 are connected to opposite sides of a suitable meter 39 via limiting resistor 430 and balancing potentiometer 429which is adjustableto permit adjustment in the meter reading.

In this circuit, application of the appropriate code causes gate 37 to produce a binary 0 output. This signal is supplied to the inputs of gate 425 to produce a binary 1 output. The binary 1 output is supplied across coil K2 tocause current flow therethrough thereby effecting actuation of the contacts K2 of the relay. When the contacts K2 are actuated,'meter 39 is interconnected with the subsea unit and reads the signals supplied thereby. In thisembodiment, the reading is indicative of the annulus pressure. However, this analog signal is produced subsea by any suitable means such as a pressure transducer or the like wherein an analog reading is representedby a voltage generated by the transducer.

The information and material discussed supra, is, of course, related to the surface unit. The surface unit is connected to a subsurface unit. The subsurface unit is described hereinafter.

Referring now to FIG. 7, there is shown a schematic diagram of the control portion of the subsea system shown diagrammatically in FIG. 1. The connection between master code generator transmitter 21 and slave code generator 21 is effected by means of the conductors labeled A, B, C and D which combine to form cable 24. The conductors in cable 24 are connected to the outputs A, B, C and D of flip-flops A-D with. each cable having the same letter designation as the flip-flop to which it is connected. Slave code generator 21 includes a plurality of J-K flip-flops 705, 706, 707 and 708. These J-K flip-flops are connected to give a toggle type operation. For example, the clock input (T) for each of flip-flops 705 708 is connected 7 to ground.

In each of the flipflops, one input is connected to the conductor lines in cable 24 directly while another input in each flip-flop is connected to the conductor lines through an inverter. For example, the A line of cable 24 is connected directly to the R input of flip-flop 705. Similarly, the A input line is connected to the S input of flip-flop 705 via inverter 701. Thus, a signal supplied to the S and the R inputs of flip-flop 705 are clearly complementary signals. The outputs of flip-flop 705 are designated as 2A and 2A. The A and A signals are indicative of the continuity with the signals supplied by code generator 21 while the prefix permits a distinction between the surface and subsurface units.

Referring to flip-flop 706, the R input is connected directly to the B line while the S input is connected via inverter 702. Thus, flip-flop 706 receives complementary input signals. The output sign als produced by flipflop 706 are designated 28 and 2B. Likewise, flip-flop 707 receives input signals on the C line. The R input of flip-flop 707 is connected directly to the C line while the S input of flip-flop 707 is connected to the C line via inverter 703. The 9utput signals produced by flipflop 707 are 2C and 2C.

Flip-flop 708 is similar to the other flip-flops. TI-Iat is,-the R input is connected directly to the D line in cable 24 and the S input is connected tov the D line via inverter 704. The output signals produced by flip-flop 708 are 2D and 2D.

The output signals produced by flip-flops 705 708 are supplied along the conductor lines included in cable 40A. These lines are designated by the signal s supplied thereto. For example, the lines are 2A, 2A, 2B and so forth. The lines in cable 40A are connected to the subsurface control circuitry. For example, detector 69 in a command receiver channel (see FIG. 1) has the 'four inputs thereof connected to four of the lines in cable 40A. The output of decoder 69 is connected to the inputs of gate 709. The output of gate 709 is connected to provide a BCD (binary coded decimal) signal. The BCD signal is utilized as an enable" signal to gates 712 and 713 as well as to gates 722 and 723 (see FIG. 8). I

The OPEN and CLOSE signalssupplied on command iine 68 (see FIG. 1) are applied to the inputs of gates 710 and 711. The output of gate 710 is connected as another input of gate 712 while the output of gate 711 is connected as another input to gate 713. The outputs of gates 712 and 713 are connected to the inputs of gates 714 and 715, respectively. The outputs of gates 714 and 715 are connected via capacitors 716 and 717 to the trigger electrodes of SCRs 718 and 719. The cathodes of SCR 718 and SCR 719 are connected to ground. The anode of SCR 718 is connected to one suitable drive element or the like included in command signal remote equipment 76. The anode of SCR 719 is connected to another suitable unit in remote equipment 76. Typically, a solenoid, motor, or the like may be connected to each SCR whereby operation of the SCR will cause operation of the remote equipment 76. The remote equipment may include valves or the like associated with subsurface wellheads, pipelines, or the like. Thus, the status or operation of the remote equipment is controlled by the signal supplied thereto via the associated SCR.

Referring now to FIG. 8, the BCD signal from gate 709 is also supplied as an enabling signal to gates 722 and 723. Other inputs of gate 722 and 723 are connected to the outputs of gates 720 and 721, respectively. The inputs of gates 720 and 721 are connected to remote equipment 49 for receiving STATUS signals therefrom. For example, when the switches on the valves represented by remote equipment 49 are operated, a signal is supplied to gates 720 and 7 21.

The outputs of gates 722 and 723 are connected to the inputs of gates 724 and 725, respectively. The outputs of gates 724 and 725 are connected to the anodes of isolating diodes 44 and 44A, respectively. The cathodes of diodes 44 and 44A are connected to the status lines of cable 67 (see FIG. 1). As suggested in FIG. 1, a plurality of status channels are provided. The outputs of the several channels are connected together via lines 67A. However, only the status channel which receives an enabling BCD signal from the command channel which is selected by the decoder and the coded signals will produce an output signal on status line 67.

The coded signals on cable 40A are further supplied to the inputs of decoder 56. The output of decoder 56 is connected to the inputs of gate 728. The output of gate 728 is connected to one input of gate 729.

A signal generated by remote equipment 60 is supplied to an input of gate 726. Gate 726 operates as a level driver and a polarity normalizer. The output of gate 726 is supplied to the inputs of gates 727. The output of gate 727 is connected to another input of gate 729. The output of gate 729 is connected to the input of gate 730. The output of gate 730 is connected to the anode of isolating diode 58. The cathode of diode 58 is connected via one of the status lines 67A to status cable 67.

In operation, a suitable signal is supplied by the subsurface equipment 60. This signal, which may represent a generator voltage status or the like, is always presented to the input of gate 726 which inverts the signal. The output of gate 726 is supplied to gate 727 which again inverts and supplies a signal to the input of gate 729. Thus, gate 729 is continuously receiving an input signal representative of the status of the subsurface equipment 60. However, gate 729 is not rendered operative until an enable signal is supplied by gate 728.

Gate 728 does not supply a signal to gate 729 until decoder'56 has been rendered operative by receiving appropriate code signals from code cable 40A. When the appropriate code signal is applied, decoder 56 and gate 728 supply a signal to gate 729 which is then enabled and supplies a signal to cable 67 via gate 730 and diode 58. The signal on cable 67 is returned to the surface unit and detected.

The operation of the status channel reporting on remote equipment 49 is similar. That is, a signal is continuously applied to the input of either gate 720 or 721. These signals are inverted and supplied continuously to the inputs of gates 722 and 723. However, in the absence of a BCD signal neither gate 722 nor gate 723 is enabled. The BCD signal, as noted supra, is generated only as a result of the proper code being supplied to decoder 69 (FIG. 7). When gates 722 and 723 are enabled, the signal supplied by. either gate 720 or 721 is passed therethrough.

When gate 722 or 723 is enabled, the signals produced thereby are supplied to gate 724 or 725 where they are inverted and passed via diodes 44 or 44A to lines 67. Cable 67 is, as noted, connected to the surface unit where the status of remote equipment 49 is detected.

In operation, the slave code generator 21 receives complementary signals at the S and R inputs thereof. With the connection of the clock terminal T to ground the outputs 2A and 2A, for example, will be a function of the signal supplied at the S and R inputs. For example, if the signal supplied to the R input is a binary l, the signal supplied at the 2A output will be a binary 1. Conversely, if a binary 1 signal is supplied at the S input of flip-flop 705, the 2A signal will be a binary 1. Because of the connections, complementary inputs are supplied to the S and R inputs of each flip-flop whereby any change at the input signal line A, B, C or D will cause a reversal of input signals for the flip-flop. Obviously, a reversal of the input signals will produce a reversal of the output signals.

Referring now to FIG. 9, there is shown a schematic diagram of the subsurface portion of the analog signal network. Decoder gate 64 is connected to the subsurface code cable 40A. As suggested supra, the application of the appropriate signals via the cable to the inputs of gate 64 will enable this gate. For example, if all of the input signals applied to gate 64 are binary l signals, a binary 0 signal is produced thereby. This signal is supplied to each of the inputs of gate 802. The output of NAND gate 802 is connected to the base of NPN transistor 0800 via resistor 803. The emitter of transistor 0800 is connected to ground while the collector electrode is connected to a +15 volt source via switching network 65. Switching network 65 comprises relay coil 804 and diode 805.

The subsea remote equipment 61 is illustrated by a bridge network. The network comprises suitable elements which may include a pressure transducer or the like. Across one diagonal of the bridge is connected the series combination of contacts K4 and source 801. Source 801 supplies a positive and negative potential (when contacts K4 are closed) across bridge 61. The other diagonal of bridge 61 has the nodes thereof connected to the respective sets of contacts K1 and K3. Contacts K1 are connected to one of the analog lines in cable 66 (see FIG. 1) while contacts K3 are connected to another of the lines in cable 66. Each of these lines is

Claims (12)

1. In a remote control system including a master station and a remote station which is adapted to be connected to said master station by a plurality of connecting cables greater in number than two but less than the number of functions to be controlled at said remote station, and to a utilization device to be controlled, a first group of said connecting cables being provided to conduct coded address signals from the master station to the remote station, and a second group of said cables being provided to conduct command and information signals between said stations, said master station comprising master station signal generating means for generating coded address signals in response to an operator command, said coded address signals providing different codes representative of different functions to be performed at said remote station, and a plurality of display means connected to said signal generating means and each such display means being enabled in response to receipt of a particular coded address signal from said signal generating means to provide a display in response to the receipt of an information signal generated in response to the function represented by said particular coded address signal; and said remote station comprising remote station signal generating means adapted to be connected to said master station generating means by said first group of connecting cables to provide said coded address signals at said remote station, a plurality of interrogation means adapted to be connected to said utilization device, to said remote station signal generating means, and by said second group of connecting cables to said display means, each of said interrogation means adapted to respond to a particular one of said coded address signals from said remote station signal generating means to perform a function represented by said particular one of said coded signals, and provide an information signal responsive to said function performed to the display means enabled by said particular one of said coded address signals.

1. In a remote control system including a master station and a remote station which is adapted to be connected to said master station by a plurality of connecting cables greater in number than two but less than the number of functions to be controlled at said remote station, and to a utilization device to be controlled, a first group of said connecting cables being provided to conduct coded address signals from the master station to the remote station, and a second group of said cables being provided to conduct command and information signals between said stations, said master station comprising master station signal generating means for generating coded address signals in response to an operator command, said coded address signals providing different codes representative of different functions to be performed at said remote station, and a plurality of display means connected to said signal generating means and each such display means being enabled in response to receipt of a particular coded address signal from said signal generating means to provide a display in response to the receipt of an information signal generated in response to the function represented by said particular coded address signal; and said remote station comprising remote station signal generating means adapted to be connected to said master station generating means by said first group of connecting cables to provide said coded address signals at said remote station, a plurality of interrogation means adapted to be connected to said utilization device, to said remote station signal generating means, and by said second group of connecting cables to said display means, each of said interrogation means adapted to respond to a particular one of said coded address signals from said remote station signal generating means to perform a function represented by said particular one of said coded signals, and provide an information signal responsive to said function performed to the display means enabled by said particular one of said coded address signals.

2. The remote control system of claim 1 wherein said first group of connecting cables is 2N 1 cables where N is the number of functions to be controlled at said remote station.

3. The remote control system of claim 1 wherein said remote station includes at least one command signal means adapted to be connected to said utilization device and responsive to said remote station signal generating means to cause said utilization device to perform a function, and wherein said plurality of display means and said plurality of interrogation means comprise a plurality of status channels with each such channel including one of said display means and interrogation means and adapted to provide status information concerning said utilization means when said one of said display means and interrogation means is addressed by one of said coded address signals.

4. The remote control system of claim 3 wherein said master station signal generator means includes means for generating command signals in response to an operator command, and adapted to be connected to said command signal means at said remote station to provide command signals thereto.

5. The remote control system of claim 3 wherein at least one of said status channels including its associated display means and detector means includes means for providing an analog display at said master station of a condition of said utilization means.

6. The remote control system of claim 1 wherein the functions to be controlled at said remote station include at least one operation of such a utilization device and a plurality of status checks of the status of conditions at said utilization device, including at least one analog display of such a condition, wherein said display means at said master station includes at least one status receiver responsive to a first of said address codes to provide a display of the status of one of said conditions, and at least one analog receiver responsive to a second of said address codes for providing an analog display of one of said conditions, and wherein said interrogation means includes at least one status transmitter responsive to said first coded address signal to provide a status information signal to said at least one status receiver, and at least one analog status transmitter responsive to said second coded address signal to provide an analog information signal to said at least one analog receiver, and wherein said remote station further includes command means adapted to be connected to said utilization device and to said remote station signal generating means and being responsive to said remote station signal generating means to cause said at least one operation of said utilization device.

7. The remote control system of claim 6 wherein said master station signal generating means includes means for generating a command signal in response to an operator command, and said command means includes a plurality of command circuit means Each adapted to control a separate operation of said utilization device in response to a different coded address signal and said command signal, and further including a plurality of status transmitters each responsive to a different one of said coded address signals to provide an information signal, and a plurality of status receivers each responsive to one of said different one of said coded address signals to provide a display in responsive to receipt of an information signal provided by the status transmitter also responding to the same different one of said coded address signals.

8. The remote control system of claim 1 wherein said master station signal generating means includes code checking means responsive to an improperly coded signal being generated by said master station signal generating means to inhibit conduction of said improperly coded signal to said display means and interrogation means.

9. The remote control system of claim 1 wherein said master station signal generator means includes switch means adapted to be actuated by an operator to cause said signal generating means to produce one of said coded address signals, matrix means connected to said switch means, and memory storage means connected to said matrix means, said memory storage means responsive to the operation of said matrix means to store signals representative of the coded address signal selected by the operator.

10. The remote control system of claim 9 wherein said master station signal generating means includes clock circuit means connected to said storage means and said switch means and operative to produce a clock signal in response to a predetermined signal from said switch means and to supply said clock signal to said storage means to enable said storage means to receive and store signals from said switch means, and a false code detector connected to said matrix means and said clock circuit means to inhibit operation of said clock circuit means in response to operation of said matrix means upon receipt of an improper code from said switch means.

11. The remote control system recited in claim 9 wherein said code checking means includes timing circuit means connected to said switch means, and operative to produce an output signal for a predetermined time period in response to receipt of a signal from said switch means to inhibit operation of said storage means during said predetermined time period.

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