US3717516A - Methods of controlling the reverse breakdown characteristics of semiconductors, and devices so formed - Google Patents

Methods of controlling the reverse breakdown characteristics of semiconductors, and devices so formed Download PDF

Info

Publication number
US3717516A
US3717516A US00083612A US3717516DA US3717516A US 3717516 A US3717516 A US 3717516A US 00083612 A US00083612 A US 00083612A US 3717516D A US3717516D A US 3717516DA US 3717516 A US3717516 A US 3717516A
Authority
US
United States
Prior art keywords
impurity
junction
slice
density profile
breakdown voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US00083612A
Inventor
A Hatcher
R Stonefelt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of US3717516A publication Critical patent/US3717516A/en
Assigned to AT & T TECHNOLOGIES, INC., reassignment AT & T TECHNOLOGIES, INC., CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). EFFECTIVE JAN. 3,1984 Assignors: WESTERN ELECTRIC COMPANY, INCORPORATED
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/144—Shallow diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/92—Controlling diffusion profile by oxidation

Definitions

  • fringe refers to a unit of linear measure based upon a fringe of sodium light approximately equal to 0.0l 16 mil or 2,940 Angstrom units.
  • This invention relates to semiconductive devices, and especially to improved p-n junctions that have steep impurity gradients and to methods for their manufacture.
  • the invention is concerned with a method for adjusting the breakdown voltage of voltage regulator diodes during their manufacture.
  • low voltage regulator diodes manufactured by this method are characterized by their sharp voltage breakdowns, low breakdown impedances, high current carrying capacities, and other desirable physical and mechanical properties.
  • Diodes comprised of semiconductive materials may be adapted for use as voltage regulators when given a reverse bias. At a determinable reverse voltage, breakdown occurs and the reverse current sharply increases.
  • a zener diode should have a sharp breakdown voltage. By this is meant that when the critical breakdown voltage is reached, the slope of the reverse current curve will abruptly shift from approximately zero to approximately infinity. This is referred to as a sharp knee.” If the transition between the two slopes of the reverse current curve is less abrupt and somewhat more gradual, the zener diode is said to have a soft knee.
  • the avalanche breakdown characteristics of zener regulators produce very sharp knees and, accordingly, provide for good voltage regulation.
  • semiconductive materials that have comparatively low resistivity (e.g., in the range from about 0.003 to 0.012 ohm-cm. for silicon) must be used as the base material.
  • the materials In order to obtain such low resistivities in semiconductive materials, the materials must be doped quite heavily with impurities. Unfortunately, such high concentration of impurities may result in field emission and tunneling at the p-n junction and will generally cause the diode to have a soft knee.
  • Zener regulators having voltage breakdowns above about 10 volts are manufactured from semiconductive materials of somewhat higher resistivity than the low voltage zenerregulators, and thus do not require as high doping with impurities. For this reason, it is comparatively easy to obtain avalanche breakdown and sharp knees in higher voltage zener regulators.
  • a given breakdown voltage is obtained by treating a slice at a time and at a temperature sufficient to establish the required concentration and concentration profile of the impurity. The electrical properties of the slice are then measured, and if the breakdown voltage is too low, the slice is returned to the oven for a period of time to approximate the desired breakdown voltage more closely.
  • the concentration or steepness of the concentration profile of the impurity may be reduced to less than that necessary to obtain the desired breakdown voltage. If this occurs, the slice will be spoiled for its intended function and must either be scrapped or used for another purpose. For these reasons, it is difficult to manufacture a zener regulator and selectively obtain a preselected breakdown voltage with any degree of precision. This problem is particularly acute when it is desired to match a regulator with the electrical parameters of a given circuit.
  • Another object of this invention is to provide methods for obtaining steep impurity gradients at localized regions of p-n junctions.
  • Another object of this invention is to provide methods for selectively and accurately adjusting the reverse voltage breakdown of zenentype diodes.
  • Another object of this invention is to provide a method for adjusting the reverse breakdown voltage of zener-type diodes that will permit re-establishing a higher breakdown voltage if the desired treatment end point is exceeded.
  • Another object of this invention is to provide low voltage zener-type diodes that have sharp knees.
  • Another object of this invention is to provide zenertype diodes for low voltage regulation that have low breakdown irnpedances.
  • Another object of this invention is to provide low voltage zener-type voltage regulators that have comparatively low ohmic resistance and comparatively high current-carrying capacity.
  • these and other objects of this invention are achieved by establishing a p-n junction with at least one impurity for which the elemental semiconductive material and its oxide have a different affinity, at a temperature such that the rate of oxide growth is greater than the rate to which the impurity diffuses in the semiconductive material, and continuing such treatment until a desired impurity density profile has been obtained.
  • the pand n-type impurities will migrate in opposite directions with respect to the growing oxide layer, thus causing the density of one impurity to be increased at the junction and the density of the other impurity to be depleted at the junction, which will result in a particularly steep impurity density gradient.
  • FIGS. 1 through 6 are highly schematic representations, in cross section, illustrating various stages in the preparation of a diode in accordance with this invention.
  • FIG. 7 is a series of curves illustrating the'effect of time and temperature, during oxidation of the surface of a p-n junction, upon the breakdown voltage of a low breakdown voltage diode.
  • FIG. 1 there is illustrated a semiconductor slice 1 l.
  • an n-type impurity such as antimony
  • the surface of the slice I1 is oxidized (FIG. 2) at elevated temperatures in a wet oxidizing atmosphere to provide a silicon dioxide layer 12 over the slice 11. (Actually, it will be understood that the silicon dioxide surface will form on all surfaces of the slice 11. However, for convenience herein, and in the drawings, only the top surface is considered.)
  • a window 13 is opened in the oxide layer by using standard photoresist techniques (FIG. 3).
  • a p-type impurity such as boron
  • excess glassy impurities are removed from the p-type impurity region 14 and the slice is raised to temperatures that are sufficiently high to give some mobility to both the pand n-type impurities.
  • the slice is exposed to a wet oxidizing environment to cause a layer of silicon dioxide 15 to grow over the surface of the slice 11.
  • this treatment results in the formation of a thin layer 16 below the silicon-silicon dioxide interface that has a high impurity concentration (n-type), and a thin layer 17 below the interface that has a low impurity concentration (p-type).
  • the breakdown voltage can be controllably altered by the time and temperature at which the slice is treated.
  • a metal contact 18 in the window (FIG. 6).
  • a conductive surface such as of silver, can be applied to the reverse side of the slice, and then, using standard diamond scribing techniques, the slice is divided into many hundreds of individual wafers. The wafers are mounted in suitable housings, electrical connections are made, and the device is then ready for use as a zener-type diode.
  • the in.- stant invention is dependent upon the different affinities of the elemental semiconductive material and its oxide for different impurities.
  • the impurities are able to diffuse into or out of the growing oxide layer, depending on their relative affinities for the elemental or oxide state of the semiconductive material. It follows that if the, impurity has greater affinity for the oxide, the elemental material will be partially depleted of the impurity, and if the impurity has greater affinity for the elemental material, the impurity density will be considerably increased in the elemental material.
  • antimony has a greater afiinity for silicon than for silicon dioxide, and it is largely excluded from that portion of the silicon that is being oxidized. To this extent, the antimony is piled up in front of the advancing oxide layer somewhat like waves pile up in front of the bow of a ship moving through the water. While the build-up of the high concentration of antimony adjacent the upper surface of the p-n junction is probably sufficient to obtain the steep impurity gradient desired in the practice of this invention, it is thought that further beneficial turns upward after about 90 minutes treatment at this temperature.
  • One observed datum that substantiates the hypothetical basis for this invention is that, if a slice is oxidized to achieve a reduced breakdown voltage, the original breakdown voltage (here, 8.2) can immediately be re-established by reheating the slice at about 1,250 C. for about 15 minutes.
  • the energy level of the antimony impurity becomes too high and provides such mobility at this temperature that the high antimony concentration is dissipated by diffusion into the silicon.
  • the same effect can be made use of with higher breakdown voltage diodes.
  • the slice can be retreated at high temperatures to reduce the localized concentration by diffusion into the elemental material and re-establish a higher breakdown voltage. After the impurity concentration has been reduced, the slice can be re-oxidized to obtain the desired breakdown voltage, thus making it possible to salvage slices that otherwise would have to be scrapped.
  • the treatment time will be reduced to minutes.
  • the same reverse breakdown voltage could be obtained by heating the slice at l,l00-C. for about 125 minutes.
  • any person skilled in the art should have no difficulty in practicing this invention by initially establishing a p-n junction, measuring the breakdown voltage of the junction, and then, by using controlled heat treatment and oxidation as suggested by the curves such as illustrated in FIG. 7, adjusting the breakdown voltage to a desired value.
  • EXAMPLE I An n-type silicon slice, about 1 V4 inch in diameter and about 0.006 inch thick, was prepared by standard techniques of growing a doped crystal and subdividing it into a number of slices. The silicon was heavily doped with antimony as the n-type impurity in order to provide a material having a low ohmic resistance in the range of about 0.009 to 0.010 ohm-cm.
  • An oxide layer of silicon dioxide 6 to 9 fringes thick was grown on the polished surface of the slice. (Actually, as noted before, the oxide layer grows on all surfaces of the slice but, for ease of description, only the upper surface is here considered.)
  • the oxidation was conducted in an oven at 1,250 C. at atmospheric pressure in a wet, free oxygen-bearing atmosphere for a period of about 2 hours.
  • Standard photoresist techniques were used to etch 14 mil diameter windows in the oxide layer on the slice. Essentially, this technique comprised covering the surface of the slice with a photoresist material, masking those portions of the photoresist where it was desired to open windows, exposing the unmasked portions of the photoresist to a light source, and removing the unexposed (masked) portions of the photoresist. The slice was then etched in a buffered hydrofluoric acid solution that was effective to dissolve the silicon dioxide but did not attack the photoresist or the silicon.
  • boron a p-type impurity
  • the boron was diffused in two stages. First, a pre-deposit of boron was laid down on the slice by placing the slide in a furnace at 1,200 C. in an atmosphere saturated with boron tribromide for 15 minutes. In a second drive-in diffusion, the slice was held in the oven for an additional 2 hours at 1,200 C. to obtain a junction depth of about 28 to 32 fringes. Excess boron glass that formed over the surface of the slice during diffusion was removed. This was accomplished by etching away the boron glass in a 10 percent hydrofluoric acid solution for about 2 minutes.
  • a window was opened in the oxide layer of a specimen slice so prepared and the reverse breakdown voltage was measured at 8.2 volts, with a sharp knee, and a breakdown impedance of about 6 to 7 ohms.
  • the original slice was then placed in an oven and raised to a temperature of 975 C. for about an hour while a wet, free oxygen-bearing atmosphere was circulated around the surface of the slice. After the slice had cooled, an 8 mil window was opened in the second oxide layer. A metallic contact was plated in the window and approximately 2,000 angstroms of silver were evaporated onto the backside of the slice. The slice was then subdivided into many hundreds of wafers by standard diamond scribing techniques and assembled to form diodes.
  • the electrical properties of the diodes so formed were measured and it was found that the reverse breakdown voltage was reduced to about 6.1 volts; the reverse breakdown impedance was reduced to about 3 to 4 ohms; and the diodes had sharp knees. Further, this was accomplished without any loss, and in fact an apparent increase, in the power rating of the diode as compared to the original junction before treatment.
  • EXAMPLE II To demonstrate the reversibility of the impurity migration, several slices, after they had been treated in accordance with the procedures of Example I to reduce their reverse breakdown voltage to 6.1 volts, were placed in an oven (prior to depositing the metal contact materials) at about 1,250 C. for 15 minutes. When the electrical properties of these slices were then measured, the reverse voltage breakdown was found to have returned to its original level of about 8.2 volts, indicating that the steep gradient established at the p-n results are obtained by a partial depletion of the boron impurity at the surface of the same junction by migration into the oxide layer.
  • the silicon dioxide has a greater affinity for the boron than does the silicon, and as a result, the boron is depleted from the silicon next to the surface of the growing oxide layer, providing a region immediately adjacent the region of high antimony concentration that is partially depleted in boron. Either or both of these factors contribute to the establishment of a very thin annular region at the surface of the junction having the desired steep impurity gradient.
  • the various impurities During the oxidation of the surface of the p-n junction, it is, of course, necessary for the various impurities to have sufficient mobility to diffuse into or out of the growing oxide layer. This readily can be accomplished by raising the temperature of the material to achieve an energy level sufficient to provide a con trolled degree of mobility to the impurity. It is equally important, however, that the temperature (and energy level) not be excessive, for if this occurs, the rate of movement of the impurity will exceed the rate at which the oxide growth is taking place. Thus, any impurity that is excluded from the oxide layer will be dissipated into the elemental material and prevent the formation of a layer having a higher impurity concentration.
  • the treatment temperature In order to obtain a controlled and selective redistribution of impurities at the p-n junction, the treatment temperature must be adjusted to lie within a rather well-defined range.
  • This temperature range is generally defined by three temperature-dependent factors: First, the rate at which the impurity diffuses at the interface into or out of the oxide layer; second, the rate at which the impurity diffuses from the interface into the elemental material; and third, the rate at which the oxide layer grows. Accordingly, when an increase in the impurity density is desired, the temperature will be selected so that the rate of oxide growth will exceed the rate at which the impurity will diffuse at the interface into the elemental material and so that the rate of diffusion of the impurity in the elemental material will be less than the rate of diffusion in the oxide.
  • the controlling factor is that the temperature is selected so that the diffusion rate in the oxide is greater than in the elemental material. Relative rates of diffusion of the impurity in the elemental material and in the oxide apparently are of lesser importance in this case.
  • impuritysegregating temperatures this temperature range that is conducive to achieving the desired selective redistribution of impurities is referred to herein as impuritysegregating temperatures.
  • the degree to which the impurity is rejected or accepted by the oxide layer relative to the body of the semiconductor is defined by the segregation coefficient. If the segregation coefficient is greater than one, the impurity will be rejected by the oxide and, at impurity-segregating temperatures, an increase in impurity concentration will be obtained. If the segregation coefficient is less than one, the impurity will be accepted by the oxide and, at impurity-segregating temperatures, a decrease in impurity concentration will be obtained.
  • FIG. 7 includes a series of four curves illustrating the effect of the time of oxidation upon the breakdown voltage at four different temperatures.
  • the least effect upon the breakdown voltage here shown occurs when the oxidation of the surface of the p-n junction is conducted at 1,250 C. It is believed that at this temperature, the energy level or mobility of the impurities is so great that the impurity diffuses from the interface into the silicon at a rate faster than the rate at which the oxide layer is being grown. For this reason, it is believed that no high impurity gradient is established, no reduction in the reverse voltagebreakdown is achieved, and in fact, an increase in voltage breakdown is observed as is consistent with theory.
  • the 850 C. curve illustrates the effect of utilizing comparatively low temperatures at which the impuritiesalmost do not have sufficient mobility freely to move into or away from the oxide layer as is desired in the practice of this invention.
  • a limited beneficial effect is achieved, however, and it is noted that the breakdown voltage can be reduced from about 8.2 to about 7.3 at this temperature.
  • EXAMPLE III estimated as being only between about 1 to 6 fringes in thickness.
  • Example IV The experiment of Example Ill was repeated, except that, rather than using a nitric acid-hydrofluoric acid etch, only a hydrofluoric acid etch was used which dissolved the silicon dioxide but not the silicon. After the silicon dioxide layer had been removed by this etchant, the electrical properties of the diode were tested and it was found that the reverse voltage breakdown remained at 6.1 volts, thus further demonstrating that the electrical properties of the p-n junction are primarily due to the impurity distribution in the silicon rather than in the silicon dioxide.
  • Diodes prepared from the slice of Example I were also found to have other superior electrical properties. For example, it was found that the breakdown impedances were reduced to only 3 to 4 ohms as compared to the 6 to 7 ohms impedance that existed prior to treatment to obtain the steep impurity gradient. Although the annulus formed by the high concentration of the antimony was extremely thin, the exceptionally high concentration of the antimony lent excellent conductivity to the region, thus enabling the junction to carry comparatively high currents.
  • the invention has also been discussed primarily with respect to boron and antimony as the pand n-type impurities, respectively. It should be understood, however, that other impurities may be used in the practice of this invention, provided that they have segregation coefficients greater or less than one and that they will, therefore, at impurity-segregating temperatures, migrate at significant rates into or away from the oxide layer being formed.
  • impurities include, for example, aluminum, that has a segregation coefficient greater than one; gallium, indium, arsenic, phosphorus, and antimony, that have segregation coefficients less than one; and boron, that apparently may have a segregation coefficient varying from more than to less than one, depending upon the treatment conditions.
  • the invention has also been discussed only with respect to a crystal grown from silicon. It is to be understood that the same principles may be applied to other semiconductive materials, such as germanium, provided, however, that the germanium and its oxides have substantially different affinities for the impurities used to form the p-n junction.
  • a method of producing a semiconductor device which comprises the steps of:
  • ntype impurity is phosphorus, arsenic or antimony.
  • a new method according to claim 1 wherein the ptype impurity is boron, aluminum, gallium or indium.
  • n-type impurity is antimony and the p-type impurity is boron.
  • a method of producing a semiconductor device which comprises the steps of:

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)

Abstract

The impurity density profile of p-n junctions in semiconductive devices is modified at localized regions of the junctions. This is achieved by a controlled oxidation process that causes a selective redistribution of impurities at such regions of the junctions. The process is particularly useful in the manufacture of reverse bias regulator diodes since it enables a controlled adjustment of the breakdown voltage with considerable precision. When the process is used in the manufacture of low voltage regulators, sharp reverse voltage breakdowns and other desirable electrical properties are obtained.

Description

States fiatcher, ,ir. et a1.
Witt 1 [54] METHOD OF CONTROLIIKNG "rrra REVERSE BREAOWN CHACTERKSTHQS 0F 7 SEMICONDUCTORS W Mwm [75] Inventors: Arthur L. Hatchet, Jr., Sinking Spring; Ronald D. Stonetelt, Reading, both of Pa.
[73] Assignee: Western Electric Company, Incorporated, New York, N.Y.
[22] Filed: Oct. 23, 1970 [21] Appl. No.: 83,612
Related US. Application Data [63] Continuation of Ser. No. 730,743, May 21, 1968,
[ 1 Feb. 20, R973 3,474,310 10/1969 Ono et 317/235 3,490,964 1/1970 Wheeler ..l48/l87 Primary ExaminerL. Dewayne Rutledge Assistant Examiner-J. Davis Miller, and J. L. Landis [5 7 ABSTRACT The impurity density profile of p-n junctions in semiconductive devices is modified at localized regions of the junctions. This is achieved by a controlled oxidation process that causes a selective redistribution of impurities at such regions of the junctions. The process is particularly useful in the manufacture of reverse bias regulator diodes since it enables a controlled adjustment of the breakdown voltage with considerable precision. When the process is used in the manufacture of low voltage regulators, sharp reverse voltage breakdowns and other desirable electrical properties are obtained.
11 Claims, 7 Drawing Figures OPEN WINDOW IN OXIDE AND APPLY METAL TERMINAL PAIENIEDFEBZOIW 3,717, 515
SHEET 16F 2 PREPARE DOPED SEMICONDUCTOR l SLICE OXIDIZE SURFACE Fla-3 OPEN WINDOW IN OXIDE LAYER DIFFUSE IMPURITY TO FORM P-N JUNCTION OXIDIZE SURFACE UNDER CONTROLLED TIME TEMPERATURE CONDITIONS TC MODIFY IMPURITY-DENSITY PROFILE OPEN WINDOW IN OXIDE AND APPLY METAL TERMINAL I N VEN TORS ALHATCHER JR R04 STO/VEFELT A r TORNE) PATENTEU Z WS sum 2 or 2 FIG? 7 BREAKDOWN VOLTAGE VS REOXIDATION TEMPERATURE AND TIME OXIDATION TIME METHOD OF CONTROLLING THE REVERSE BREAKDOWN CHARACTERISTICS OF SEMICONDUCTORS This is a continuation of Ser. No. 730,743, filed May 21, 1968, now abandoned.
DEFINITIONS For purposes of clarity in this specification, the folvided from a slice.
The term fringe refers to a unit of linear measure based upon a fringe of sodium light approximately equal to 0.0l 16 mil or 2,940 Angstrom units.
BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to semiconductive devices, and especially to improved p-n junctions that have steep impurity gradients and to methods for their manufacture. In a preferred specific embodiment, the invention is concerned with a method for adjusting the breakdown voltage of voltage regulator diodes during their manufacture. Advantageously, low voltage regulator diodes manufactured by this method are characterized by their sharp voltage breakdowns, low breakdown impedances, high current carrying capacities, and other desirable physical and mechanical properties.
2. Description of the Prior Art Diodes comprised of semiconductive materials may be adapted for use as voltage regulators when given a reverse bias. At a determinable reverse voltage, breakdown occurs and the reverse current sharply increases.
This breakdown of the p-n junction is generally attributed to the avalanche effect. When properly designed, provided only that the current is limited to a value which will not dangerously overheat the diode, the voltage across the diode will be constant and virtually independent of the reverse current flowing through the diode. For this reason, they make excellent and inexpensive voltage regulators. Diodes that are designed to operate in this manner are frequently referred to as zener diodes.
Ideally, a zener diode should have a sharp breakdown voltage. By this is meant that when the critical breakdown voltage is reached, the slope of the reverse current curve will abruptly shift from approximately zero to approximately infinity. This is referred to as a sharp knee." If the transition between the two slopes of the reverse current curve is less abrupt and somewhat more gradual, the zener diode is said to have a soft knee.
Above about 10 volts, the avalanche breakdown characteristics of zener regulators produce very sharp knees and, accordingly, provide for good voltage regulation. However, when designing low voltage breakdown devices, that is, having voltage breakdowns below less than about 10 volts, semiconductive materials that have comparatively low resistivity (e.g., in the range from about 0.003 to 0.012 ohm-cm. for silicon) must be used as the base material. In order to obtain such low resistivities in semiconductive materials, the materials must be doped quite heavily with impurities. Unfortunately, such high concentration of impurities may result in field emission and tunneling at the p-n junction and will generally cause the diode to have a soft knee.
Zener regulators having voltage breakdowns above about 10 volts are manufactured from semiconductive materials of somewhat higher resistivity than the low voltage zenerregulators, and thus do not require as high doping with impurities. For this reason, it is comparatively easy to obtain avalanche breakdown and sharp knees in higher voltage zener regulators.
However, in the manufacture of higher voltage zener regulators, as is also the case with low voltage zener regulators, it is difficult to control process conditions to obtain a given reverse breakdown voltage. Since the breakdown voltage is generally dependent upon the concentration and concentration profile of the impurity diffused into the slice to form the p-n junction, a given breakdown voltage is obtained by treating a slice at a time and at a temperature sufficient to establish the required concentration and concentration profile of the impurity. The electrical properties of the slice are then measured, and if the breakdown voltage is too low, the slice is returned to the oven for a period of time to approximate the desired breakdown voltage more closely. However, if the slice is left in the oven for too long a period of time, the concentration or steepness of the concentration profile of the impurity may be reduced to less than that necessary to obtain the desired breakdown voltage. If this occurs, the slice will be spoiled for its intended function and must either be scrapped or used for another purpose. For these reasons, it is difficult to manufacture a zener regulator and selectively obtain a preselected breakdown voltage with any degree of precision. This problem is particularly acute when it is desired to match a regulator with the electrical parameters of a given circuit.
It has been recognized for some time that the reverse breakdown voltage of a pm junction can be altered if a steep impurity gradient is established at a p-n junction. It is also known that such steep impurity gradients significantly contribute to the establishment of sharp knees in low breakdown voltage devices. The prior art does not, however, suggest any practical method for selectively controlling the impurity gradient at localized portions of the p-n junction, either to adjust the breakdown voltage or to provide diodes with sharp knees.
SUMMARY OF THE INVENTION Accordingly, it is an object of this invention to provide methods for modifying the impurity density profile of p-n junctions.
Another object of this invention is to provide methods for obtaining steep impurity gradients at localized regions of p-n junctions.
Another object of this invention is to provide methods for selectively and accurately adjusting the reverse voltage breakdown of zenentype diodes.
Another object of this invention is to provide a method for adjusting the reverse breakdown voltage of zener-type diodes that will permit re-establishing a higher breakdown voltage if the desired treatment end point is exceeded.
Another object of this invention is to provide low voltage zener-type diodes that have sharp knees.
Another object of this invention is to provide zenertype diodes for low voltage regulation that have low breakdown irnpedances.
Another object of this invention is to provide low voltage zener-type voltage regulators that have comparatively low ohmic resistance and comparatively high current-carrying capacity.
Briefly, these and other objects of this invention are achieved by establishing a p-n junction with at least one impurity for which the elemental semiconductive material and its oxide have a different affinity, at a temperature such that the rate of oxide growth is greater than the rate to which the impurity diffuses in the semiconductive material, and continuing such treatment until a desired impurity density profile has been obtained. In a preferred method of practicing this invention, the pand n-type impurities will migrate in opposite directions with respect to the growing oxide layer, thus causing the density of one impurity to be increased at the junction and the density of the other impurity to be depleted at the junction, which will result in a particularly steep impurity density gradient.
DESCRIPTION OF THE DRAWINGS Other objects, advantages and features of the invention will be set out in the following detailed description of specific examples and embodiments of the invention when read in conjunction with the drawings, wherein:
FIGS. 1 through 6 are highly schematic representations, in cross section, illustrating various stages in the preparation of a diode in accordance with this invention; and
FIG. 7 is a series of curves illustrating the'effect of time and temperature, during oxidation of the surface of a p-n junction, upon the breakdown voltage of a low breakdown voltage diode.
DETAILED DESCRIPTION OF THE DRAWINGS In FIG. 1, there is illustrated a semiconductor slice 1 l. The slice 11, which in the preferred embodiment of this invention is comprised of silicon, has been heavily doped with an n-type impurity, such as antimony, to provide low ohmic resistance, i.e., less than about 0.012 ohm-cm.
The surface of the slice I1 is oxidized (FIG. 2) at elevated temperatures in a wet oxidizing atmosphere to provide a silicon dioxide layer 12 over the slice 11. (Actually, it will be understood that the silicon dioxide surface will form on all surfaces of the slice 11. However, for convenience herein, and in the drawings, only the top surface is considered.)
After the oxide layer 12 has been established over the surface of the slice 11, a window 13 is opened in the oxide layer by using standard photoresist techniques (FIG. 3). A p-type impurity, such as boron, is then diffused into the surface of the slice 1 l where the window 13 has been opened. This forms a highly doped p-type region 14 FIG-4. Preferably, excess glassy impurities are removed from the p-type impurity region 14 and the slice is raised to temperatures that are sufficiently high to give some mobility to both the pand n-type impurities. At the same time, the slice is exposed to a wet oxidizing environment to cause a layer of silicon dioxide 15 to grow over the surface of the slice 11. As is best illustrated in FIG. 5, this treatment results in the formation of a thin layer 16 below the silicon-silicon dioxide interface that has a high impurity concentration (n-type), and a thin layer 17 below the interface that has a low impurity concentration (p-type).
By establishing the layer of high impurity concentration 16 and the adjacent layer of low impurity concentration 17, a steep impurity gradient is obtained at the p-n junction which enables adjustment of the breakdown voltage and/or the manufacture of a diode with a low reverse voltage breakdown and a sharp knee. As will be discussed in more detail hereinafter, the breakdown voltage can be controllably altered by the time and temperature at which the slice is treated.
Subsequent to the redistribution of the impurities, standard techniques are utilized to complete the manufacture of the diode such as by opening another window in the second oxide layer 15 and depositing a metal contact 18 in the window (FIG. 6). A conductive surface, such as of silver, can be applied to the reverse side of the slice, and then, using standard diamond scribing techniques, the slice is divided into many hundreds of individual wafers. The wafers are mounted in suitable housings, electrical connections are made, and the device is then ready for use as a zener-type diode.
While the theory or mechanism for this invention has not been definitely established, it is believed that the results are achieved by a controlled impurity redistribution caused by the thermal oxidation of the semiconductive base material that effects modification of the impurity density profile at the surface of the junction. This theory is compatible with the presently observed data and has proven useful in predicting, with considerable accuracy, the results to be obtained upon varying process conditions.
According to this theory, it is believed that the in.- stant invention is dependent upon the different affinities of the elemental semiconductive material and its oxide for different impurities. By first heating the p-n junction to temperatures high enough to impart controlled mobility to the several impurities while simultaneously forming an oxide layer immediately adjacent the exposed surface of the p-n junction, the impurities are able to diffuse into or out of the growing oxide layer, depending on their relative affinities for the elemental or oxide state of the semiconductive material. It follows that if the, impurity has greater affinity for the oxide, the elemental material will be partially depleted of the impurity, and if the impurity has greater affinity for the elemental material, the impurity density will be considerably increased in the elemental material.
In the particular illustration under consideration, antimony has a greater afiinity for silicon than for silicon dioxide, and it is largely excluded from that portion of the silicon that is being oxidized. To this extent, the antimony is piled up in front of the advancing oxide layer somewhat like waves pile up in front of the bow of a ship moving through the water. While the build-up of the high concentration of antimony adjacent the upper surface of the p-n junction is probably sufficient to obtain the steep impurity gradient desired in the practice of this invention, it is thought that further beneficial turns upward after about 90 minutes treatment at this temperature.
One observed datum that substantiates the hypothetical basis for this invention is that, if a slice is oxidized to achieve a reduced breakdown voltage, the original breakdown voltage (here, 8.2) can immediately be re-established by reheating the slice at about 1,250 C. for about 15 minutes. In accordance with the theory, the energy level of the antimony impurity becomes too high and provides such mobility at this temperature that the high antimony concentration is dissipated by diffusion into the silicon.
The same effect can be made use of with higher breakdown voltage diodes. Here, if the treatment reduces the breakdown voltage below the desired value, the slice can be retreated at high temperatures to reduce the localized concentration by diffusion into the elemental material and re-establish a higher breakdown voltage. After the impurity concentration has been reduced, the slice can be re-oxidized to obtain the desired breakdown voltage, thus making it possible to salvage slices that otherwise would have to be scrapped.
In FIG. 7, only four representative curves are shown. The l,250 C. curve is above the useful temperature range for the practice of this invention, and the 850 C. curve borders on the lower useful temperature range. Between these temperatures, a whole family of curves can be drawn, somewhat similar for those drawn for 975 C. and 1,l C., the slopes of which can readily be determined by empirical means for any given system of impurities. Once the slope of these curves is established, it is a simple matter to select the temperature and time of oxidation required to obtain, within limits, any desired breakdown voltage. For example, if a reverse voltage breakdown of about 6 volts is desired, a temperature of 975 C. for a period of 60 minutes can be selected'for treatment. Alternatively, a temperature of 1,100 C. can be used, but here the treatment time will be reduced to minutes. (In theory, the same reverse breakdown voltage could be obtained by heating the slice at l,l00-C. for about 125 minutes. These conditions are not entirely practical, however, since the long treatment time will tend to deplete the boron and thus adversely affect other desired characteristics of the junction.
With the above explanation before him, any person skilled in the art should have no difficulty in practicing this invention by initially establishing a p-n junction, measuring the breakdown voltage of the junction, and then, by using controlled heat treatment and oxidation as suggested by the curves such as illustrated in FIG. 7, adjusting the breakdown voltage to a desired value.
EXAMPLE I An n-type silicon slice, about 1 V4 inch in diameter and about 0.006 inch thick, was prepared by standard techniques of growing a doped crystal and subdividing it into a number of slices. The silicon was heavily doped with antimony as the n-type impurity in order to provide a material having a low ohmic resistance in the range of about 0.009 to 0.010 ohm-cm.
An oxide layer of silicon dioxide 6 to 9 fringes thick was grown on the polished surface of the slice. (Actually, as noted before, the oxide layer grows on all surfaces of the slice but, for ease of description, only the upper surface is here considered.) The oxidation was conducted in an oven at 1,250 C. at atmospheric pressure in a wet, free oxygen-bearing atmosphere for a period of about 2 hours.
Standard photoresist techniques were used to etch 14 mil diameter windows in the oxide layer on the slice. Essentially, this technique comprised covering the surface of the slice with a photoresist material, masking those portions of the photoresist where it was desired to open windows, exposing the unmasked portions of the photoresist to a light source, and removing the unexposed (masked) portions of the photoresist. The slice was then etched in a buffered hydrofluoric acid solution that was effective to dissolve the silicon dioxide but did not attack the photoresist or the silicon.
After the windows were opened in the oxide layer, boron, a p-type impurity, was diffused into the window to form the p-junction. In this example, the boron was diffused in two stages. First, a pre-deposit of boron was laid down on the slice by placing the slide in a furnace at 1,200 C. in an atmosphere saturated with boron tribromide for 15 minutes. In a second drive-in diffusion, the slice was held in the oven for an additional 2 hours at 1,200 C. to obtain a junction depth of about 28 to 32 fringes. Excess boron glass that formed over the surface of the slice during diffusion was removed. This was accomplished by etching away the boron glass in a 10 percent hydrofluoric acid solution for about 2 minutes.
A window was opened in the oxide layer of a specimen slice so prepared and the reverse breakdown voltage was measured at 8.2 volts, with a sharp knee, and a breakdown impedance of about 6 to 7 ohms.
The original slice was then placed in an oven and raised to a temperature of 975 C. for about an hour while a wet, free oxygen-bearing atmosphere was circulated around the surface of the slice. After the slice had cooled, an 8 mil window was opened in the second oxide layer. A metallic contact was plated in the window and approximately 2,000 angstroms of silver were evaporated onto the backside of the slice. The slice was then subdivided into many hundreds of wafers by standard diamond scribing techniques and assembled to form diodes.
The electrical properties of the diodes so formed were measured and it was found that the reverse breakdown voltage was reduced to about 6.1 volts; the reverse breakdown impedance was reduced to about 3 to 4 ohms; and the diodes had sharp knees. Further, this was accomplished without any loss, and in fact an apparent increase, in the power rating of the diode as compared to the original junction before treatment.
EXAMPLE II To demonstrate the reversibility of the impurity migration, several slices, after they had been treated in accordance with the procedures of Example I to reduce their reverse breakdown voltage to 6.1 volts, were placed in an oven (prior to depositing the metal contact materials) at about 1,250 C. for 15 minutes. When the electrical properties of these slices were then measured, the reverse voltage breakdown was found to have returned to its original level of about 8.2 volts, indicating that the steep gradient established at the p-n results are obtained by a partial depletion of the boron impurity at the surface of the same junction by migration into the oxide layer. (Note that some authorities suggest that boron tends to regard both states with equal favor, and thus, little change in surface concentration will be obtained, and to this extent, the theory with respect to boron redistribution here set forth may be subject to dispute.) in this instance, the silicon dioxide has a greater affinity for the boron than does the silicon, and as a result, the boron is depleted from the silicon next to the surface of the growing oxide layer, providing a region immediately adjacent the region of high antimony concentration that is partially depleted in boron. Either or both of these factors contribute to the establishment of a very thin annular region at the surface of the junction having the desired steep impurity gradient.
For a more complete discussion of the above phenomena, see Impurity Redistribution and Junction Formation in Silicon by Thermal Oxidation in the Bell System Technical Journal, Volume 39, July, 1960, pages 933946; INTEGRATED CIRCUITS Design Principles and Fabrication by Engineering Staff, Motorola, lnc., 1965, pages 304-306; and A. S. Grove,
. Physics and Technology of Semiconductor Devices,
i967, pages 69-75.
During the oxidation of the surface of the p-n junction, it is, of course, necessary for the various impurities to have sufficient mobility to diffuse into or out of the growing oxide layer. This readily can be accomplished by raising the temperature of the material to achieve an energy level sufficient to provide a con trolled degree of mobility to the impurity. It is equally important, however, that the temperature (and energy level) not be excessive, for if this occurs, the rate of movement of the impurity will exceed the rate at which the oxide growth is taking place. Thus, any impurity that is excluded from the oxide layer will be dissipated into the elemental material and prevent the formation of a layer having a higher impurity concentration.
In order to obtain a controlled and selective redistribution of impurities at the p-n junction, the treatment temperature must be adjusted to lie within a rather well-defined range. This temperature range is generally defined by three temperature-dependent factors: First, the rate at which the impurity diffuses at the interface into or out of the oxide layer; second, the rate at which the impurity diffuses from the interface into the elemental material; and third, the rate at which the oxide layer grows. Accordingly, when an increase in the impurity density is desired, the temperature will be selected so that the rate of oxide growth will exceed the rate at which the impurity will diffuse at the interface into the elemental material and so that the rate of diffusion of the impurity in the elemental material will be less than the rate of diffusion in the oxide. When a decrease in the impurity density is desired, the controlling factor is that the temperature is selected so that the diffusion rate in the oxide is greater than in the elemental material. Relative rates of diffusion of the impurity in the elemental material and in the oxide apparently are of lesser importance in this case.
Thus, it will be recognized that certain minimum temperatures are required to obtain the desired rate of growth of the oxide layer and to provide sufficient mobility for the impurity so that it is capable of movement with respect to the oxide or the body of the semiconductor. On the other hand, certain maximum temperatures cannot be exceeded or the degree of mobility will be too great and the desired segregation of the impurity at the oxide-semiconductor interface will not be obtained. For convenience, this temperature range that is conducive to achieving the desired selective redistribution of impurities is referred to herein as impuritysegregating temperatures.
The degree to which the impurity is rejected or accepted by the oxide layer relative to the body of the semiconductor is defined by the segregation coefficient. If the segregation coefficient is greater than one, the impurity will be rejected by the oxide and, at impurity-segregating temperatures, an increase in impurity concentration will be obtained. If the segregation coefficient is less than one, the impurity will be accepted by the oxide and, at impurity-segregating temperatures, a decrease in impurity concentration will be obtained.
The effects of time and temperature during the oxidation step upon the breakdown voltage are illustrated by the curves in FIG. 7. FIG. 7 includes a series of four curves illustrating the effect of the time of oxidation upon the breakdown voltage at four different temperatures. The least effect upon the breakdown voltage here shown occurs when the oxidation of the surface of the p-n junction is conducted at 1,250 C. It is believed that at this temperature, the energy level or mobility of the impurities is so great that the impurity diffuses from the interface into the silicon at a rate faster than the rate at which the oxide layer is being grown. For this reason, it is believed that no high impurity gradient is established, no reduction in the reverse voltagebreakdown is achieved, and in fact, an increase in voltage breakdown is observed as is consistent with theory.
At the other extreme, the 850 C. curve illustrates the effect of utilizing comparatively low temperatures at which the impuritiesalmost do not have sufficient mobility freely to move into or away from the oxide layer as is desired in the practice of this invention. A limited beneficial effect is achieved, however, and it is noted that the breakdown voltage can be reduced from about 8.2 to about 7.3 at this temperature.
The two curves obtained at intermediate temperatures, that is, at 975 C. and l,l00 C., illustrate that a very considerable reduction in breakdown voltage can be achieved at these temperatures. If the treatment follows the l, 1 00 C. curve, a breakdown voltage of about 5.2 volts can be obtained. Note that after about an hour, the breakdown voltage begins to rise again. It is believed that this occurs since the rate of oxidation decreases considerably with time due to the fact that the increasingly thick oxide layer becomes increasingly impervious to further oxidative attack. Accordingly, when the rate of oxidation decreases until it is approximately equal to the diffusion rate of the antimony through the elemental material, the l,l00 C. curve reflects a flat horizontal portion where no net change in breakdown voltage takes place. As the rate of oxidation still further decreases, the rate of diffusion of the antimony into the elemental material eventually becomes greater than the rate of oxidation, and, as a result, the high antimony concentration is dissipated faster than it is formed. This is thought to be the reason the curve junction by the controlled oxidation at lower temperatures had been dissipated bydiffusion of the impurities.
EXAMPLE III estimated as being only between about 1 to 6 fringes in thickness.
EXAMPLE IV The experiment of Example Ill was repeated, except that, rather than using a nitric acid-hydrofluoric acid etch, only a hydrofluoric acid etch was used which dissolved the silicon dioxide but not the silicon. After the silicon dioxide layer had been removed by this etchant, the electrical properties of the diode were tested and it was found that the reverse voltage breakdown remained at 6.1 volts, thus further demonstrating that the electrical properties of the p-n junction are primarily due to the impurity distribution in the silicon rather than in the silicon dioxide.
Diodes prepared from the slice of Example I were also found to have other superior electrical properties. For example, it was found that the breakdown impedances were reduced to only 3 to 4 ohms as compared to the 6 to 7 ohms impedance that existed prior to treatment to obtain the steep impurity gradient. Although the annulus formed by the high concentration of the antimony was extremely thin, the exceptionally high concentration of the antimony lent excellent conductivity to the region, thus enabling the junction to carry comparatively high currents.
In the above description of this invention, particular emphasis has been placed upon the production of a zener-type diode with controlled reverse voltage breakdown characteristics. It should be understood that the invention is not so limited, however, as it will find equal applicability in other instances where it is desired to establish a junction having a steep impurity gradient.
The invention has also been discussed primarily with respect to boron and antimony as the pand n-type impurities, respectively. It should be understood, however, that other impurities may be used in the practice of this invention, provided that they have segregation coefficients greater or less than one and that they will, therefore, at impurity-segregating temperatures, migrate at significant rates into or away from the oxide layer being formed. Examples of such impurities include, for example, aluminum, that has a segregation coefficient greater than one; gallium, indium, arsenic, phosphorus, and antimony, that have segregation coefficients less than one; and boron, that apparently may have a segregation coefficient varying from more than to less than one, depending upon the treatment conditions.
The invention has also been discussed only with respect to a crystal grown from silicon. It is to be understood that the same principles may be applied to other semiconductive materials, such as germanium, provided, however, that the germanium and its oxides have substantially different affinities for the impurities used to form the p-n junction.
Although certain embodiments of this invention have been shown in the drawings and described in the specification, it is to be understood that the invention is not limited thereto, is capable of modification, and can be rearranged without departing from the spirit and scope of the invention.
What is claimed is:
1. A method of producing a semiconductor device, which comprises the steps of:
establishing a p-n junction with a first impurity-density profile in a semiconductor body such that a major portion of the junction is further than 1 fringe from a surface of the body but such that the junction intersects said surface; and
oxidizing the surface of the body which the junction intersects to modify the impurity-density profile of the junction in the region of the intersection whereby a p-n junction is produced having a major portion of its area with a first impurity-density profile and a minor portion of its area with a modified impurity-density profile.
2. A new method according to claim 1 wherein the ntype impurity is phosphorus, arsenic or antimony.
3. A new method according to claim 1 wherein the ptype impurity is boron, aluminum, gallium or indium.
4. The method of claim 1 wherein the modification of the impurity-density profile produces a reverse breakdown voltage of the semiconductor device of less than about 8 volts and produces a junction having a sharp knee.
5. A new method according to claim 1 wherein the semiconductive body is comprised of silicon.
6. A method according to claim 5 wherein the n-type impurity is antimony and the p-type impurity is boron.
7. A method of producing a semiconductor device, which comprises the steps of:
preparing a slice of semiconductive material comprised of an intrinsic semiconductor and a high concentration of a first conductivity-type determining impurity;
forming an oxide film on a surface of the slice;
generating a first opening in the oxide film; diffusing a second impurity through said first opening of opposite conductivity type than the first impurity into the slice to form a pm junction with a first impurity-density profile such that a major portion of the junction is further than one fringe from said surface and such that the junction intersects said surface of the slice; oxidizing said surface to modify the impurity-density profile of the junction in the region of the intersection to form an annular region having a reverse breakdown characteristic with a sharp knee;
generating a second opening in the oxide film within the bounds of said annular region; and
depositing a metallic contact onto the slice through said second opening with the outer portion of the metallic contact being at least one mil from the annular region whereby the functioning of said region is unaffected by the metal of the contact.
purity is a p-type impurity.
10. A method according to claim 9 wherein the first impurity is antimony.
l l. A method according to claim 10 wherein the second impurity is boron.

Claims (10)

1. A method of producing a semiconductor device, which comprises the steps of: establishing a p-n junction with a first impurity-density profile in a semiconductor body such that a major portion of the junction is further than 1 fringe from a surface of the body but such that the junction intersects said surface; and oxidizing the surface of the body which the junction intersects to modify the impurity-density profile of the junction in the region of the intersection whereby a p-n junction is produced having a major portion of its area with a first impurity-density profile and a minor portion of its area with a modified impurity-density profile.
2. A new method according to claim 1 wherein the n-type impurity is phosphorus, arsenic or antimony.
3. A new method according to claim 1 wherein the p-type impurity is boron, aluminum, gallium or indium.
4. The method of claim 1 wherein the modification of the impurity-density profile produces a reverse breakdown voltage of the semiconductor device of less than about 8 volts and produces a junction having a sharp knee.
5. A new method according to claim 1 wherein the semiconductive body is comprised of silicon.
6. A method according to claim 5 wherein the n-type impurity is antimony and the p-type impurity is boron.
7. A method of producing a semiconductor device, which comprises the steps of: preparing a slice of semiconductive material comprised of an intrinsic semiconductor and a high concentration of a first conductivity-type determining impurity; forming an oxide film on a surface of the slice; generating a first opening in the oxide film; diffusing a second impurity through said first opening of opposite conductivity type than the first impurity into the slice to form a p-n junction with a first impurity-density profile such that a major portion of the junction is further than one fringe from said surface and such that the junction intersects said surface of the slice; oxidizing said surface to modify the impurity-density profile of the junction in the region of the intersection to form an annular region having a reverse breakdown characteristic with a sharp knee; generating a second opening in the oxide film within the bounds of said annular region; and depositing a metallic contact onto the slice through said second opening with the outer portion of the metallic contact being at least one mil from the annular region whereby the functioning of said region is unaffected by the metal of the contact.
8. A new method according to claim 7 wherein the oxidation to form the annular region is continued for a time sufficient to reduce the breakdown voltage to a value less than about 8 volts and the breakdown impedance to a value less than about 4 ohms.
9. A new method according to claim 7 wherein the first impurity is an n-type impurity and the second impurity is a p-type impurity.
10. A method according to claim 9 wherein the first impurity is antimony.
US00083612A 1970-10-23 1970-10-23 Methods of controlling the reverse breakdown characteristics of semiconductors, and devices so formed Expired - Lifetime US3717516A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8361270A 1970-10-23 1970-10-23

Publications (1)

Publication Number Publication Date
US3717516A true US3717516A (en) 1973-02-20

Family

ID=22179506

Family Applications (1)

Application Number Title Priority Date Filing Date
US00083612A Expired - Lifetime US3717516A (en) 1970-10-23 1970-10-23 Methods of controlling the reverse breakdown characteristics of semiconductors, and devices so formed

Country Status (1)

Country Link
US (1) US3717516A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886004A (en) * 1972-03-04 1975-05-27 Ferranti Ltd Method of making silicon semiconductor devices utilizing enhanced thermal oxidation
USRE28500E (en) * 1970-12-14 1975-07-29 Low noise field effect transistor with channel having subsurface portion of high conductivity
US4051504A (en) * 1975-10-14 1977-09-27 General Motors Corporation Ion implanted zener diode
US4079402A (en) * 1973-07-09 1978-03-14 National Semiconductor Corporation Zener diode incorporating an ion implanted layer establishing the breakdown point below the surface
US4099998A (en) * 1975-11-03 1978-07-11 General Electric Company Method of making zener diodes with selectively variable breakdown voltages
US4590664A (en) * 1983-07-29 1986-05-27 Harris Corporation Method of fabricating low noise reference diodes and transistors
US4797371A (en) * 1987-02-26 1989-01-10 Kabushiki Kaisha Toshiba Method for forming an impurity region in semiconductor devices by out-diffusion

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3016313A (en) * 1958-05-15 1962-01-09 Gen Electric Semiconductor devices and methods of making the same
US3474310A (en) * 1967-02-03 1969-10-21 Hitachi Ltd Semiconductor device having a sulfurtreated silicon compound thereon and a method of making the same
US3490964A (en) * 1966-04-29 1970-01-20 Texas Instruments Inc Process of forming semiconductor devices by masking and diffusion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3016313A (en) * 1958-05-15 1962-01-09 Gen Electric Semiconductor devices and methods of making the same
US3490964A (en) * 1966-04-29 1970-01-20 Texas Instruments Inc Process of forming semiconductor devices by masking and diffusion
US3474310A (en) * 1967-02-03 1969-10-21 Hitachi Ltd Semiconductor device having a sulfurtreated silicon compound thereon and a method of making the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE28500E (en) * 1970-12-14 1975-07-29 Low noise field effect transistor with channel having subsurface portion of high conductivity
US3886004A (en) * 1972-03-04 1975-05-27 Ferranti Ltd Method of making silicon semiconductor devices utilizing enhanced thermal oxidation
US4079402A (en) * 1973-07-09 1978-03-14 National Semiconductor Corporation Zener diode incorporating an ion implanted layer establishing the breakdown point below the surface
US4155777A (en) * 1973-07-09 1979-05-22 National Semiconductor Corporation Zener diode incorporating an ion implanted layer establishing the breakdown point below the surface
US4051504A (en) * 1975-10-14 1977-09-27 General Motors Corporation Ion implanted zener diode
US4099998A (en) * 1975-11-03 1978-07-11 General Electric Company Method of making zener diodes with selectively variable breakdown voltages
US4590664A (en) * 1983-07-29 1986-05-27 Harris Corporation Method of fabricating low noise reference diodes and transistors
US4797371A (en) * 1987-02-26 1989-01-10 Kabushiki Kaisha Toshiba Method for forming an impurity region in semiconductor devices by out-diffusion

Similar Documents

Publication Publication Date Title
Hu Properties of amorphous silicon nitride films
US2855524A (en) Semiconductive switch
US2875505A (en) Semiconductor translating device
US3821783A (en) Semiconductor device with a silicon monocrystalline body having a specific crystal plane
US3226614A (en) High voltage semiconductor device
US3149395A (en) Method of making a varactor diode by epitaxial growth and diffusion
JPS58182259A (en) Method of forming polysilicon resistor
US3333326A (en) Method of modifying electrical characteristic of semiconductor member
US3085033A (en) Fabrication of semiconductor devices
IE34446L (en) Semi-conductor device
US2784121A (en) Method of fabricating semiconductor bodies for translating devices
US3434021A (en) Insulated gate field effect transistor
US3203840A (en) Diffusion method
US3538401A (en) Drift field thyristor
US3717516A (en) Methods of controlling the reverse breakdown characteristics of semiconductors, and devices so formed
US3121808A (en) Low temperature negative resistance device
US3879236A (en) Method of making a semiconductor resistor
US2819191A (en) Method of fabricating a p-n junction
US3818583A (en) Method for fabricating semiconductor structure having complementary devices
US3582410A (en) Process for producing metal base semiconductor devices
US3585464A (en) Semiconductor device fabrication utilizing {21 100{22 {0 oriented substrate material
US3512056A (en) Double epitaxial layer high power,high speed transistor
US3376172A (en) Method of forming a semiconductor device with a depletion area
US3473093A (en) Semiconductor device having compensated barrier zones between n-p junctions
US3194699A (en) Method of making semiconductive devices

Legal Events

Date Code Title Description
AS Assignment

Owner name: AT & T TECHNOLOGIES, INC.,

Free format text: CHANGE OF NAME;ASSIGNOR:WESTERN ELECTRIC COMPANY, INCORPORATED;REEL/FRAME:004251/0868

Effective date: 19831229