US3714464A - Detecting circuit for indicating occurrence of peak in an input signal - Google Patents
Detecting circuit for indicating occurrence of peak in an input signal Download PDFInfo
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- US3714464A US3714464A US00053359A US3714464DA US3714464A US 3714464 A US3714464 A US 3714464A US 00053359 A US00053359 A US 00053359A US 3714464D A US3714464D A US 3714464DA US 3714464 A US3714464 A US 3714464A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1532—Peak detectors
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- ABSTRACT A circuit for processing an input signal incorporating a technique of constant fraction timing on the trailing edge of the input signal. The processing is performed in such a manner that the resultant timing signal is independent of the pulse shape and further incorporates means for adjusting the level at which the timing signal is derived in order to optimized the statistical or rms noise uncertainty and further serves to minimize the time delay from the peak of the input signal.
- a system based on the premise ofconstant fraction timing on the trailing edge is useful for all shapes of signal pulses having either single polarity or bipolar shape in that the systematic timing error may essentially be reduced to zero, for all such signal shapes so long as the signal bandwidth is constant.
- the ability to adjust the fraction of pulse height offers at least three unique advantages.
- a large class ofsignals may be used, having an optimum trigger point which is equal to a fraction of the peak amplitude.
- the timing fraction can be adjusted to optimize the time resolutions.
- the signal countrate is sufficiently high that pairs of signal pulses can occur very close together.
- the constant fraction can be adjusted to minimize the pulse pair resolving time.
- the third advantage of the variable constant fraction is that the time delay from the peak of the pulse can be minimized for the applications where this is an important parameter. In general, it is believed that this is the first time adjustable constant fraction that has been used on the trailing edge ofthe signal pulse.
- the time derivation process described has applications in many fields where an electrical signal, in the form of a voltage pulse, is to be analyzed for both time and amplitude information.
- an electrical signal in the form of a voltage pulse
- the signals derived from a scintillation detector or solid state detector contains information about when incident radiation reaches the detector as well as the magnitude (amplitude) or amount of the radiation.
- the proposed circuit when used in conjunction with a single channel analyzer, establishes both the time and the amplitude information. THe use of a constant fraction timing technique based on the trailing edge of such signals would offer all the previously mentioned advantages over prior art techniques.
- the purpose of performing the timing on the trailing edge is to allow sufficient time for decisions to be made on pulse peaks.
- the proposed constant fraction technique for all practical purposes, almost entirely eliminates systematic timing errors due to pulse height variations.
- the fraction of the pulse height on which the timing is performed may be adjusted to obtain optimum time resolution due to noise or statistical contributions, and minimum time delay from the peak of the input signal.
- the comparator in the absence of an input signal, the comparator is, for example, in a high" state. However, when the signal level becomes more positive than a reference signal connected to the comparator state, the comparators output will switch from the high state to a low state. The low state of the comparator then causes another gate to switch the comparator reference to a voltage level that is derived from the stretcher circuit. During this interval, the stretcher circuit is measuring the peak amplitude of the input signal and storing this information on a capacitor. Thus, the information stored in the capacitor which has been switched to the gate, is equal to a constant fraction of the input pulse height. The comparator remains in the low state until the signal becomes less positive than the voltage stored on the capacitor at which time the output of the comparator is switched to the high state and a timing marker is generated.
- one object of the present invention to provide a circuit capable of producing a timing pulse based on a constant fraction of the trailing edge of an input signal.
- Still another object of the present invention is to provide a circuit capable of producing a timing pulse based on a constant fraction of the trailing edge of an input signal wherein the systematic timing error may be essentially reduced to zero for all such signal shapes having an approximately constant bandwidth.
- FIG. 1 is a partial schematic and block diagram of my signal processing circuit
- FIG. 2 is a schematic circuit diagram of one embodiment of a complete timing generator.
- FIG. I there is shown an input terminal 10 for applying an input signal to a buffer amplifier 42 the output of which is applied simultaneously to potentiometer 26 and to comparator 14.
- the voltage developed across potentiometer 26 is applied as one input to a stretcher circuit consisting of amplifiers 20 and 22 having a series diode 28 and a shunt capacitor 30 connected between the amplifiers.
- Shunt capacitor 30 has a gate circuit 38 connected parallel therewith and a lead 44 connected to one output of gate 46.
- the output of amplifier 22 is applied as an input to amplifier 20, by means of lead 40, and also as an input to gate 16 by means of lead 36.
- Reference voltage 32 is applied as another input to gate 16 by means of lead 34.
- FIG. 2 there is shown a complete circuit diagram of an embodiment of my invention.
- a positive going input signal is applied to input terminal 10 which signal is then applied as an input to buffer amplifier 42, consisting of active devices Q1 through 04 arranged in a typical buffer configuration.
- the outputof buffer amplifier 42 is applied, as an input, to terminal 3 of'an integrated circuit (IC) arranged as a comparator.
- IC integrated circuit
- I have choosen to use and show a devices 011-015 with the input thereto being shown as a pair of N-channel field effect transistors (FET). While FETs Q11 and Q12 are shown in a differential amplifier configuration, it will be obvious to those skilled in the art that various other types of active devices may be substituted for 011 and Q12.
- comparator 14 is then applied as an input to gate 46 consisting of Q5, Q6 and Q24 and the cathode terminal of Zener diode D1, the anode terminal of which is connected directly to tithing output terminal 18.
- the output of amplifier 20 is applied as an input to unity gain amplifier 22 through a series diode 28 arranged with its anode terminal connected to amplifier 20 and its cathode terminal connected to amplifier 22.
- Amplifier 22 consist of active devices 018 Q23. Connected between the cathode end of diode 28 and ground is capacitor 30, the function of which will be described hereinafter.
- the output of unity gain amplifier 22 is derived at the emitter electrode of active device Q23 and is applied to the gate of PET Q12 by means of lead 40 to provide a feedback loop for the stretcher circuit.
- Lead 36 is connected to the junction of the gate of PET Q12 and the feedback loop, designated by lead 40, so as to provide one input to gate 16.
- Another input to gate 16 is provided by potentiometer 32 between a source of operating potential and ground and is applied by means of lead 34 to the base ofactive device 010.
- Clamp 38 consists of active devices Q16 and 017.
- Capacitor 30 continues to be charged until the peak of the signal is reached at which time, a voltage equal to the capacitor voltage appears at the output of unity gain amplifier 22 and is fed back to the other input (the gate of 012) of the differential pair 011 and Q12.
- diode 28 is reversed biased causing the charge on capacitor 30 to be stored as it no longer has a leakage path.
- the voltage at the output of unity gain amplifier 22 becomes greater than the signal applied to the gate of 011 and the differential pair (011 and Q12) are switched OFF.
- the voltage stored on capacitor 30 appears at the emitter of active device Q23 (in unity gain amplifier 22) it will be proportional to the peak of the input signal.
- reference signal E is applied as one input to pin 2 of comparator 14 to generate a timing signal or marker.
- the timing pulse is applied, by means of lead 44, as an input to Q17 of clamp 38 to restore the voltage on capacitor 30 to zero, signifying that the processing is completed.
- a circuit for detecting an input signal and producing an output signal to indicate the occurrence of a peak in the inputsignal comprising:
- a comparator having first and second inputs and an output, said first input being responsive to the input signal
- a stretcher circuit having an input responsive to the input signal and an output for producing a signal proportional to the peak amplitude of the input signal
- a gating circuit having a first input responsive to the output of said comparator, a second input for receiving the predetermined reference voltage from said source, a third input responsive to the output of said stretcher circuit, and an output coupled to the second input of said comparator for selectively applying the predetermined reference voltage and the signal produced by said stretcher circuit to the second input of said comparator in response to signals produced by said comparator.
- a buffer amplifier having an input responsive to the input signal and an output coupled to the first input of said comparator and the input of-said stretcher circuit.
- a potentiometer coupled to the input of said stretcher circuit and responsive to the input signal for applying a signal proportional to the input signal to said stretchercircuit.
- said stretcher circuit comprises:
- a first amplifier having an input responsive to the input signal and an output
- a second amplifier having an input and an output
- a diode having an anode terminal connected to the output of said first amplifier and a cathode terminal connected to the input of said second amplifier; and i a capacitance responsive to the cathode terminal of said diode for storing a signal proportional to the peak amplitude of the input signal.
- a switch connected in parallel with said capacitance and responsive to the output of said comparator for discharging said capacitance when the input signal at the first input of said comparator is less than the signal applied to its second input.
- a gating circuit having a first input responsive to the output of said comparator, a second input for receiving the predetermined reference voltage from said source, a third input responsive to the output of said second amplifier in said stretcher circuit, and an output coupled to the second input of said comparator for selectively applying the predetermined reference voltage and the signal produced by said stretcher circuit to the second input of said comparator: and which includes a detector responsive to the output of said comparator for controlling the operation of said gating circuit to apply the reference voltage to the second input of said comparator while the amplitude of the input signal is less than the reference voltage and to apply the output signal produced by said stretcher circuit to the second input of the comparator when the amplitude of the input signal exceeds the reference voltage and for operating said switch to discharge said capacitance when the input signal is less than the signal applied to the second input of said comparator.
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Abstract
A circuit for processing an input signal incorporating a technique of constant fraction timing on the trailing edge of the input signal. The processing is performed in such a manner that the resultant timing signal is independent of the pulse shape and further incorporates means for adjusting the level at which the timing signal is derived in order to optimized the statistical or rms noise uncertainty and further serves to minimize the time delay from the peak of the input signal.
Description
United States Patent 1191 Nutt 1 1 Jan. 30, 1973 1541 DETECTING CIRCUIT FOR 3,553,593 1/1971 Gedance .328/116 x INDICATING OCCURRENC OF PEAK 3,564,287 2/1971 Todd ..328/151 x IN AN INPUT SIGNAL [75] Inventor: Ronald Nutt, Knoxville, Tenn.
[73] Assignee: Ortec, Incorporated, Oak Ridge,
Tenn. i
[221 Filed: July 9,1970
[21] Appl. No.: 53,359
[52] U.S. Cl. ..307/235, 328/116, 328/146, 328/151, 330/30 D [51} Int. Cl. ..Il03k 5/20 [581 Field of Search ..307/235;328/11S,116,117,
References Cited OTHER PUBLICATIONS Bjorkman and Brondum, Peak Picking and Noise Suppression Circuitry, IBM Technical Disclosure Bulletin, Vol. 9, No. 6, Nov. 1966 p. 508-589.
Primary ExaminerDonald D. Forrer Assistant ExaminerR. C. Woodbridge Attorney-Ralph L. Cadwallader and Lawrence P. Benjamin 5? ABSTRACT A circuit for processing an input signal incorporating a technique of constant fraction timing on the trailing edge of the input signal. The processing is performed in such a manner that the resultant timing signal is independent of the pulse shape and further incorporates means for adjusting the level at which the timing signal is derived in order to optimized the statistical or rms noise uncertainty and further serves to minimize the time delay from the peak of the input signal.
7 Claims, 2 Drawing Figures STRETCHER CIRCUIT AMPLIFIER d T swn'cu A) oeriacroa7 V AT G 34 LQ UNITY GAIN AMPLIFIER PATENTED JAN 30 I973 SHEET 1 BF 2 .CDUEQ mmIuPwmhm H mokowkuo RONALD NUTT INVENTOR ATTORNEYS PATENTEUJAN 30 ms 3,714,464 SHEET 20F 2 RONALD NUTT INVENTOR ATTORNEYS DETECTING CIRCUIT FOR INDICATING OCCURRENCE OF PEAK IN AN INPUT SIGNAL BACKGROUNDOF THE INVENTION proposed signal processing circuit that distinguishes it from other techniques used in conjunction with timing single channel analyzers. A system based on the premise ofconstant fraction timing on the trailing edge is useful for all shapes of signal pulses having either single polarity or bipolar shape in that the systematic timing error may essentially be reduced to zero, for all such signal shapes so long as the signal bandwidth is constant.
The ability to adjust the fraction of pulse height offers at least three unique advantages. First, a large class ofsignals may be used, having an optimum trigger point which is equal to a fraction of the peak amplitude. For such signals the timing fraction can be adjusted to optimize the time resolutions. Secondly, in many applications the signal countrate is sufficiently high that pairs of signal pulses can occur very close together. For such applications the constant fraction can be adjusted to minimize the pulse pair resolving time. The third advantage of the variable constant fraction is that the time delay from the peak of the pulse can be minimized for the applications where this is an important parameter. In general, it is believed that this is the first time adjustable constant fraction that has been used on the trailing edge ofthe signal pulse.
The time derivation process described has applications in many fields where an electrical signal, in the form of a voltage pulse, is to be analyzed for both time and amplitude information. For example, in the nuclear field, the signals derived from a scintillation detector or solid state detector contains information about when incident radiation reaches the detector as well as the magnitude (amplitude) or amount of the radiation. The proposed circuit, when used in conjunction with a single channel analyzer, establishes both the time and the amplitude information. THe use of a constant fraction timing technique based on the trailing edge of such signals would offer all the previously mentioned advantages over prior art techniques.
The purpose of performing the timing on the trailing edge is to allow sufficient time for decisions to be made on pulse peaks. The proposed constant fraction technique, for all practical purposes, almost entirely eliminates systematic timing errors due to pulse height variations. The fraction of the pulse height on which the timing is performed may be adjusted to obtain optimum time resolution due to noise or statistical contributions, and minimum time delay from the peak of the input signal.
SUMMARY OF THE INVENTION state, in the absence of an input signal, the comparator is, for example, in a high" state. However, when the signal level becomes more positive than a reference signal connected to the comparator state, the comparators output will switch from the high state to a low state. The low state of the comparator then causes another gate to switch the comparator reference to a voltage level that is derived from the stretcher circuit. During this interval, the stretcher circuit is measuring the peak amplitude of the input signal and storing this information on a capacitor. Thus, the information stored in the capacitor which has been switched to the gate, is equal to a constant fraction of the input pulse height. The comparator remains in the low state until the signal becomes less positive than the voltage stored on the capacitor at which time the output of the comparator is switched to the high state and a timing marker is generated.
It is, therefore, one object of the present invention to provide a circuit capable of producing a timing pulse based on a constant fraction of the trailing edge of an input signal.
Still another object of the present invention is to provide a circuit capable of producing a timing pulse based on a constant fraction of the trailing edge of an input signal wherein the systematic timing error may be essentially reduced to zero for all such signal shapes having an approximately constant bandwidth.
The features of my invention which I believe to be novel are set forth with particularity in the appended claims. My invention itself, however, both as to its or ganization and method of operation, together with further objects and advantages thereof, may be best understood by reference to the following description taken in conjunction with the accompanying drawings.
DESCRIPTION or THE DRAWINGS FIG. 1 is a partial schematic and block diagram of my signal processing circuit; and
FIG. 2 is a schematic circuit diagram of one embodiment ofa complete timing generator.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. I there is shown an input terminal 10 for applying an input signal to a buffer amplifier 42 the output of which is applied simultaneously to potentiometer 26 and to comparator 14. The voltage developed across potentiometer 26 is applied as one input to a stretcher circuit consisting of amplifiers 20 and 22 having a series diode 28 and a shunt capacitor 30 connected between the amplifiers. Shunt capacitor 30 has a gate circuit 38 connected parallel therewith and a lead 44 connected to one output of gate 46. The output of amplifier 22 is applied as an input to amplifier 20, by means of lead 40, and also as an input to gate 16 by means of lead 36. Reference voltage 32 is applied as another input to gate 16 by means of lead 34.
Referring now to FIG. 2 there is shown a complete circuit diagram of an embodiment of my invention. In the operation of my device, a positive going input signal is applied to input terminal 10 which signal is then applied as an input to buffer amplifier 42, consisting of active devices Q1 through 04 arranged in a typical buffer configuration. The outputof buffer amplifier 42 is applied, as an input, to terminal 3 of'an integrated circuit (IC) arranged as a comparator. In this particular situation, while I have choosen to use and show a devices 011-015 with the input thereto being shown as a pair of N-channel field effect transistors (FET). While FETs Q11 and Q12 are shown in a differential amplifier configuration, it will be obvious to those skilled in the art that various other types of active devices may be substituted for 011 and Q12.
The output of comparator 14 is then applied as an input to gate 46 consisting of Q5, Q6 and Q24 and the cathode terminal of Zener diode D1, the anode terminal of which is connected directly to tithing output terminal 18.
"The output of amplifier 20 is applied as an input to unity gain amplifier 22 through a series diode 28 arranged with its anode terminal connected to amplifier 20 and its cathode terminal connected to amplifier 22. Amplifier 22 consist of active devices 018 Q23. Connected between the cathode end of diode 28 and ground is capacitor 30, the function of which will be described hereinafter.
The output of unity gain amplifier 22 is derived at the emitter electrode of active device Q23 and is applied to the gate of PET Q12 by means of lead 40 to provide a feedback loop for the stretcher circuit. Lead 36 is connected to the junction of the gate of PET Q12 and the feedback loop, designated by lead 40, so as to provide one input to gate 16. Another input to gate 16 is provided by potentiometer 32 between a source of operating potential and ground and is applied by means of lead 34 to the base ofactive device 010.
which are connected in parallel with capacitor 30 and is provided with an input thereto, by means of lead 44, representing one output of detector 46.
, The gate circuit that detects the particular reference signal to be applied to pin 2 of comparator 14 involves active devices 05 Q (in detector 46 and gate 16). When comparator 14 is in a quiescent state, that is, with no signal applied to input terminal 10, it may be said to be in a high state ==+2.5 volts) in which event,
transistors 05, Q9 and 010 will be biased ON and a reference voltage, (E corresponding to the leading edge of the input signal (derived across resistor 32) is applied to pin 2 by means of active devices 010 and Q9. Any incoming signal appearing at input terminal 10, will switch comparator 14 to a low state =0.5
volts), in which event, active devices 05, Q9 and Q10 switch to an OFF condition and active devices Q6 and Q7 and 08 are then switched ON. When this latter condition occurs, the reference voltage derived from lead 36 is applied to pin 2 by means of active devices Q7 and This latter reference voltage (E is obtained from the peak detector and stretcher circuits (20, 22). The incoming attenuated input signal is applied to the differential pair Q11 and Q12 (by meansof potentiometer 26) thus causing active devices 014 and Q15 to be switched ON allowing capacitor 30 to be charged to a positive voltage. Capacitor 30 continues to be charged until the peak of the signal is reached at which time, a voltage equal to the capacitor voltage appears at the output of unity gain amplifier 22 and is fed back to the other input (the gate of 012) of the differential pair 011 and Q12. After the peak is reached and the signal is slightly less than the peak voltage, diode 28 is reversed biased causing the charge on capacitor 30 to be stored as it no longer has a leakage path. When this occurs,.the voltage at the output of unity gain amplifier 22 becomes greater than the signal applied to the gate of 011 and the differential pair (011 and Q12) are switched OFF. Thus, when the voltage stored on capacitor 30 appears at the emitter of active device Q23 (in unity gain amplifier 22) it will be proportional to the peak of the input signal. In this manner, the signal previously referred to as reference signal E is applied as one input to pin 2 of comparator 14 to generate a timing signal or marker. Thus, when a timing signal is generated and applied to output terminal 18 the timing pulse is applied, by means of lead 44, as an input to Q17 of clamp 38 to restore the voltage on capacitor 30 to zero, signifying that the processing is completed.
While I have described what is presently considered the preferred embodiment of my invention, it will be obvious to those skilled in the art that various other changes and modifications may be made therein without departing from the inventive concept, and it is aimed, therefore, to cover all such changes and modifications that may fall within the true spirit and scope of my invention.
What is claimed is:
1. A circuit for detecting an input signal and producing an output signal to indicate the occurrence of a peak in the inputsignal, comprising:
a comparator having first and second inputs and an output, said first input being responsive to the input signal;
a stretcher circuit having an input responsive to the input signal and an output for producing a signal proportional to the peak amplitude of the input signal; and
means for applying a predetermined reference voltage to the second input of said comparator while the, amplitude of the input signal is less than the reference voltage and forapplying the signal produced by said stretcher circuit to the second input of said comparator when the amplitude of the input signal exceeds the reference voltage, the output of said comparator thereafter changing state when the amplitude of the input signal decreases to the amplitude of the signal produced by said stretcher circuit to indicate the occurrence of a peak in the input signal.
2. The circuit of claim 1, wherein said means comprises:
a source for generating a predetermined reference voltage;and
a gating circuit having a first input responsive to the output of said comparator, a second input for receiving the predetermined reference voltage from said source, a third input responsive to the output of said stretcher circuit, and an output coupled to the second input of said comparator for selectively applying the predetermined reference voltage and the signal produced by said stretcher circuit to the second input of said comparator in response to signals produced by said comparator.
3. The circuit ofclaim l, which includes:
a buffer amplifier having an input responsive to the input signal and an output coupled to the first input of said comparator and the input of-said stretcher circuit.
4. The circuit of claim 1, which includes:
a potentiometer coupled to the input of said stretcher circuit and responsive to the input signal for applying a signal proportional to the input signal to said stretchercircuit.
5. The circuit of claim 1, wherein said stretcher circuit comprises:
a first amplifier having an input responsive to the input signal and an output;
a second amplifier having an input and an output;
a diode having an anode terminal connected to the output of said first amplifier and a cathode terminal connected to the input of said second amplifier; and i a capacitance responsive to the cathode terminal of said diode for storing a signal proportional to the peak amplitude of the input signal.
6. The circuit ofclaim 5, which includes:
a switch connected in parallel with said capacitance and responsive to the output of said comparator for discharging said capacitance when the input signal at the first input of said comparator is less than the signal applied to its second input.
7. The circuit of claim 6, wherein said means responsive to the output of said comparator comprises:
a source for generating a predetermined reference voltage, and
a gating circuit having a first input responsive to the output of said comparator, a second input for receiving the predetermined reference voltage from said source, a third input responsive to the output of said second amplifier in said stretcher circuit, and an output coupled to the second input of said comparator for selectively applying the predetermined reference voltage and the signal produced by said stretcher circuit to the second input of said comparator: and which includes a detector responsive to the output of said comparator for controlling the operation of said gating circuit to apply the reference voltage to the second input of said comparator while the amplitude of the input signal is less than the reference voltage and to apply the output signal produced by said stretcher circuit to the second input of the comparator when the amplitude of the input signal exceeds the reference voltage and for operating said switch to discharge said capacitance when the input signal is less than the signal applied to the second input of said comparator.
Claims (7)
1. A circuit for detecting an input signal and producing an output signal to indicate the occurrence of a peak in the input signal, comprising: a comparator having first and second inputs and an output, said first input being responsive to the input signal; a stretcher circuit having an input responsive to the input signal and an output for producing a signal proportional to the peak amplitude of the input signal; and means for applying a predetermined reference voltage to the second input of said comparator while the amplitude of the input signal is less than the reference voltage and for applying the signal produced by said stretcher circuit to the second input of said comparator when the amplitude of the input signal exceeds the reference voltage, the output of said comparator thereafter changing state when the amplitude of the input signal decreases to the amplitude of the signal produced by said stretcher circuit to indicate the occurrence of a peak in the input signal.
1. A circuit for detecting an input signal and producing an output signal to indicate the occurrence of a peak in the input signal, comprising: a comparator having first and second inputs and an output, said first input being responsive to the input signal; a stretcher circuit having an input responsive to the input signal and an output for producing a signal proportional to the peak amplitude of the input signal; and means for applying a predetermined reference voltage to the second input of said comparator while the amplitude of the input signal is less than the reference voltage and for applying the signal produced by said stretcher circuit to the second input of said comparator when the amplitude of the input signal exceeds the reference voltage, the output of said comparator thereafter changing state when the amplitude of the input signal decreases to the amplitude of the signal produced by said stretcher circuit to indicate the occurrence of a peak in the input signal.
2. The circuit of claim 1, wherein said means comprises: a source for generating a predetermined reference voltage; and a gating circuit having a first input responsive to the output of said comparator, a second input for receiving the predetermined reference voltage from said source, a third input responsive to the output of said stretcher circuit, and an output coupled to the second input of said comparator for selectively applying the predetermined reference voltage and the signal produced by said stretcher circuit to the second input of said comparator in response to signals produced by said comparator.
3. The circuit of claim 1, which includes: a buffer amplifier having an input responsive to the input signal and an output coupled to the first input of said comparator and the input of said stretcher circuit.
4. The circuit of claim 1, which includes: a potentiometer coupled to the input of said stretcher circuit and responsive to the input signal for applying a signal proportional to the input signal to said stretcher circuit.
5. The circuit of claim 1, wherein said stretcher circuit comprises: a first amplifier having an input responsive to the input signal and an output; a second amplifier having an input and an output; a diode having an anode terminal connected to the output of said first amplifier and a cathode terminal connected to the input of said second amplifier; and a capacitance responsive to the cathode terminal of said diode for storing a signal proportional to the peak amplitude of the input signal.
6. The circuit of claim 5, which includes: a switch connected in parallel with said capacitance and responsive to the output of said comparator for discharging said capacitance when the input signal at the first input of said comparator is less than the signal applied to its second input.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5335970A | 1970-07-09 | 1970-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3714464A true US3714464A (en) | 1973-01-30 |
Family
ID=21983676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US00053359A Expired - Lifetime US3714464A (en) | 1970-07-09 | 1970-07-09 | Detecting circuit for indicating occurrence of peak in an input signal |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US3714464A (en) |
| JP (1) | JPS5238376B1 (en) |
| DE (1) | DE2134160A1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3784921A (en) * | 1973-03-23 | 1974-01-08 | Gen Motors Corp | Circuit indicating change and steady state of a dc signal |
| US3797894A (en) * | 1973-01-24 | 1974-03-19 | Bendix Corp | Combination peak detector and level detector for use in an adaptive braking system |
| USB387363I5 (en) * | 1970-11-23 | 1975-01-28 | ||
| US3869624A (en) * | 1973-05-21 | 1975-03-04 | Nasa | Peak holding circuit for extremely narrow pulses |
| US4020423A (en) * | 1971-05-10 | 1977-04-26 | Carl Schenck Ag | Method and circuit arrangement for producing and transmitting electrical reference pulses |
| US4123674A (en) * | 1975-12-12 | 1978-10-31 | Sun Electric Corporation | Voltage peak short store system |
| US4160175A (en) * | 1978-01-12 | 1979-07-03 | The United States Of America As Represented By The Secretary Of The Navy | Differential threshold detector |
| US5333162A (en) * | 1993-02-23 | 1994-07-26 | The United States Of America As Represented By The United States Department Of Energy | High resolution time interval counter |
| US6687006B2 (en) * | 2001-09-28 | 2004-02-03 | Agilent Technologies, Inc. | Heterodyne based optical spectrum analysis with reduced data acquisition requirement |
| US7439776B1 (en) * | 2006-04-14 | 2008-10-21 | Atheros Communications, Inc. | Technique to increase the speed of a peak detector |
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| US3116458A (en) * | 1959-12-21 | 1963-12-31 | Ibm | Peak sensing system employing sampling and logic circuits converting analog input topolarity-indicating digital output |
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| US3465169A (en) * | 1966-11-14 | 1969-09-02 | Bunker Ramo | Circuit apparatus for detecting recurring input signals within a wide amplitude range |
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- 1970-07-09 US US00053359A patent/US3714464A/en not_active Expired - Lifetime
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- 1971-07-08 DE DE19712134160 patent/DE2134160A1/en active Pending
- 1971-07-09 JP JP46050395A patent/JPS5238376B1/ja active Pending
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| US2834883A (en) * | 1955-10-12 | 1958-05-13 | Sperry Rand Corp | Peak amplitude indicator |
| US3116458A (en) * | 1959-12-21 | 1963-12-31 | Ibm | Peak sensing system employing sampling and logic circuits converting analog input topolarity-indicating digital output |
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| US3465169A (en) * | 1966-11-14 | 1969-09-02 | Bunker Ramo | Circuit apparatus for detecting recurring input signals within a wide amplitude range |
| US3553593A (en) * | 1968-01-10 | 1971-01-05 | Westinghouse Electric Corp | Pulse width measuring circuit |
| US3564287A (en) * | 1968-07-25 | 1971-02-16 | Us Navy | Maximum seeking zero order hold circuit |
Non-Patent Citations (1)
| Title |
|---|
| Bjorkman and Brondum, Peak Picking and Noise Suppression Circuitry , IBM Technical Disclosure Bulletin, Vol. 9, No. 6, Nov. 1966 p. 508 589. * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USB387363I5 (en) * | 1970-11-23 | 1975-01-28 | ||
| US3927378A (en) * | 1970-11-23 | 1975-12-16 | Ericsson Telefon Ab L M | Demodulator |
| US4020423A (en) * | 1971-05-10 | 1977-04-26 | Carl Schenck Ag | Method and circuit arrangement for producing and transmitting electrical reference pulses |
| US3797894A (en) * | 1973-01-24 | 1974-03-19 | Bendix Corp | Combination peak detector and level detector for use in an adaptive braking system |
| US3784921A (en) * | 1973-03-23 | 1974-01-08 | Gen Motors Corp | Circuit indicating change and steady state of a dc signal |
| US3869624A (en) * | 1973-05-21 | 1975-03-04 | Nasa | Peak holding circuit for extremely narrow pulses |
| US4123674A (en) * | 1975-12-12 | 1978-10-31 | Sun Electric Corporation | Voltage peak short store system |
| US4160175A (en) * | 1978-01-12 | 1979-07-03 | The United States Of America As Represented By The Secretary Of The Navy | Differential threshold detector |
| US5333162A (en) * | 1993-02-23 | 1994-07-26 | The United States Of America As Represented By The United States Department Of Energy | High resolution time interval counter |
| US6687006B2 (en) * | 2001-09-28 | 2004-02-03 | Agilent Technologies, Inc. | Heterodyne based optical spectrum analysis with reduced data acquisition requirement |
| US7439776B1 (en) * | 2006-04-14 | 2008-10-21 | Atheros Communications, Inc. | Technique to increase the speed of a peak detector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5238376B1 (en) | 1977-09-28 |
| DE2134160A1 (en) | 1972-01-20 |
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