US3702441A - Frequency synthesizing system - Google Patents

Frequency synthesizing system Download PDF

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US3702441A
US3702441A US185261A US3702441DA US3702441A US 3702441 A US3702441 A US 3702441A US 185261 A US185261 A US 185261A US 3702441D A US3702441D A US 3702441DA US 3702441 A US3702441 A US 3702441A
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frequency
value
variable
output
produce
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Keith R Thrower
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Aeroflex Burnham Ltd
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Racal Instruments Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B21/00—Generation of oscillations by combining unmodulated signals of different frequencies
    • H03B21/01—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies
    • H03B21/02—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies by plural beating, i.e. for frequency synthesis ; Beating in combination with multiplication or division of frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B21/00—Generation of oscillations by combining unmodulated signals of different frequencies
    • H03B21/01—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies
    • H03B21/04—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies using several similar stages

Definitions

  • a frequency synthesizing system includes frequency synthesizing means operative to produce an adjustable intermediate frequency, frequency dividing means for dividing the intermediate frequency by an adjustable division factor to produce an output frequency, setting means operable to set up the desired value of the output frequency, and control means automatically responsive to the setting means to adjust the synthesizing means and the dividing means in dependence on the desired value of the output.
  • SHEET 2 OF 5 mm mm The invention relates to frequency synthesizers.
  • a frequency synthesizing system including frequency synthesizing means operative to produce an adjustable intermediate frequency, frequency dividing means connected to divide the intermediate frequency by an adjustable division factor to produce an output frequency, setting means operable to set up the desired value of the output frequency, and control means automatically responsive to the setting means to adjust the synthesizing means and the dividing means such that the value of intermediate frequency produced by the synthesizing means produces, when divided by the division factor of the dividing means, the desired output frequency.
  • a method of frequency synthesis in which an intermediate frequency is synthesized and then divided to produce the desired output frequency, the division factor being automatically selected according to a predetermined program relating values of division-factors to values of the desired output frequency, and the intermediate frequency being automatically selected according to the product of the division factor and the third output frequency, such that the intennediate frequency, when divided by the division factor, gives the desired output frequency.
  • the control unit 24 (in combination with the indices selector 26) sets up a multiplier unit 28.
  • the multiplierunit 28 is connected to control the synthes-' izer blocks to 16 such that the value of the frequency F1 on line 18 is, when divided by the division factor Q or the divider 20, equal to the desired value of the vention, and a method of frequency synthesis according to the invention, will now be described, by way of example only, and with reference to the accompanying drawings in which:
  • FIG. 1 is a block circuit diagram of the system
  • FIGS. 2, 3 and 4 are more detailed block circuit diagrams of various parts of the system of FIG. 1;
  • FIG. 5 shows waveforms occurring in the system.
  • the synthesizer system comprises frequency synthesizing blocks l0, 12, 14 and 16 which are settable by an operator in a manner to be described to produce an output frequency F l on a line 18.
  • the frequency F1 is fed through an automatically variable frequency divider 20 to produce the required synthesized frequency F0 on an output line 22.
  • the divider 20 comprises, in this example, two frequency dividing chains in series, the first dividing chain dividing by 10'' and the second frequency dividing chain dividing by 2", where m can be 0, l or 2, and n can be 0,1, 2 or 3.
  • the synthesizer system has a control panel 24 with, in this example, five manually operable controls 24A to 24E which are used by the operator to set up the required decade digits of the frequency F0 to be synthesized.
  • the frequency range covered is 0 to 160 MHz (actually 0.1 to 159.99 MHz).
  • the controls 24A to 24D each have 10 settings, Q"to.9, and respectively set up the number of tens of KHz in the required output frequency, the number of hundreds of KI-Iz, the number of units of MHz, and the number of tens of MHz.
  • the control 24E sets the number of hundreds of MHz in the required output frequency, and thus has two settings of l and 0.
  • the control panel 24 controls an indices selector 26 which, for each desired frequency value set up on the control panel 24,
  • the synthesizer blocks 10, 12 and 14 can be set so that the frequency F1 on line l8 is variable between and MHz (actually 80 and 159.99 MHz), that is, variable over one octave.
  • Q is variable from 1 (when m and n are both zero) and 800 (when m is 2 and n is 3), thus making F0 variable between 0.1 MHz and 159.99 MHz.
  • the synthesizer block 10 synthesizes the digit D (see equation 1). It is connectedto receive a fixed frequen cy Fr on a line 40 which, in this example, is 0.6 MHz,
  • switch 44 which has 10 settings, numbered 0, 1, 2, .j. 9.
  • the 10 input terminals of the switch 44 are respectively connected to receive inputs of different frequency.
  • an input frequency of 5.4 MHz is connected to line 42, and the input frequency increases by 0.1 MHz per switch setting, up to 6.3 for setting 9.
  • the illustration of switch 44 is purely diagrammatic, and in a practical case the switch would be electronic in nature. As shown, it is controlled by a logic unit 46 which is connected by a channel 48 to the multiplier unit 28.
  • the channel 48 has four lines which carry, in binary coded decimal (BCD) form, signals representing that setting of switch 44 which, as determined by the multiplier 28, is required in order to produce the correct value of thedigit D in the frequency F1 on line 18. If the multiplier 28 determines that the required value of D is 2, say, then it produces, in BCD form, a signal representing decimal 2 on channel 48 and switch 44 is set into setting 2 by the-logic unit 46 thus giving F a value of 5.6 MHz; and similarly for the other values of D.
  • BCD binary coded decimal
  • the multiplier 28 determines that the desired value of the digit C is 6, then it produces, in BCD form, a signal on channel 58 representing decimal 6 and the logic unit 56 is caused to set the switch 54 into setting .6, thus givingF a value of 6 .0 MHz; and correspondingly for the othervalues of.
  • the frequency F B is controlled by a switch 66 which has settings, 0,' l, 2, 9.
  • the IO'inputs of the switch 66 are respectively connected to receive fixed frequencies of 4, 5, 6, Q 188 13 MHz.
  • Switch 66 (which, like the switches 44 and 54, is shown only diagrammatically) is controlled by a logic unit 68 which is connected by a channel 70 to the multiplier 28.
  • Channel 70 has four lines which carry, in BCD form, the required value of the digit B as determined by the multiplier 28.
  • a signal representing decimal 6 is produced in BCD form on channel 70 and the logic unit 68 is caused to set switch 66 into setting 6 to give F B a value of 10 MHz; and correspondingly for the other values of B. Therefore F, 4 B 1 1
  • the frequency F is controlled by a switch 72 which has eight settings, 0, l, 2, 7.
  • the eight inputs of the switch 72' are respectively connected to receive frequencies of 70, 80, 140 MHz.
  • Switch 72 (which, like the other switches, is shown only diagrammatically) is controlled by a logic unit 74 which is connected by a channel 76 to the multiplier 28.
  • the logic unit 74 responds to the signal received on channel 76 by producing an output indicating the desired value of the digit A and setting the switch 72 accordingly.
  • the switch. 72 is set intosetting6 and soon. It will be seen that the range of possible values for F A is such that of the signal received via channel 76. The reason for this is explained later. Table I below indicates the switch setting produced by the logic unit 74 for each signal value on channel 76.
  • the indices selector 26 is connected to the control panel 24 by five channels 90, 92, 94, 96, 98.
  • Each of channels to 96 has four lines which carry, in BCD form, signals representing the setting of the controls 24A to 24D.
  • Channel 98 has only one line which carries a binary 0 or a binary 1 dependent on whether control 24E is set to 0 or 1.
  • the indices selec-' tor 26 has an output channel 100 having seven lines which can respectively carry the binary signals m0, m1, m2, n0, n1, n2, n3.
  • the selector 26 determines that the required value of 'Q is 8, then the required values of m and n are 0 and 3, and it sets lines m and n to binary l and the remaining five lines in channel 100 to binary 0, and similarly for the other values of m and n.
  • Table H shows the values of Q and F0 (in MHz) for different values of m and n, having regard to the fact that F1 is variable between 80 and (actually 159.99) MHz.
  • the serial BCD multiplier unit 136 (see FIG. 4) comprises four AND gates 148 to 151,'all of which are connected to receive the clock signals on the line 134 and which have their second inputs respectively connected to receive the signals P2 to P5.
  • the outputs of the AND gates 148 to 151 are respectively connected to the inputs of scale of ten cascaded decimal counters 153 to 156.
  • the outputs of the counters are respectively connected to BCD encoders 158 to 164. The latter respectively feed the channels 48, 58, 70 and 76.
  • Each signal P2 opens the gate 148. Clock pulses from line 134 therefore pass through the gate 148, and are counted up by the counter 153.
  • the number of clock pulses passing into the counter during each pulse of the signal P2 is proportional to the length of that pulse, and thus directly proportional to the BCD value presented on channel 90. In other words, the number of pulses counted by counter 153 during each pulse of signal P2 is equal to the product of the decimal value set up by the control 24A and the division factor, Q, selected by the indices selector 26.
  • the number of clock pulses on line 134 which are counted by the counter 154 is therefore equal to the product of the setting of control 24B and the division factor Q.
  • pulses P4 and P5 open gates 150 and 151 and cause the counters 155 and 156 to count the products of Q and the settings of the controls 24C and 24D. Since the counters are cascaded, their outputs continuously carry, in decimal form, the last four digits of the product of Q and the number set up by the controls 24A to 24D.
  • the BCD encoders 158 to 164 convert the decimal signals into BCD form and respectively energize the channels 48, 58, 70 and 76.
  • the counters are reset during each pulse 411 by means of a line 165, while the encoders are updated during each pulse (#1 (but before the counters are reset) by means of a line 166.
  • the product produced by the multiplier 28 is not directly affected by the setting of the control 24E.
  • the product produced is indirectly affected by the setting of the control 24E since the latter affects the value of the division factor Q which in turn affects the value of the product produced by the multiplier 28.
  • the output of the multiplier 28 does not indicate the value of the most significant digit of the required value of F1.
  • F1 cannot be more than 159.99 MHz, this digit can only be decimal l or 0.
  • F 1 cannot be less than 80 MHz. Therefore, when the decimal value of the digit presented on channel 76 is 8 or 9, the most significant digit of F 1 must be zero, and when the decimal value of the digit on channel 76 has the value of 0, l, 2, 3, 4 or 5 (it cannot have the value of 6 or 7), the most significant digit of F 1 must be 1.
  • the output from the multiplier 28 implicitly indicates the value of the most significant digit of F l
  • the decimal value of the output on channel 76 represents, therefore, the number of tens of MHZ in the required value of F 1. This number must lie within the range 8 to (since the minimum value of F1 is 80 MHz and the maximum is 159.99 MHz). If the required number of tens of MHz is 8 or 9, this is indicated directly by the decimal value of the output in channel 76; ifthe number oftensis 10, 1 1, l2, 13, 14 or 15, this is indicated in channel 76 by the number 0, 1, 2, 3, 4 or 5, respectively.
  • the controls 24A to 24E would respectively be set to decimal values of 3, 4, 9, 2 and 0 and BCD coded versions of these decimal values would be presented to the indices selector 26 on the channels to 98.
  • the BCD values of the settings of controls 24A to 24D would be presented on channels 90 to 96 to the multiplier 28.
  • the indices selector 26 would determine that the required value for m is 0 and for n is 2, that is, Q 4. Therefore, the indices selector 26 would produce a binary l on the lines m0 and n2 in the channel 100, thus enabling the AND gates 102 and 124 (FIG. 2) of the divider 20, the other lines of the channel being maintained at binary 0.
  • the multiplier unit 28 multiplies the decimal value of the total signal presented to it on channels 90 to 96 by the division factor Q.
  • the resultant product is 117.72, of which, as explained above, only the last four digits appear on the output channels 48, 58, 70 and 76.
  • channel 48 carries decimal 2
  • channel 58 carries decimal 7
  • channel 70 carries decimal 7
  • channel 76 carries decimal 1, these numbers of course being presented in BCD form.
  • the logic unit 46 sets the switch 44 (FIG. 1) into setting 2, thus giving frequency F D a value of 5.6MH2. Therefore, from equations (4) and (5), F2 is 6.2MHz, and F3 is 0.62MHz.
  • logic unit 56 sets the switch 54 into setting 7, thus giving F a value of 6.1MHz. Therefore, from equation (7), F4 becomes 6.72 MHz.
  • the logic unit 68 determines that the required value of B is 7, and sets the switch 66 into the setting 7, thus giving the signal F a value of l lMHz.
  • the logic unit 74 determines from the signal on channel 76 (decimal 1)- that the required value of A is 3 (see Table l) and sets the switch 72 into the setting 3, thus giving the signal F A a value of 100MHz. Therefore, from equation (10) it follows that the synthesizer block 14 produces an output frequency, F5, of l 1 lMHz.
  • Table III shows the logic required to produce the signals m0, ml, m2, n0, n1, n2, n3.
  • the decimal numbers in brackets indicate the decimal values of the digits K, to K
  • the indices selector 26 contains logic required to satisfy Table III and to produce the required values of signals m0 to n3 for each required value of F0.
  • FIG. 2 illustrates the divider 20. It comprises three two-input AND gates 102, 104, and 106 which are respectively connected to be enabled by the signals m0, ml, and m2.
  • Gate 102 has its second input connected directly to line 18 (FIG. 1).
  • Gate 104 has its second input connected to line 18 through a frequency divider 108 having a fixed division factor of 10, while the second input of gate 106 is connected to line 18 through frequency divider 108 and a second frequency divider 1 10 which also has a fixed division factor of 10.
  • the outputs of the gates 102 to 106 are connected through an OR gate 112 to a chain of three binary dividers or flip-flops 114, 116, 118.
  • the output of the OR gate 112 is connected to one input of a two-input AND gate 120, whilethe outputs of the flip-flops 114 to 118' are respectively connected to one input of further two-input AND gates 122, 124, 126.
  • the second input of each of the AND gates 120 to 126 is respectively connected to receive the signals n0, n1, n2, n3.
  • the outputs of the AND gates 120 to 126 are connected to the line 22 (FIG. 1) throughan OR gate 128.
  • FIG. 2 makes clear how the total division factor Q applied between lines 18 and 22 is determined by the values of the signals m0 to n3.
  • the multiplier 28 determines the value required for the frequency F1 in order to produce the correct value for F0 having regard to the selected division factor, Q, and will now be described in detail.
  • the multiplier 28 comprises a synchronous clock divider 126 which is connected to line 128 which comprises pulses at a fixed repetition frequency of 10/800 MHz, each pulse thus defining a period, T, of so s; these pulses are applied as one input to a five-phase clock generator 130 and also to a pulse generator 132.
  • the divider 126 has a second output, on a line 134, comprising pulses at a. frequency of 10Q/800 MHz, where Q is determined by the values of the signals presented on the channel 100: line 134 feeds a serial dynamic BCD multiplier unit136.
  • the five-phase clock generator 130 has five output lines which respectively carry signals 411 to 5.
  • the waveforms of the outputs 4:1 to s are shown in FIG. 5.
  • Each output comprises a succession of negative 800 1.8 pulses but the outputs are phase displaced with respect to each other.
  • the pulse generator 132 is controlled by the binary coded decimal signals received from the control panel 24 by means of the channels 90 to 96 and has four output lines 138, 140, 142, and 144 carrying signals P2, P3, P4 and P5 respectively.
  • a signal P2 is produced on line 138 under control of theBCD-sigrral received on channel 90.
  • the signal P2 comprises a series of positive pulses whose trailing edges are in phase with the pulses of the signal (#2 but the length of each pulse of the signal P2, in multiples of ;:8, is directly proportional to the value of the BCD signal on the channel 90.
  • each pulse of the signal P2 will have a length of 80p.S (that is, 1 times 80,48); If the BCD signal on channel 90 is decimal 6, for example, then each pulse of the signal P2 will have a length of 480p.S (that is, 6 times 80p.S or six-tenths of the length of each pulse of the signal (1)2); and so on.
  • the signals P3 to P5 are controlled by the BCD signals presented on channels 92 to 96 respectively and, as shown in FIG. 5, the signals P3 to P5 respectively comprise trains of pulses whose trailing edges are in phase with the signals 3 to screening and relatively high noise values.
  • the synthesizer described and illustrated uses comparatively low frequencies which do not impose unusually difficult screening requirements or produce unacceptable noise levels (in fact, the divider 20 has the effect of reducing the noise when the division factor Q is relatively high).
  • the synthesizer described and illustrated overcomes these disadvantages by virtue of its use of the divider 20.
  • the provision of the indices selector 26 and the multiplier 28 ensures that the divider 20 does not render the synthesizer difficult to set up: if, for example, the indices selector 26 and the multiplier 28 were not present, and the divider 20 were made manually settable, then it would be necessary for the operator first to calculate or otherwise ascertain the correct division factor required for his desired output frequency, then to calculate the corresponding value of F1, and finally to set up the desired values of Q and Fl. This would be a time consuming process, and would also suffer from the disadvantage that the value of the output frequency F would not be immediately apparent from the setting of the controls of the synthesizer. These disadvantages are overcome by the provision of the indices selector 26 and the multiplier 28.
  • Each synthesizer block 10 to 16 may, for example, comprise a simple mixer with filtering means to select the upper sideband as the required output frequency. Instead, however, each synthesizer block may comprise a mixer which mixes one of the inputfrequencies with the output of a voltage controlled oscillator, and a phase sensitive detector connected to compare the lower sideband output from the mixer with the other of the two input frequencies, the phase sensitive detector being connected to control the voltage controlled oscillator in a sense such as to tend to maintain the difference between the two frequencies compared at zero.
  • the divider 20 has been indicated as dividing by a factor given by 10'". 2" where m and n are variable, the divider may divide by any other suitable variable factor of different mathematical'form.
  • the system is fitted with a range switch which enables different possible frequency ranges for the output frequency F0 to be selected: for example, for range setting l,Fo. would be variable between 10 and 159.99, for range setting 2,F0 would be variable between 1 and 15.999, and for range setting 3,F0 would be variable between 0.1 and 1.5999.
  • the selection of the divide-by-lO dividers in the divider 20 would be controlled by the range switch and would not be controlled by the indices selector 26 which would only determine changes in the value of the signal n.
  • the range switch would select neither of the two divide-by-lO dividers 108, 110.
  • the switch would select divider 108 alone, while in setting 3 it would select both dividers 108 and 110.
  • the multiplier 28 would only respond to changes in the signal n and would be unaffected by the range change switch.
  • This method of range changing is advantageous in that it reduces the multiplication factor to be employed by the multiplier 28 to a maximum of 8. Since the multiplier 28 is dynamic in operation, it takes longer to carry out multiplication at high multiplication factors than at low factors, and the range changing method described enables excessive delays to be avoided.
  • a frequency synthesizing system comprising frequency synthesizing means operative to produce an adjustable intermediate frequency, frequency dividing means connected to receive the intermediate frequency and to divide it by an ad- 7 -justable division factor to produce an output frequency, setting means operable to set up a desired value of the output frequency, and control means connected to the setting means to respond to the value of the output frequency set up thereby and also connected to the synthesizing means and the dividing means to control the values of the said intermediate frequency and of the division factor in dependence on the value of the output frequency set up, such that the value of intermediate frequency produces, when divided by the division factor of the dividing means, the desired output frequency.
  • control means comprises selecting means operative to produce, for each desired value of the output frequency set up by the setting means, a different and predetermined first control output representing a particular value of division factor, multiplying means connected to the setting means and the selecting means and operative to multiply the desired value of the output frequency set up by the setting means and the first control output to produce a second control output, means feeding the first control output to the dividing means to set the division factor thereof, and
  • the dividing means comprises means for dividing the intermediate frequency by an additional factor of Y, where Y is a fixed integer and y is an integer which is manually variable to alter the range of the output frequency.
  • the dividing means comprises means operative to divide the intermediate frequency by a division factor of X Y", where X and Y are fixed integers, and x and y are integers which are varied in dependence on the value of the fust control output, whereby to vary the value of the division factor.
  • the frequency synthesizing means comprises a plurality of synthesizer arrangements each operative to synthesize a separate frequency
  • summing means connected to sum the separate frequencies to produce the said intermediate frequency
  • each synthesizing arrangement comprising means responsive to the control means to set the value of the said separate frequency which it synthesizes whereby that frequency determines the value of a respective one of the decades of the said intermediate frequency.
  • the frequency synthesizing means comprises a plurality of synthesizer arrangements each operative to synthesize a respective individually variable frequency which is variable stepwise from a predetermined datum frequency, and
  • summing means for summing the individually variable frequencies to produce the said intermediate frequency
  • the frequency synthesizing means comprises a plurality of synthesizer arrangements each operative to synthesize a separate frequency
  • each synthesizer arrangement comprising means for adding two frequencies each having a predetermined datum value and at least one of which is variable stepwise in predetermined steps from the datum value, and means responsive to the said second control output to vary the variable frequency, the said datum value and the sizes of the step variations in the variable frequencies being such that the frequency synthesized by each synthesizer arrangement determines the value of a respective one of the decades of the said intermediate frequency.
  • the intermediate frequency comprises the sum of a fixed frequency and a variable frequency, the variable frequency comprising four decades, and in which:
  • the firstv synthesizer arrangement is connected to add a firstfixed frequency fixed at .a predetermined predetermined steps'froma predetermined datum value, and includes means responsive to the said second control output to vary the value of the second variable frequency stepwise whereby to produce a second synthesized frequency,
  • the said output summing means is connected to receive and sum the said second and third synthesized frequencies whereby to produce the said intermediate frequency, a
  • the datum values of the first fixed frequency and of the first, second, third and fourth variable frequencies and the sizes of the predetermined steps of the latter frequencies are such that the first variable frequency is variable to vary the value of the least significant decade in the said intermediate frequency, the second variable frequency is variable to vary the value of the, next more significant decade thereof, and the third and fourth variable frequencies are respectively variable to vary the values of the two most significant decades thereof.

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US185261A 1970-10-02 1971-09-30 Frequency synthesizing system Expired - Lifetime US3702441A (en)

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GB4686670A GB1372188A (en) 1970-10-02 1970-10-02 Frequency synthesizers

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3842354A (en) * 1972-06-29 1974-10-15 Sanders Associates Inc Digital sweep frequency generator employing linear sequence generators
US3956703A (en) * 1974-04-22 1976-05-11 U.S. Philips Corporation Multichannel generator
US4109208A (en) * 1971-07-31 1978-08-22 Nippon Gakki Seizo Kabushiki Kaisha Waveform producing system
US4318045A (en) * 1980-04-10 1982-03-02 Rca Corporation Symmetrical waveform signal generator having coherent frequency shift capability
US4494073A (en) * 1982-09-27 1985-01-15 Cubic Corporation Frequency generator using composite digitally controlled oscillators
US4878027A (en) * 1987-08-03 1989-10-31 Hewlett-Packard Company Direct frequency synthesizer using powers of two synthesis techniques

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293561A (en) * 1965-09-27 1966-12-20 Rutherford Electronics Co Frequency synthesizer
US3513412A (en) * 1966-09-28 1970-05-19 Us Navy Minimum peak power signal synthesizer
US3566278A (en) * 1968-05-31 1971-02-23 Gen Radio Co Swept frequency synthesizer with frequency marker generation capability

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372347A (en) * 1966-04-29 1968-03-05 Monsanto Co Frequency synthesizer employing minimal number of driving frequencies
NL6705448A (de) * 1967-04-18 1968-10-21
US3509483A (en) * 1968-05-31 1970-04-28 Gen Radio Co Frequency synthesizer apparatus
US3588732A (en) * 1969-01-16 1971-06-28 Collins Radio Co Frequency synthesizer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293561A (en) * 1965-09-27 1966-12-20 Rutherford Electronics Co Frequency synthesizer
US3513412A (en) * 1966-09-28 1970-05-19 Us Navy Minimum peak power signal synthesizer
US3566278A (en) * 1968-05-31 1971-02-23 Gen Radio Co Swept frequency synthesizer with frequency marker generation capability

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4109208A (en) * 1971-07-31 1978-08-22 Nippon Gakki Seizo Kabushiki Kaisha Waveform producing system
US3842354A (en) * 1972-06-29 1974-10-15 Sanders Associates Inc Digital sweep frequency generator employing linear sequence generators
US3956703A (en) * 1974-04-22 1976-05-11 U.S. Philips Corporation Multichannel generator
US4318045A (en) * 1980-04-10 1982-03-02 Rca Corporation Symmetrical waveform signal generator having coherent frequency shift capability
US4494073A (en) * 1982-09-27 1985-01-15 Cubic Corporation Frequency generator using composite digitally controlled oscillators
US4878027A (en) * 1987-08-03 1989-10-31 Hewlett-Packard Company Direct frequency synthesizer using powers of two synthesis techniques

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DE2149128B2 (de) 1981-01-15
DE2149128A1 (de) 1972-05-10
FR2110197B1 (de) 1976-03-26
DE2149128C3 (de) 1981-10-29
GB1372188A (en) 1974-10-30
FR2110197A1 (de) 1972-06-02

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