US3701104A

US3701104A - Address synchronizer

Info

Publication number: US3701104A
Application number: US757870A
Authority: US
Inventors: Neil L Wiseman
Original assignee: Singer Co
Current assignee: Singer Co
Priority date: 1968-09-06
Filing date: 1968-09-06
Publication date: 1972-10-24
Anticipated expiration: 1989-10-24

Abstract

A synchronizer for the address counter of an on-the-fly print wheel has two flip-flops complemented by paired photoelectric signals. One flip-flop responds to all character pads, or spaces, of the wheel and the other to all but one. When the two flipflops fall out of step, a synchronizing signal is gated for setting the address counter and for also resynchronizing the two flip-flops, which then stay synchronized until the next unpaired signal.

Description

United States Patent Wiseman 1 Oct. 24, 1972 [s41 ADDRESS SYNCHRONIZER 3 P:- 3 B n v I 4 N 12 M n t I 72 inventor: Neil L. Wiseman, San Ramon, Calif. 1962 u e 0 [73] Assignee: The Singer Company m Em P I J H mary mmerau enon [22] Sept 1968 Assistant Examiner-Paul R. Woods [21] Appl. No.; 757,870 Attorney-Charles R. Lepchinsky 57 ABSTRACT [52] U.S. Cl. ..340/l72.5, 307/216, 307/269,

101/93 C A synchronizer for the address counter of an on-the- 511 1m. (:1 .00 7/02, 006k 15/06 y P wheel a w flinflopspomplememed y {581 Field of Search ..340/172.5; 101/93; 307/216, Paved photoelecmc signals- One p p responds to 307/269, 208; 328/48 all character pads, or spaces, of the wheel and the other to all but one. When the two flip-flops fall out of [56] References Cit d step, a synchronizing signal is gated for setting the address counter and for also resynchronizing the two UNITED STATES PATENTS flip-flops, which then stay synchronized until the next 3,395,352 7/1968 McCammon ..328/48 X 3,430,2 Foure at a]. 9 8 Figures OTHER PUBLICATIONS IBM Tech. Disclosure Bulletin, Vol. 7, No. 9, Februai 5') 26 FM IOTJCIEENCE PRINT 'NPUT com onsc'roa comm 54 ADDRESS COUNTER V IL 1[ Ga PATENTEMM 2 2 3 10 1. 104 sum 1 or 4 INVENTOR.

91M BNiseman BY Z //l// PATENTEDBI am 36101; 104

SHEtT 2 [IF 4 COlNCIDENQE PRINT NPUT CODER DETECTOR CONTROL 1 6 ADDRESS 44 COUNTER U Gu- 2b ADDRESS SYNCHRONIZER BACKGROUND OF THE INVENTION 1 Field of the Invention The present invention relates to on-the-fly printers and, more particularly, to synchronizers for the address counters therefor.

2. Description of the Prior Art It is known to generate a single synchronizing signal from an element mechanically coupled to the print wheel, such as a magnet, as in US. Pat. No. 3,131,627, or an electric contact, or a photoelectric cell responding to a single small aperture as in US. Pat. No. 2,800,073. A copending application of Beat A. Koeher, U.S. Ser. No. 754,431, filed Aug. 2l, 1968, now US. Pat. No. 3,566,782 issued Mar. 2, I971. discloses a counter-synchronizer that is responsive to an unpaired signal pulse in paired trains of pulses generated photoelectrically from the print wheel itself. That system requires that each pulse of one train be completely bracketed in time by its pairing pulse. That requirement imposes on the apparatus several limitations of size, spacing, speed and tolerances to vibration.

SUMMARY OF THE INVENTION The system of the present invention is applicable to a spoked wheel, or the like, where a single signal per revolution is not readily obtainable. It utilizes a single difference between two trains of signals. It applies paired signal pulses to two flip-flops and later tests their states. The testing time is made short and the test is spaced with respect to those pulses for providing large tolerances in the duration of the signals and the times of their occurrence.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages will be apparent from the following description of a specific embodiment of the invention, reference being had to the accompanying drawings wherein:

FIG. 1 is a partial perspective view of an on-the-fly printer embodying my present invention;

FIG. 2 is an enlarged detail of the apparatus of FIG.

FIG. 3 is an enlarged sectional view taken along the lines 3-3 of FIG. 2;

FIG. 4 is a partially schematic diagram of a logic and control system;

FIG. 5 is a graph showing waveforms illustrating part of the operation of the apparatus of FIG. 4;

FIG. 6 is a graph showing in greater detail the sequences of certain operations in the time interval t,- t,, in FIG. 5;

FIG. 7 is a view similar to FIG. 2 for showing a modified construction; and

FIG. 8 is a graph similar to FIG. 5 for illustrating the operation of the construction of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. I shows a print wheel 10 having sixty-four, regularly spaced character pads, indicated generally at 22, each carried on the end of a radial, flexible spoke 20. The wheel rotates counter-clockwise continuously, for example, at 900 revolutions per minute, and a hammer l2 strikes the individual character pads 22 for printing on a work sheet 14 carried on a "platen" l6.

A photoelectric assembly 18 includes two

photoelectric cells

24 and 26, which are also shown in FIG. 2, and includes also cooperating

light sources

25 and 27, as shown for cell 26 in FIG. 3, to provide a narrow beam of light through which the character pads pass successively. Thus, the pads and the spaces between them provide dark and light elements to which the photoelectric cells respond. One character pad 64 is radially shorter than the others. The photoelectric cell 24 and its cooperating light source 25 are set radially inward so as to respond to all 64 of the character pads of the wheel. Photoelectric cell 26 and its cooperating light source 27, FIG. 3, are set radially outward so that its light beam is not intercepted by the short character pads 64, but it intercepted by the other 63 character pads. Because of space limitations, the two

cells

24 and 26 cannot respond simultaneously to the same character pad and so are spaced circumferentially by the distance of an integral number of character pads, here shown as two pads.

As shown in the diagram of FIG. 4, in a known manner a coder 30 receives an input signal identifying a character to be printed and transmits a number representing the address of that character to a coincidence detecter 32. A continuously running, address counter 34, driven by pulses from the photocell 24, presents, in succession, the numerical addresses of the characters on the print wheel, and when an address so presented corresponds to the address of the character to be printed, a signal is transmitted to the print control 36 which actuates the hammer 12 (FIG. 1) for printing the desired character.

The present invention provides the necessary synchronism of the counter 34 with the rotation of the wheel 10. The signal pulses from the photoelectric cell 24 are paired by the pulses from the photoelectric cell 26, except at the passage of the short character pad 64. This failure to pair the pulse from the cell 24 identifies the specific instantaneous position of the wheel 10 and is utilized for setting the address counter 34 to a particular numerical address, such as 64."

Certain waveforms appearing in the system are shown in FIG. 5. There, the curves 40 and 42 depict the output of

photoelectric cells

24 and 26. The other curves depict voltages in the circuits of FIG. 4. For convenience, the values of these curves will be described in relative terms. The high values will be called positive, that is, positive relation to the others, and the low values negative, negative to the others. A flip-flop is in reset" condition when the output of its lower half, as shown in the diagram, is positive and the upper half negative." It is set when the upper is positive and the lower negative.

Conveniently in FIG. 4, the counter 34 counts consecutively from l to 64. Each number constitutes the identification or address of one of the character pads 22 and, conveniently, the short pad 64 has the address 64. In FIG. 5 the curve 42 is labeled with the

numbers

62, 63, 64 and 1 to indicate the addresses of the particular pads passing the photoelectric cell 26. As shown by this curve, the cell 26 generates a dark value, or dark pulse, at each pad except the pad 64. The signal represented by the curve 40 from the photocell 24 is similar to the signal 42, and in phase therewith, except that it has dark pulses at all character pad positions. Because the

photocells

24 and 26 are spaced two character pads apart, the dark pulses produced, for example, by the pad 62 in photocell 26, shown by curve 42, is accompanied, or paired, by a dark pulse from a different pad in the photocell 24, but these signals will be described here with respect to the pad numbers marked on the curve 42. As indicated in FIG. 5, the period of the periodic signal C is approximately 1,000 microseconds when the print wheel runs at 900 rpm.

The signal C from the photocell 24, shown by the curve 40 in FIG. 5, is applied to a level-responsive NAND gate 44, FIG. 4, operating as an inverter, to produce a signal B which drives the address counter 34. As is shown in FIG. 5, the changes in the value of the B signal in curve 46 occur near the mid-level of the signal C in curve 40. This 8 signal is applied to a resistor-condenser delay circuit 45, FIG. 4, and a NAND 48 operatin g as an inverter, to provide a short sampling signal Gs. As shown by the curve 50 of FIG. 5, these short Gs pulses occur near the mid-level position of the dark-going part of the curve 40, that is, at the leading edge of the dark pulse.

The C and H signals from the

photocells

24 and 26, FIG. 4, are applied to flip-flops Fe and Fh, respectively, for complementing them. These flip-flops change state near the rnid level of the photoelectric signals on the light-going, or negative-going, slope of the curves 40 and 42, FIG. 5, that is, at the trailing edge of the dark pulse.

The outputs of the flip-flops Fe and Fit, FIG. 4, are applied to two

NAND gates

56 and 57 operating as an exclusive-OR circuit enabled by the sampling pulses Gs from the gate 48. The output of the NANDs S6 and 57, and also the sampling signal Gs, are applied to two

NAND gates

58 and 59, connected as a flip-flop. The output Sn of the gate 58 constitutes a synchronizing signal which is applied to the counter 34 for resetting it to the count, or address, 64" and is applied also to flip-flops Fe and Pb for resetting them.

During normal operation, the particular Gs sampling pulse 47, FIG. 5, that occurs at the leading, or darkgoing edge of character pad No. l, puts the two flipflops Fe and Fit in the same, reset, state. Then, as successive character pads pass the two photocells, for generating paired pulses, the flip-flops will be complemented together and will remain in phase, going to the reset" condition at the trailing, or light-going edges of even numbered pads and to the set" condition at the trailing edges of odd numbered pads.

Thus, as shown by the

curves

53 and 55 in FIG. 5, both of these two flip-flops Fe and Fh go to reset (low value of curves S3 and 55) at time t indicated by line 49, at the trailing edge of pad 62, and both go to set" at time indicated byline 51, at the trailing edge of pad 63. At time 1,, indicated by the vertical line 60, flip-flop Fc changes to "reset as the signal represented by the curve 40 goes through its mid-value in the lightgoing swing. Since the short pad 64, FIG. 3, does not intercept the light to the photoelectric cell 26, the curve 42, FIG. 5, does not have a light-going swing at this time 1,, and consequently the flip-flop Fh does not change its state, but remains set" as shown at 65 on the curve 55.

Then, during the time interval 1, to 1 indicated in FIG. 5, the sampling signal Gs enables the

gates

56, 57 which, because flip-flops Fe and Pb are in opposite states, delivers a negative pulse Gu which, with the sampling pulse Gs, activates the flip-flop $8, 59 for delivering a negative synchronizing pulse Sn. The actions in this interval 1, to 1,, are detailed in FIG. 6.

The horizontal scale in the graph of FIG. 6 is not intended as an accurate time scale, but is arranged only to show the order in which the events take place. The curve 67 represents the sampling signal Gs which has a high, or "positive" value for approximately 10 microseconds. It rises at the time 1, and falls at the time t At time 1 with Fh set and Fe reset, positive voltages are applied by both flip-flops to the NAN D 56, FIG. 4. These voltages, plus the positive sampling signal Gs, cause the gate 56 to deliver the negative-going excursion of the signal Gu, at time 1, shown at 68 in FIG. 6, to the NAND 59. Normally, this Gu, and also the synchronizing signal, applied to this NAND 59, are both positive so that the output Gv of NAND 59 is negative. The NAND 59 puts out such a negative signal only while both inputs are positive. Accordingly, the negative-going swing 68 of the Ga signal, FIG. 6, causes Gv to swing positive, as shown at 70, at time 1,. Then, with Gv and Gs both positive, they drive the output Sn of NAND 58, which constitutes the synchronizing signal, negative at time 1, as shown at 72 in FIG. 6. The negative value of this synchronizing signal Sn, applied to the flip-flop Fh, resets it at time 1-,, as indicated at 74 in both FIGS. 5 and 6. This negative level of the synchronizing signal is applied also to the reset connection of flip-flop Fe, but since Fe is already in the "reset" condition, it does not change, so that, as shown in FIG. 5, the two flip-flops Fe and Fh are now in the same state, that is, both of them are reset. The negative value of the synchronizing signal Sn also sets the counter 34 to the address 64," as previously described. This negative value of Sn is also applied to the NAND 59, but since the signal Gu is already negative, this negative value of Sn merely reinforces the other, and the output Gv of NAND 59 remains positive.

The resetting of Fh at time 1, returns the two flipflops Fe and F h to a like condition so that the output of the exclusive-

OR gate

56, 57 returns to a positive value at time 1 as indicated at 76 in FIG. 6 Because the synchronizing signal applied to NAND 59 is still negative, no change occurs in the output Gv and it remains at the positive value. This positive signal Gv, together with the positive signal Gs, holds the NAND gate 58 active so that its output Sn remains negative.

This condition continues until the sampling signal Gs returns to its normal, inactive level (shown at 50 in FIG. 5), and also as indicated at 78 in FIG. 6, at time 1,. Thereupon, the output Sn of gate 58, which constitutes the synchronizing signal, goes positive at time 1 as indicated at 80in FIG. 6. Then, because both Sn and Gu are positive, Gv goes negative at time t as indicated at 82 in FIG. 6. Thus, at the time 1 the

gates

56, 57, 58 and 59 and the signals Gs, Gu, Gv and the synchronizing signal Sn have all returned to the conditions existing at time 1,. However, the two flip-flops Fh and Fe are again in step. At the next light-going swing of the photoelectric signals, at time t at the trailing edge of the No. 1 character pad, they both flip to the set condition, as previously described. The sampling signal Gs is applied to the

gates

56, 57 and 58 at each pulse of signal C from photocell 24, but only when the flip-flops F c and Fh are in opposite states is a negative Gu signal generated for producing a synchronizing signal.

It is to be noted that since the two flip-flops Fe and Fh are controlled independently by their respective photocells responding to separate, flexibly mounted, character pads, they may not, and generally will not, flip at precisely the same time. However, precision is not required. It is permissible, for example, that the Gs pulse 90, FIG. 5 on the dark-going swing of the pulse from cell 24, fall anywhere between the two successive flips of Fh at times t and 2,, indicated by

lines

49 and 51 in FIG. 5, on the light-going swings of the pulses from cell 26. The tolerance of the system for nonuniformity and vibration is further enhanced by giving the Gs pulse a short duration, specifically about 1 percent of the time between t and t The tolerance is a full character interval, and it exceeds the tolerance permissible in the timing of the stroke of hammer 12, FIG. 1.

Although, in the normal operations just described, the NAND 57 never passes any signal, this unit is needed during start-up. It is necessary that the operation of the flip-flops Fc and F b be synchronized with the rotation of the print wheel so that the negative,

synchronizing pulse Sn from gate 58 is supplied to the counter 34 when the short character pad 64 is at the photoelectric cell 26. if the NAND gate 58 were omitted, the system could develop a synchronizing pulse only if Fc was reset and Pb was set at that time. Then, when the system started up, if the two flip-flops Fe and Fh were initially out of step, enabling signals would be supplied to the NAND gate 56 at the passage of either the even or odd numbered pads, but not both. The first such signal passed to NAND 56 would reset Fh to bring the two flip-flops Fe and PI: into step. When so brought into step with each other, or if started up in step, the two flip-flops might also be in step with the print wheel so that they would go to their set condition at the trailing edges of odd numbered pads, as is required for normal operation and, if so, the system could then operate using only the NAND 56 and not require the NAND 58. However, the two flip-flops Fe and F h might be in step with each other, but out of step with the print wheel so they would go to their set conditions at the trailing edges of even numbered pads and, in that case, the NAND 56 could not receive enabling signals at the passage of the short character pad 64 but, rather, would receive them one pad later. This action would put the address counter 34 out of step with the print wheel. Although it would return the two flip-flops to an in-step condition, it would again make them go to the set condition at the passage of the even numbered pads, so that, again, the synchronizing signal would be developed one pad late, and the system would persist in developing the synchronizing signal at the wrong time.

it will be recognized that, taken together, the two flip-flops Fe and F h have four possible states, namely i FhFc, when both are set;" (2) FcFh, when both are reset;" and (3, 4) FhFc and FhFc when one is set and the other reset. The system responds to FcFh, as at pad 64 in normal operation (time to t in FIG. 6) to change F11, and may respond to FcFh during start-up to change Fe. The exclusive-

OR gate

56, 57 responds to either the FcFh or the FcFh state to generate the synchronizing signal that changes one flip-flop to bring the state of the two flip-flops to FcFh in which state the

gate

56, 57 is blocked from generating that signal.

The signal D for driving the counter 34 may not be needed at the position of pad 64, either because the counter is always brought to address 64" by the synchronizing signal,

or because the pad 64 will not be used for printing. In such case, the counter can be driven from either of the

photocells

24 and 26.

In the specific structure here disclosed, the Gs pulse can be omitted at the 64 position. Accordingly, the G: signal also can be generated from either of the two photoelectric cells.

FIG. 7 shows a modified structure in which all 64 character pads of a print wheel 10 are full length, but pads 64 and 1' are connected by a bridge 86 that closes the inner half of the light space between them. An outer photocell 24' receives a light pulse at each inter-pad space, and the inner cell 26' sees and responds to only 63 light spaces. Thus, while in the print wheel 10 of FIGS. 1 and 2 the unpaired pulse is a dark pulse, in the wheel 10' of FIG. 7 it is a light pulse.

FIG. 8 shows the outputs of the photocells 24 and 26' of FIG. 7 and also the states of flip-flops Fe and F11 (similar to Fe and Fit) complemented thereby. These differ from the corresponding curves of FIG. 5 only in the omission of alight pulse at 88, instead of the omission of a dark pulse. In all other respects, the two constructions operate similarly.

The system of the present invention operates reliably at all speeds of the print wheel from near zero speed to far above the intended operating speed and so operates during start-up, and furthermore, puts the address counter 34 into synchronism with the print wheel at the first passage of the omitted pulse element (the short character pad 64 in FIG. 2 or the bridge 86 in FIG. 7). Thus, only during start-up will the address counter 34 normally remain out of synchronism with the print wheel, and then for not more than one turn of the wheel.

It will be apparent that the invention is capable of modifications and variations within the scope of the claims.

lclaim:

l. A counter synchronizer for resetting an associated counter to an initial state comprising:

pulse train generating means coupled to said flipflops, said means including first means for generating a first train of pulses for complementing a first one of said flip-flops and second means for generating an interrupted train of pulses each paired with the pulses of said first train for complementing the second one of said flip-flops, at least one of said first train pulses being unpaired;

means coupled to said pulse train generating means for generating a sampling signal;

means coupled to said flip-flops for generating a FLIP-FLOPS UNPHASED signal whenever said flip-flops are in opposite states during the occurrence of said sampling signal; and

means coupled to said lastnamed means and responsive to the appearance of said FLlP-FLOPS UNPHASED signal for generating a reset signal for resetting said first and second flip-flops and said counter.

2. The apparatus of claim 1 wherein said pulse train generating means comprises:

a source of radiation;

a rotating member having a plurality of circumferentially spaced radiation modulating elements; and

first and second photoelectric cells positioned adjacent the path of travel of said light modulating elements at first and second radial distances from the center of rotation of said member for receiving modulated radiation from said source,

one of said modulating elements being provided with partial modulation means for modulating the radiation incident on only one of said cells.

3. The apparatus of claim 2 wherein each of said radiation modulation elements comprises an opaque pad, and said one of said modulation elements has a shorter length than the remaining ones of said elements.

4. The apparatus of claim 2 wherein each of said radiation modulating elements comprises an opaque pad, and said partial modulation means comprises an opaque interstitial web having a shorter length than said pads.

5. The apparatus of claim 2 wherein said rotating member comprises a print wheel having a plurality of radial spokes and each of said radiation modulating elements comprises a character pad mounted on one of 8 said spokes.

6. The apparatus of claim 1 further including means coupled to said pulse train generating means for generating a COUNTER INCREMENT signal for incrementing said counter.

7. The apparatus of claim 1 wherein said FLIP- FLOPS UNPHASED signal generating means comprises an inverting AND-gate, the inputs of which are coupled to one preselected output from each of said flip-flops and to said sampling signal generator.

8. The apparatus of claim 1 wherein said FLIP- FLOPS UNPHASED signal generating means comprises a pair of inverting AND-gates, the input of each AND-gate being coupled to a different preselected output from each of said flip-flops and to said sampling signal generator.

9. The apparatus of claim 1 wherein said reset signal generating means comprises a first inverting ANDgate having first and second inputs, said first input being coupled to said FLIP-FLOPS UNPHASED signal generating means, a second inverting AND-gate having third and fourth inputs, said third input being coupled to said sampling signal generator, said fourth input being coupled to the output of said first inverting AND- gate, the output of said second inverting AND-gate being coupled to said second input, said counter and said flip-flops.

* i it

Claims

1. A counter synchronizer for resetting an associated counter to an initial state comprising: a pair of flip-flops; pulse train generating means coupled to said flip-flops, said means including first means for generating a first train of pulses for complementing a first one of said flip-flops and second means for generating an interrupted train of pulses each paired with the pulses of said first train for complementing the second one of said flip-flops, at least one of said first train pulses being unpaired; means coupled to said pulse train generating means for generating a sampling signal; means coupled to said flip-flops for generating a FLIP-FLOPS UNPHASED signal whenever said flip-flops are in opposite states during the occurrence of said sampling signal; and means coupled to said last-named means and responsive to the appearance of said FLIP-FLOPS UNPHASED signal for generating a reset signal for resetting said first and second flip-flops and said counter.

2. The apparatus of claim 1 wherein said pulse train generating means comprises: a source of radiation; a rotating member having a plurality of circumferentially spaced radiation modulating elements; and first and second photoelectric cells positioned adjacent the path of travel of said light modulating elements at first and second radial distances from the center of rotation of said member for receiving modulated radiation from said source, one of said modulating elements being provided with partial modulation means for modulating the radiation incident on only one of said cells.

5. The apparatus of claim 2 wherein said rotating member comprises a print wheel having a plurality of radial spokes and each of said radiation modulating elements comprises a character pad mounted on one of said spokes.

7. The apparatus of claim 1 wherein said FLIP-FLOPS UNPHASED signal generating means comprises an inverting AND-gate, the inputs of which are coupled to one preselected output from each of said flip-flops and to said sampling signal generator.

8. The apparatus of claim 1 wherein said FLIP-FLOPS UNPHASED signal generating means comprises a pair of inverting AND-gates, the input of each AND-gate being coupled to a different preselected output from each of said flip-flops and to said sampling signal generator.

9. The apparatus of claim 1 wherein said reset signal generating means comprises a first inverting AND-gate having first and second inputs, said first input being coupled to said FLIP-FLOPS UNPHASED signal generating means, a second inverting AND-gate having third and fourth inputs, said third input being coupled to said sampling signal generator, said fourth input being coupled to the output of said first inverting AND-gate, the output of said second inverting AND-gate being coupled to said second input, said counter and said flip-flops.