US3699584A - Insertion phase correction of phase shifters by presetting binary counters - Google Patents

Abstract

This invention relates to a method of inserting into a phase shifter the necessary amount of insertion phase shift to correct for departure of phase shift from an acceptable value for that phase shifter resulting from normal inadequate production tolerances. The method involves using in the logic-driver circuit for the phase shifter a counter whose digital output determines the magnitude of the phase shift command applied to the phase shifter. The input to the counter is preset in accordance with the amount of phase shift correction determined from the phase shift measuring test to be necessary to correct for the undesired phase deviation in the manufacturing process.

Description

United States Patent Hrivnak et al.

1 51 Oct. 17,1972

[54] INSERTION PHASE CORRECTION OF 3,316,506 4/1967 Whicker et al. ..333/24.1 PHASE SHIFTERS BY PRESETTING 3,582,953 6/1971 Manner ..333/24.l X BINARY COUNTERS OTHER PUBLICATIONS 72 I 1 mentors 3322 13 gggg ti g g r J or Klng et al., Precise Control of Ferrlte Phase Shifters, P IRE Trans. on MTT, April 1959 [73] Assignee: The United States of America as represented by the Secretary of the Primary Examiner-Paul L. Gensler Army Attorney-Harry M. Saragovitz, Edward J. Kelly, Her- [22] Filed. Dec 30 1970 bert Berl and Daniel D. Sharp [21] Appl. No.2 102,748 [57] ABSTRACT This invention relates to a method of inserting into a [52 us. c1. ..343/854, 324/84, 328/155, phase shifter the necessary amount of insertion phase 333/24 1 shift to correct for departure of phase shift from an [511 1111.01. ..I-I0lq 3/26,I-I01p 1/32 acceptable value for that Phase shifter resulting from [58] Field of Search ..333/17, 24.1, 31, 31 A; normal inadequate Production teleranees- The method 324/33 D, 84, 83 328/155; 343/778, 854 involves using in the logic-driver circuit for the phase shifter a counter whose digital output determines the [56] References Cited magnitude of the phase shift command applied to the phase shifter. The input to the counter is preset in ac- UNITED STATES PATENTS cordance with the amount of phase shift correction determined from the phase shift measuring test to be 53 32; necessary to correct for the undesired phase deviation s s I s u u t t I s s I u a s n t f t 3,482,244 12/1969 Gadenne ..343/854 m he ac process 3,274,521 9/1966 Nourse ..333/24.l 6 Claims, 2 Drawing Figures PHASE SHIFTER PAIENIEDMI n mm FIG. 1

l sA mass smrren COUNTER JR???" 4 M K CLOCK PRESET-- PULSE RF SIGNAL CLOCK-4 FRESH counren PULSE PHASE SHIFTER @PRESET DATA LINES PRESET PULSE am m s a WWW M W m RJ. 1 m V am .v mm 0 w 4 INSERTION PHASE CORRECTION OF PHASE SHIFTERS BY PRESETTING BINARY COUNTERS BACKGROUND OF THE INVENTION from a common signal source, with each radiating element being connected to a separate phase shifter which determines individually the phase delay of the signal for that element. By individually driving the phase shifters so as to achieve the proper relative phase shift at the various elements, the contributions from these elements can be added vectorially in such a manner as to steer the antenna beam electronically. One of the severe problems in construction of a phased array antenna is that of unit-to-unit variation in the insertion phase shift of the phase shifters, that is, the amount of phase shift inherently present in a phase shifter when no differential phase shift command is present. The problem of inadequate production tolerances in the phase shifter is magnified because of the large number of antenna elements; often more than several hundred such elements are required. These production tolerances in phase shift often exceed the limit necessary for accurately steering the beam or shaping the radiation pattern of the antenna array. Consequently, some method of correcting for such unit-to-unit variations of insertion phase shift is required.

A commonly used method of correcting for differences in insertion phase shift consists of placing a dielectric shim of appropriate dimensions in the waveguide to change the propagation time of the RF energy through the waveguide by an amount sufficient to bring the insertion phase within the desired tolerance. This method often takes considerable time in a production run of several hundred or thousand phase shifters because each phase shifter must be first placed in an RF test fixture to measure the insertion phase and, after removal from the test fixture the appropriate dielectric shim must be securely mounted within the waveguide, and, finally, the phase shifter must be placed back in the test fixture for verification of the correct value of insertion phase. If the insertion phase is still improper, further shimming is required, together with subsequent verification of correct value.

One type of logic-driver circuit often used for each phase shifter of the antenna array employs a binary counter. With this type of logic-driver circuit for the phase shifters, the desired phase command is represented by a specified number of pulses applied to the clock input of the first stage of the binary counter which advances the counter to represent the desired phase shift state. Previously, the counter has been set normally to the ZERO state before each new differential phase shift command is entered at the clock input. This ZERO state then is used as the insertion phase reference state. An appropriate dielectric shim is glued into the waveguide to correct the insertion phase shift to within the desired tolerance, in accordance with the procedure already outlined.

SUMMARY OF THE INVENTION A novel method of correcting the insertion phase involves the use of a presettable binary counter. By the addition of preset lines to the counter, the latter may be preset, rather than cleared or set to the ZERO state, when a preset pulse is received. The preset value is chosen to represent the necessary amount of phase shift to correct the value of insertion phase to within the tolerance required. This preset value then becomes the corrected insertion phase shift for that phase shifter. The differential phase command merely advances the counter an additional specified number of steps to obtain the desired differential phase shift. Application of this novel concept to a production run of phase shifters can result in considerable cost reduction. After determining the actual phase shift inherent in the phase shifter by means of the RF test jig, presetting of the counter by an amount necessary to correct for the deviation of the insertion phase shift from a desired reference value can be accomplished simply by permanently wiring into each of the preset data lines of the binary counter the binary representation of the desired insertion phase correction, which is inserted into the counter upon receipt of a preset pulse (command). Since the microwave assembly of the phase shifter is not disturbed, selection of the preset value will be a one-time operation, and expensive and often tedious repeated gluing of a dielectric shim and multiple retesting of the phase shifter and alteration of the shim is eliminated.

DESCRIPTION OF THE DRAWING FIG. 1 is a simplified functional block diagram of a typical application for which the method of the invention is well suited; and

FIG. 2 is a diagram showing the application of the system diagrammed in FIG. 1 to a ferrite phase shifter.

DETAILED DESCRIPTION OF THE PREFERRED- EMBODIMENT An arrangement of phase shifters is shown in FIG. 1 for a typical application, namely, a phased array radar system. The RF signal is applied to each of many phase shifters 10A to 10N and the phase-shifted output from each of said phase shifters is coupled to respective antennas 12A to 12N. The direction of propagation of the transmitted signal is indicated in FIGS. 1 and 2 by a solid line and the direction for the received signal is indicated by a dashed line. A binary counter 15A to 15N is associated with each of the respective phase shifters 10A to ION. The counters of FIG. I are illustrated, by way of example, as four-bit counters; the invention, however is not limited to counters having this number of bits. The number of counter stages is dependent upon the precision of adjustment required and, for a given maximum overall phase shift, the greater the number of counter stages the smaller will be the amount of phase shift represented by each count thereof. Each counter 15 has a preset pulse (command) line, a clock input, and the preset data lines 28, as will be described in greater detail subsequently.

A typical phase shifter 10 is shown in FIG. 2 and is shown, by way of example, as a four-bit ferrite phase shifter which includes four separate rectangular ferrite toroids 20a, 20b, 20c and 20d spaced apart by inter-bit spacers 22a, 22b and 22c. The toroids can be provided at each end with matching transformers, if necessary, one of which, viz., transformer 24, is partially visible in FIG. 2. Magnetizing wires 25a, 25b, 25c and 25d pass through an elongated dielectric 23 to provide necessary energization of the respective toroids 20a to 20d. These wires 25 pass axially through the dielectric member 23 and one end of each magnetizing wire 25 is connected to a reference potential, such as ground. The other ends of the magnetizing wires 25a, 25b, 25c and 25d are connected to the output lines of respective counter stages 15a, 15b, 15c and 15d, usually through driver amplifier circuits 30. As shown in FIG. 2 the length of the toroid 20b is twice as long as that of toroid 20a, and thus provides twice as great a phase shift, since it is associated with the next larger significant bit of counter 15. Similarly, the toroid 20c provides twice as much phase shift as toroid 20b and toroid 20d twice as much phase shift as toroid 20c. In this manner, one obtains a digital phase shifter with the phase shift dependent upon the output of the four stages of binary counter 15. The counter 15 of FIG. 2 includes preset data input lines 28a to 28d, one for each of the respective four counter stages 15a to 15d. Each of these input lines can be connected either to a binary ONE or to a binary ZERO input. This alternative connection is shown schematically in FIG. 2 by moveable switch arms; however, in practice, these connections are wired in permanently.

The phase shift introduced by each of the phase shifters A to 10N of FIG. 1 must be determined by any one of several well known methods of measuring phase shift. For example, an input signal can be supplied to the shunt arm of a magic tee with the energy in one of the side arms thereof being supplied to a calibrated phase shifter and the energy in the other side arm of the magic tee being supplied to the phase shifter under test. The outputs of both the calibrated phase shifter and the test phase shifter then is coupled, as by means of another magic tee, to a detector. The calibrated phase shifter is adjusted to provide maximum detector output, first prior to activation of the phase shifter undergoing test and then after such activation. The difference in two readings of the calibrated phase shifter for these two conditions provides a measure of the phase shift introduced by the phase shifter undergoing test.

In a phased array radar application, for example, the effective insertion phase shift of every phase shifter in the phased array should be made as uniform as possible. As previously explained, this cannot be achieved readily in production and the various phase shifters exhibit different values of insertion phase shift. will be assumed arbitrarily, for purposes of explanation only, that the insertion phase shift is to be 220. By insertion phase shift is meant the phase shift which the phase shifter should have at the time the differential phase shift command is applied. If it be assumed further that a given phase shifter 10A provides actually only 150 of insertion phase shift, an additional 70 phase shift obviously is required to achieve this effective insertion phase shift of 220. For a system using a four-bit binary approximation of differential phase shift, one could use a four-bit counter, with a total count of 16, and since one cycle of counter operation represents 360 phase shift, it is evident that each count represents an increment of 22 V2" phase shift which results in a tolerance of plus or minus 11 A". If greater accuracy had been required, one could have used a five-bit counter (32 counts) and then a tolerance of 5 96 would be obtained. In the example given, presetting will be the closest approximation to which, for a four-bit approximation, is 67.5, will be the wired-in present data for the counter. In other words, preset data lines 28a and 28b will be prewired to a ONE input and preset data lines 280 and 28d will be prewired to a ZERO" input; that is the binary number 001 l (least significant bit to the right) is wired into this binary counter 10A. This binary number 00ll represents 0 180 0 X 1 X 45 1 X 22.5 675. The same procedure, using the appropriate preset data, would be used for each of the other phase shifters 10 used in the system shown in FIG. 1. In operation, a preset pulse is applied to the preset pulse line of each counter, whereupon the wired-in preset data is transferred into the counter. In the example given, counter 15A would have an initial state of 0011 to correct the insertion phase for that phase shifter. This initial state is the state of the given counter prior to receiving the differential phase shift command at the clock input, and is the closest approximation (675) to the desired insertion phase correction of 70. This binary approximation (67.5) then is the starting condition for the given counter.

In order to provide the necessary differential phase shift for each of the phase shifters of the system of FIG. 1, an appropriate number of clock pulses can then be supplied to the corresponding counter 15 to advance the counter by that number hence, an addition of the preset number (insertion phase correction 0011) and the differential phase shift is accomplished. For example, if the phase shifter 10A is designed to provide phase shift after correction of the differential insertion phase, then 135 divided by 22 ie or six clock pulses more would be applied to the counter 15A in order to advance it by an additional six counts corresponding to the additional 135.

We wish it to be understood that we do not desire to be limited to the exact details of construction shown and described, for obvious modifications will occur to a person skilled in the art.

What is claimed is:

l. A method for initially setting a plurality of phase shifters to an identical desired reference insertion phase shift by correcting for departure of the actual inherent insertion phase shift from the desired reference insertion phase shift in each phase shifter operating in conjunction with a binary counter, each count of which acts upon said phase shifter to produce an incremental amount m of phase shift, comprising the steps of;

measuring the amount n by which the phase shift produced by each said phase shifter departs from said reference insertion phase shift; and

presetting the closest binary approximation of said amount n into each said counter to correct for each said departure in insertion phase shift.

2. A method according to claim 1 wherein said amount m is equal to the ratio of 360 to the number of counts in the counting cycle of each said counter.

3. A method according to claim 1 further comprising the steps of;

applying a number k/m of clock pulses to each said counter to advance the count obtained by presetting said counter an amount sufficient to establish a desired differential phase shift k within each said phase shifter.

4. A phased array system comprising an array of antennas, a separate phase shifter connected in circuit with each corresponding antenna, a separate multistage binary counter having output lines coupled to a corresponding phase shifter for supplying said phase shifter with a binary input data which changes the inherent insertion phase shift of said phase shifter by an increment of m degrees for each binary count of the counter, said counter having a preset pulse line for all stages of said counter and a preset data line for each stage of said counter, means for applying to said preset data lines of a given counter the closest binary representation of the phase correction necessary to correct for the deviation of the actual insertion phase shift of the corresponding phase shifter from a desired reference insertion phase shift which is identical for all phase shifters, and means for applying a preset pulse to said preset pulse line of a given counter to transfer said preset binary data to the output lines of the corresponding counter.

5. A phased array system according to claim 4 wherein each counter includes a clock pulse input, and means responsive to n/m said clock pulses for advancing the count established for the counter by said preset binary data to provide a desired differential phase shift of n degrees for said corresponding phase shifter.

6. A phased array system according to claim 4 further including separate means for driving each of said phase shifters with said binary data at the corresponding counter output lines.

Claims (6)

1. A method for initially setting a plurality of phase shifters to an identical desired reference insertion phase shift by correcting for departure of the actual inherent insertion phase shift from the desired reference insertion phase shift in each phase shifter operating in conjunction with a binary counter, each count of which acts upon said phase shifter to produce an incremental amount m of phase shift, comprising the steps of; measuring the amount n by which the phase shift produced by each said phase shifter departs from said reference insertion phase shift; and presetting the closest binary approximation of said amount n into each said counter to correct for each said departure in insertion phase shift.

2. A method according to claim 1 wherein said amount m is equal to the ratio of 360* to the number of counts in the counting cycle of each said counter.

3. A method according to claim 1 further comprising the steps of; applying a number k/m of clock pulses to each said counter to advance the count obtained by presetting said counter an amount sufficient to establish a desired differential phase shift k within each said phase shifter.

4. A phased array system comprising an array of antennas, a separate phase shifter connected in circuit with each corresponding antenna, a separate multi-stage binary counter having output lines coupled to a corresponding phase shifter for supplying said phase shifter with a binary input data which changes the inherent insertion phase shift of said phase shifter by an incrEment of m degrees for each binary count of the counter, said counter having a preset pulse line for all stages of said counter and a preset data line for each stage of said counter, means for applying to said preset data lines of a given counter the closest binary representation of the phase correction necessary to correct for the deviation of the actual insertion phase shift of the corresponding phase shifter from a desired reference insertion phase shift which is identical for all phase shifters, and means for applying a preset pulse to said preset pulse line of a given counter to transfer said preset binary data to the output lines of the corresponding counter.

5. A phased array system according to claim 4 wherein each counter includes a clock pulse input, and means responsive to n/m clock pulses for advancing the count established for the counter by said preset binary data to provide a desired differential phase shift of n degrees for said corresponding phase shifter.

6. A phased array system according to claim 4 further including separate means for driving each of said phase shifters with said binary data at the corresponding counter output lines.

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