US3689895A - Micro-program control system - Google Patents
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- US3689895A US3689895A US91810A US3689895DA US3689895A US 3689895 A US3689895 A US 3689895A US 91810 A US91810 A US 91810A US 3689895D A US3689895D A US 3689895DA US 3689895 A US3689895 A US 3689895A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
Definitions
- a micro-program control system for computing apparatus provides a time shared concurrent utilization [30] Foreign Appumuon Priority Data of a fixed, or semi-fixed memory containing a plurality Nov. 24, 1969 Japan .A4/94068 of -p Micro'instl'ultions of each microprogram are read out in repetitive, sequential manner 52] us. Cl ..34o/172.5, 444/1 from the memory and entered into control registers [51] Int.
- a micro-program control system refers to a class of systems wherein control of arithmetic, logic, or other operations performed by an information processing system is implemented by micro-programs, each comprising difierent sequences of basic micro-operations. That is, micro-instructions are stored in a fixed or semifixed memory for subsequent read out and execution in accordance with the respective microprograms.
- Such a control system has a number of advantages, e.g., it is simple in arrangement and fabrication, and is readily susceptible to change in design.
- a micro-program control system suffers the following drawbacks:
- conditional jump of a microprogram requires a relatively prolonged period of time for complete execution.
- micro-program control systems exhibit low control efficiency, i.e., they slow down a computing process below the cycle time capability of the fixed or semi-fixed memory. High speed memory operation,attainable with recent semiconductor integrated circuit development and associated technologies, cannot therefore be efficiently utilized.
- micro-program memory An appreciable storage capacity is required for a typical memory which stores micro-programs. Should an increased demand be placed upon the performance of such micro-programs, as to perform complex operations by utilizing a micro-program requiring a great number of micro-instructions, even greater fixed or semi-fixed memory capacity would be necessary. The micro-program memory would then become a major contributor to the total cost of a computing system, and this may not be economically realistic.
- a single fixed or semi-fixed memory stores a number of micro-programs which are selectively executed on a time division basis.
- read-out of the memory is successively efiected for each of the plural microprograms, at constant repetitive intervals, with the micro-instructions so read-out being executed individually.
- a sequence control circuit is provided to determine the next address to be interrogated in each micro-program from the result of the execution of prior micro-instructions.
- the sequence control circuit decides whether a jump or a sequential operation is to be performed next in a particular micro-program and, accordingly provides the address of the next micro-instruction to be read out. This next address is entered into the system to access the next stored micro-instruction in that particular micro-program at an appropriate time interval.
- a single micro-program memory is shared for the concurrent execution of a plurality of stored micro-programs on a time division basis.
- FIG. I is a schematic diagram illustrating a prior art micro-program control system
- FIG. 2 is a schematic diagram of the micro-program control system according to one embodiment of the present invention.
- FIG. 3 is a block diagram showing an example of an arithmetic unit used in the system of FIG. 2,
- FIG. 4 is a detailed wiring diagram showing an example of a sequence control unit used in the system of FIG. 2, and
- FIG. 5 is a timing chart illustrating the operation of the micro-program control system of the invention.
- like reference numerical designations in different figures identify like structural elements.
- the system includes a fixed or semi-fixed memory 1 which stores micro-programs.
- a selected micro-instruction, stored at an address specified by an address register 2 is read from the memory 1 into a read-out or output register 3.
- the micro-instruction in the register 3 is transferred to an arithmetic unit 4 for execution, that is, to perform an arithmetic operation.
- the address information in the address register 2 is then supplied to an add-one" circuit 5 to augment the original address by one.
- the updated address is then supplied to the address register 2 through an AND-gate 6 and an OR-gate 7.
- the information stored in the memory 1 at the original address plus one is read out. In this manner, micro-instructions located in the memory I at immediately following addresses can be sequentially accessed.
- an AND-gate 9 having a first input 8 and a second input 10.
- the first input 8 may be connected with the arithmetic unit 4 to receive a signal indicating whether the result of the arithmetic operation performed is positive, negative or zero.
- it may be connected with a particular register (not shown) associated with the system for detecting the state of a particular bit therein.
- the second input 10 is connected to the read-out register 3 to detect the presence of jump or "transfer" bit in this register.
- the AND-gate 9 produces a binary one output which is directly supplied to one input of an AND-gate l1 and to the other input of an AND-gate 6 after inversion. It will be seen that if the transfer condition is not met, the AND-gate 6 is opened to allow the passage of the output of the add-one circuit 5 to the OR-gate 7. Conversely, when the transfer condition is satisfied, the address stored in the output register 3 at that point in micro-program processing is fed through a terminal 12 to an AND-gate 13, or the instruction code of the instruction read out from a main memory to be executed and the content of the address register 2 in which the most significant bits are set to zero are supplied through a terminal 14 to AND-gate 15.
- This instruction code represents the address of a specified micro-program to be read out next.
- a particular bit in the readout register 3 is directly supplied via a terminal 16 to the second input of the AND-gate and, after inversion, to the second input of AND-gate 13.
- An output from the selected AND-gate 15 or 13 is thus supplied to OR-gate 17 through AND-gate 11 which is opened when the transfer condition is met. Accordingly, the transfer address data is supplied to the address register 2.
- micro-program control system The effectiveness of a micro-program control system is predicated upon its ability to perform the conditional transfer function as well as to executing a program through successive read-out of sequential addresses.
- the address for the next micro-instruction to be read out remains undetermined until the result of an arithmetic operation is available, as mentioned above.
- a relatively prolonged period of time is therefore required until the address for the next micro-instruction is decided as a result of the execution of the preceding micro-instruction.
- execution of a micro-program sequence disadvantageously proceeds in a relatively slow manner, even when a micro-program memory capable of high speed operation is used.
- a switching gate 18 is connected to the output of the memory 1, and a timing pulse signal from a pulse generator 191 is supplied to a ternary ring counter 19 so that successive cyclic gate signals may be obtained from three output terminals 19a, 19b and 19c of the counter to distribute information read out from the memory 1 to the arithmetic units 4a, 4b and 4c in a repeated sequence.
- a sequence control unit 20 is operable to decide the next addresses to be accessed for the respective micro-programs, which addresses may be supplied through the address register 2 to the memory I in synchronism with the switching operation of the switching gate 18 so as to correspond with the first, second and third micro-programs, respectively.
- Each of the arithmetic units 40, 4b and 4c is not novel per se, but may be of any conventional arrangement. In the example shown, the three units are assumed to be of an identical construction, one of these units being shown in detail in FlG. 3.
- information from two information buses 21 and 22 is supplied to an arithmetic circuit 24 in which basic logical operations such as addition, subtraction, multiplication, shift or the like are performed, and the computational result is supplied by the circuit 24 to a bus 23.
- a general purpose register 25 is provided and includes plural (for example, 16 individual registers, which are separately specified by register specifying circuits 26, 2'7 and 28. Read-out and write-in operations are performed between the register specified by the specifying circuit 26 and the bus 21 through gates 29 and 30, respectively. Similarly, read-out and writein operations are performed between the register specified by the specifying circuit 27 and the bus 22 through gates 31 and 32, respectively, and information on the bus 23 is written into the register specified by the specifying circuit 28 through a gate 33.
- a main memory is provided to store ordinary (MACRO) instructions and data.
- One such instruction stored in the main memory 34 is executed by performing a micro-program comprising a plurality of micro-instructions.
- MACRO ordinary
- One such instruction stored in the main memory 34 is executed by performing a micro-program comprising a plurality of micro-instructions.
- both gates 35 and 36 are open, information on the buses 21 and 22 is stored in an address register 37 and in a write-in or input register 38, respectively, for subsequently writing the content of the register 38 into the main memory 34 at the address specified by the address register.
- both gates 35 and 39 are open, information at the address specified by the address register 37 are read through the gate 39 onto the bus 22.
- control over the arithmetic circuit 24, specifying circuits 26, 27 and 28 and the gates 29, 30, 31, 32, 33, 35, 36 and 39 is effected by information (micro-instructions) stored in a control register 40 associated with each arithmetic unit.
- the control register 40 is supplied with these micro-instructions read out from the memory 1 via the switching gate 18.
- the bit arrangement of a micro-instruction that is, the digital content stored in the control register 40, is shown in Table 1 and comprises forty bits. The first four hits of these represent by their combination the type of arithmetic operations (operation code) to be performed by the arithmetic circuit 24.
- the designation NOP represents no operation; BAD the binary addition of information on the buses 21 and 22 and supply of the addition result to the bus 23, BSU the binary subtraction between information on the buses 21 and 22 and supply of the result to the bus 23; AND making a logical product of information on the buses 21 and 22 and supply of the result to the bus 23; HAD performing a half-add (exclusive OR) operation in information and supply of the result to the bus 23; OR making a logical sum of the information and supply of its result to the bus 23; AD], AD2 and AD4 the addition of l, 2 and 4, respectively to the information on the bus 21 and supply of the result to the bus 23; SB], S82 and 8B4 the subtraction of l, 2 and 4, respectively, from the information on the bus 25 and supply of the result to the bus 23; and SFI a ring shift, LSFT a shift to the left, and RSFT a shift to the right.
- the four bits in the portion 41A of the control register 40 which represent the type of arithmetic
- a gate controlling portion 418 of the control register 40 which comprises nine bits from the fifth to thirteenth bit, is connected to control the gates 35, 39,36, 43,29,30,3l,32 and 33 in the sequence of bit number, respectively, each bit separately controlling a different gate.
- a gate 43 is provided (FIG. 4) to determine whether the address stored in the address portion of the control register 40 or a part of the information stored in the main memory 34 is to be used for a conditional transfer.
- the bits from 14 to twenty-fifth bit, or those contained in a register specifying portion 41C of the control register 40, are used to specify a selected one of the 16 individual registers contained in the general purpose register 25.
- the first four bits in the specifying portion 41C (those numbered 14 to 17) are supplied in combination to the specifying circuit 26 to specify one of the i6 registers.
- the next four hits (numbered 18 to 21) are supplied to the specifying circuits 27 to specify another register, and the last four bits (numbered 22 to 25) are supplied to the specifying circuit 28 to specify a still different one of the i6 registers.
- the three bits numbered 26 to 28 in the control register 40 represent a test portion 41D thereof, the combination of these three hits providing a transfer condition.
- this transfer condition coincides with the result of an arithmetic operation performed in the arithmetic circuit 24, the transfer condition is satisfied and a transfer operation is effected.
- NOP never satisfies such a condition, so that no transfer is effected
- UCJ MP represents the case where the condition is always satisfied
- ALLO a transfer operation when the result of an arithmetic operation comprises bits which are all zeros.
- the symbol represents a transfer operation when the result of an arithmetic operation has a positive polarity, and the symbol a transfer operation when the result of an arithmetic operation has a negative polarity.
- OVF represents a transfer operation when there is as overflow, and carry a transfer operation when there is a carry from the number of bits allocated to one word.
- the remaining 12 bits numbered 29 to 40 of the control register 40 constitute an address portion 41E which represents the address to which the transfer is to be continued.
- the control unit 20 specifies the next address when a conditional transfer is or is not effected depending upon the transfer condition in the read-out (control register) and upon the result of arithmetic operations by a respective arithmetic units 40, 4b, or 40 controlled by stored micro-instructions.
- the sequence control unit 20 comprises three sequence control circuits 44a, 44b, and 44c, of an identical construction, arranged in a manner corresponding to the respective arithmetic units 40, 4b and 40.
- Each circuit includes a register and is operable to supply the address register 2 with either the address to which transfer is to be continued, or a sequential address.
- sequence control circuits 44a, 44b and 44c information from the common add-one circuit 5 is supplied to sequential addressing registers 46a, 46b and 46c through AND-gates 45a, 45b and 45c, respectively. These registers are connected through AND-gates 47a, 47b and 47c and ORgate 48a, 48b and 480, respectively, and through a common OR-gate 49 with the address register 2.
- the output from the address portion 41E of the respective control registers 40a, 40b and 40c associated with the arithmetic units 40, 4b and 4c, respectively, are supplied to the terminals 12a, 12b and 120, and thence through AND-gates 13a, 13b and 13c and OR- gates 17a, 17b and 17c, respectively, to AND-gates 50a, 50b and 50c, respectively.
- the instruction code portion of the information thereon is supplied to the terminals 14a, 14b and 14c, respectively, and thence through AND- gates 15a, 15b and 15c to the ORgates 17a, 17b and 17c, respectively.
- Gates 43a, 43b and 430 are con trolled by the fourth bit in the gate portion 418 of the respective control registers 40a, 40b and 40c, and the output from these gates are directly applied to the other input of the AND-gates 15a, 15b and 15c and also applied, after inversion, to the AND-gates 13a, 13b and 13c.
- an instruction code (the instruction code of an instruction stored in the main memory 340) is supplied from the bus 22a to the AND-gate 50a.
- the gate 430 is closed, the content in the address portion 41E of the control register 40a is supplied to the AND-gate 50a.
- a conditioning bit from the test portion 41D of the control register 40a is applied via a terminal a to one input of an AND-gate 9a, the other input of which receives an output from the arithmetic circuit 240 through a terminal 80.
- the output of circuit 24a represents a particular status for the result of the arithmetic operation performed, that is, the status above in connection with the test portion 41D.
- the AND-gate 9a opens and its output is supplied to one input of the AND-gate 50a so that when a timing pulse, discussed later, is furnished to its other input, the AND-gate 50a is opened, thereby allowing either the content of the address portion 41E of the control register 400 or information on the bus 22a to be supplied through the AND-gate 50a to the address register 2.
- the inverted output of the AND-gate 9a is connected to one input of the AND-gate 47a, so that when the transfer condition is not satisfied, the content of the register 46a is supplied through this ANDgate 47a to the address register 2.
- sequence control circuits 44b and 440 are similar in construction and operation to the sequence control circuit 440.
- these circuits include the AND-gates 9b and 9c which, like the AND-gate 9aare supplied with the output from the corresponding test portion and the output from the respective arithmetic circuits which represents a particular status for the result of an arithmetic operations performed thereby.
- the output of the AND-gate 9b and 9c are directly applied to the AND-gates 50b, 50c, and also applied, after inversion, to the AND-gates 47b, 47c.
- Output pulses repeatedly obtaining at a given interval from a terminal 190 of the ring counter 19 are supplied to the AND-gates 45b, 47c and 500.
- the output pulses from the counter terminal 19!) are supplied to the AND-gates 45c, 47a and 50aand output pulses from the terminal 196 are supplied to the AND-gates 45a, 47b and 50b.
- These AND-gates open only when timing pulses from the terminals 19a, 19b and 19c are supplied thereto.
- the content of the address register 2 is adapted to be supplied to the micro-program memory 1, and to the add-one circuit 5.
- the pulse generator l9z produces pulses at times 1,, t t and so forth, as shown in FIG. 5A.
- the terminal 190 of the ring counter 19 provides pulses at times t,, t, and so on, as shown in FIG. 5B, and the terminals 19b and 19c provide pulses at times l l and so on, and at times t t and so on, respectively, as shown in FIGS. 5C and 5D.
- FIG. 5B depicts a microinstruction 51a, for a first micro-program, having the bit arrangement set forth above, which is stored in the control register 40a at time t and which is read out at the time t,.
- the arithmetic circuit 14a operates in accordance with the content of this micro-instruction (such an operation being symbolic shown at 520, of FIG. 5F), and at the end of the clock period beginning at t the matter of whether or not the transfer condition (given by test register 40 portion 41D) is satisfied is determined.
- the status of the fourth gate bit in the gate portion 41B of the microinstruction 5la selectively conditions the gate 43a, thereby enabling the selected AND-gate 150 or to pass the information on the bus 22a or the address information in the address portion 41E of the micro-instruction 51a, therethrough and through the OR-gate 17a and AND-gate a to be stored in the address register 20.
- each register is arranged so that the information entered at its input side appears at its output side after a time delay of one clock period, this being effected by any conventional gating or shifting circuitry.
- a signal 54a which comprises the address 53a plus one (effected by the add-one circuit 5) is stored in the register 460 (FIG. SI).
- an address signal 53b, from the AND-gate 50b or 47b is stored in the address register 2 at the end of the clock period beginning at Also a micro-instruction 51c, of the third micro-program is read out from the memory I and stored in the control register 40c (FIG. 5K).
- the output 53a from either AND gate 50a 47a is supplied to the address register 2 FIG. 56).
- the digital word 530 is read out from the address register 2, and that information is supplemented by one in the manner discussed previously, with resulting signal being stored in the register 46c.
- the next micro-instruction 5119 of the second micro-program is read out from the memory 1 and entered into the control register 4012 (FIG. 5H).
- the output 5%,. from either AND-gate 50b or 47b is stored in the address register 2.
- the information 53a is read out from the address register 2, and after being increased by one, is stored in the register 46a as 540,. Also during this clock interval, the next micro-instruction 51c, of the third micro-program is read into the control register 40c.
- the micro-instruction 51a is read out at t, ("a um m t, (52d of FIG. F), and the results of this execution checked to determine whether the transfer condition is satisfied.
- the address 53:1 used to identify and read out the next micro-instruction 51a, of a program sequence, is supplied to the address register 2. This next instruction is read-out from the memory 1 at the next clock time t,, and so on.
- a plurality of microprograms or, in the present example, the first, second and third microprograms are controlled in a time sharing manner.
- the micro-instruction 51a of the first micro-program has been executed, the next address is stored in the address register 2.
- the micro-instruction 518 of the second micro-program is read, followed by the micro-instruction Slc of the third micro-program.
- the micro-instruction 51b of the second micro-program is executed and before the next micro-instruction 51b, is read out
- the micro-instruction 51c of the third micro-program is read out.
- the second micro-instruction 51a, of the first micro-program is read-out, and this process repeatedly continues in similar fashion.
- the memory 1 always reads-out a micro-instruction for one or another of the first, second and third micro-programs during each clock cycle, thus achieving efficient memory utilization.
- micro-program memory 1 since the multiple utilization of the micro-program memory 1 is effected in a time sharing manner, with memory operation being repeated at a predetermined definite time interval, there is no need for a complex arrangement to check and obviate interruptions in the computing process, as is required for typical prior art multiple programming configurations.
- the present system can be readily operated under the direction of a relatively simple executive control arrangement.
- the arithmetic units 40, 4b and 4e illustrated as having an identical construction, may in fact differ. These arithmetic units may be controlled by different bit arrangements in the control registers 40. Further, a single memory 34 may be used for all of the micro-programs.
- the arithmetic operations performed during execution of micro-instructions as shown at 52],, 52b,, 520,3 52 52b, are effected in successively offset period of time, so that one arithmetic circuit 24 may be shared by a plurality of micro-programs in a time division manner. ln this instance, registers such as general purpose registers 25 and control registers 40 may be separately provided for each of the micro-programs.
- timing means for cyclically controlling said ap paratus for said plural micro-programs
- first address updating means for providing a first next instruction address based on the memory address identified by the current contents of said address register
- gate means controlled by said timing means for loading said additional registers with the first next instruction addresses for said respective micro-programs
- second address updating means for selectively providing in response to a micro-instruction stored in each of said output registers, a second next instruction address based on one of the prior processed micro-instructions and the instruction obtained as a result of previous data processing, and control gating means controlled by said timing means and a logical combination of the priorprocessed micro-instruction and the result of data processing effected in accordance therewith for loading said address register with either of said first next instruction address and the selected second next instruction address.
- a micro-program control system as in claim 1 further comprising arithmetic means controlled by the contents of an associated one of said output registers, and means responsive to signals characterizing said arithmetic means for selectively signaling the incidence of a program instruction transfer condition for a selected one of the stored micro-programs, said signaling means having the output thereof connected to said control gating means.
- a micro-program control system as in claim 1 further comprising plural arithmetic means, said output registers being respectively associated with said arithmetic means, each of said output registers having a first portion thereof connected to the corresponding arithmetic means for defining the functional operation performed thereby, a second portion thereof for selectively identifying a transfer operation, and a third portion thereof containing an address in said memory, said control gating means including logic means connected to each of said arithmetic means and its associated output register for selecting between said first and second next instruction address from each micro-program.
- a combination as in claim 5 further comprising additional memory means, and means for selectively connecting the contents of said additional memory means as an input signal to said second address updating means.
- said second address updating means comprises plural next address selecting circuit means each associated with a different micro-program, each next address selecting circuit means including first and second coincidence means for selectively passing said first next instruction address or said second next instruction address respectively, one of said first and second coincidence means being opened during a selected cyclically repeating time interval by said timing means, logic means for enabling a selected one of said first or second coincidence means responsive to the presence or absence of micro-instruction transfer requirement, means for supplying a selected second next instruction address to said second coincidence means, means for supplying said first next instruction address to said first coincidence means.
- a combination as in claim 7 further comprising disjunctive logic means for connecting the outputs of said first and second coincidence means for each of said next address selecting circuit means with said address register.
- timing means comprise a pulse generator, and plural stage ring counter means having a clock input thereof connected to said pulse generator, the outputs from the several stages of said ring counters means being distributed to said control gating means.
- a micro-program control system as in claim 4 further comprising switched gate means controlled by said timing means for selectively distributing the mic roinstructions read out from said memory to said output registers associated with said arithmetic means.
- a method for effecting micro-program control of electronic computing apparatus which includes a memory, an address register, an address updating circuit, plural arithmetic circuits and timing circuitry for cyclically subdividing the control of said computing apparatus into a plurality of clock phases depending upon the number of micro-programs to be simultaneously executed on a time shared basis, comprising the steps of reading out a micro-program instruction for a first one of said micro-programs being executed during each clock phase, effecting execution during that clock phase of an instruction for a second micro-program read from the memory during a preceding clock phase, and impressing a next address for a third one of the micro-programs in said address register during that clock phase, said address representing a selection between a sequential updating of the previous address for said third micro-program and a transfer for said third micro-program, said memory thereby being interrogated to read out a new micro-instruction during each clock phase.
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JP44094068A JPS514381B1 (fr) | 1969-11-24 | 1969-11-24 |
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Cited By (39)
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US4085450A (en) * | 1976-12-29 | 1978-04-18 | Burroughs Corporation | Performance invarient execution unit for non-communicative instructions |
US4103328A (en) * | 1974-02-20 | 1978-07-25 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) | Control apparatus for controlling data flow between a control processing unit and peripheral devices |
US4110822A (en) * | 1975-03-26 | 1978-08-29 | Honeywell Information Systems, Inc. | Instruction look ahead having prefetch concurrency and pipeline features |
US4151597A (en) * | 1976-07-23 | 1979-04-24 | Thomson-Csf | Microprogrammable control unit |
US4156925A (en) * | 1976-04-30 | 1979-05-29 | International Business Machines Corporation | Overlapped and interleaved control store with address modifiers |
FR2409550A1 (fr) * | 1977-11-21 | 1979-06-15 | Burroughs Corp | Appareil d'interface de la famille des gabarits |
US4161026A (en) * | 1977-11-22 | 1979-07-10 | Honeywell Information Systems Inc. | Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes |
US4197579A (en) * | 1978-06-06 | 1980-04-08 | Xebec Systems Incorporated | Multi-processor for simultaneously executing a plurality of programs in a time-interlaced manner |
US4205372A (en) * | 1974-09-25 | 1980-05-27 | Data General Corporation | Central processing unit employing microprogrammable control for use in a data processing system |
US4247904A (en) * | 1976-06-18 | 1981-01-27 | Thomson-Csf | Addressing unit for a microprogrammed memory |
US4310881A (en) * | 1979-09-21 | 1982-01-12 | Bell Telephone Laboratories, Incorporated | Conditional transfer control circuit |
US4320453A (en) * | 1978-11-02 | 1982-03-16 | Digital House, Ltd. | Dual sequencer microprocessor |
US4323964A (en) * | 1976-11-01 | 1982-04-06 | Data General Corporation | CPU Employing micro programmable control for use in a data processing system |
EP0059293A1 (fr) * | 1981-02-27 | 1982-09-08 | International Business Machines Corporation | Procédé et dispositif pour l'attribution sélective de ressources d'une unité de commande à un parmi plusieurs utilisateurs |
EP0063256A1 (fr) * | 1981-04-17 | 1982-10-27 | International Business Machines Corporation | Appareil de commande à pipeline avec mémoire d'adresse pour traitement multiple |
DE2560129C2 (de) * | 1974-09-25 | 1982-11-04 | Data General Corp., 01581 Westboro, Mass. | Verfahren für die Erzeugung und Ausführung der Anfangsmikroinstruktion einer zur Ausführung einer Makroinstruktion dienenden Mikroinstruktionsfolge |
WO1982004148A1 (fr) * | 1981-05-22 | 1982-11-25 | Corp Burroughs | Ordinateur numerique pouvant executer des instructions en trois parties multiplexees dans le temps |
US4373180A (en) * | 1980-07-09 | 1983-02-08 | Sperry Corporation | Microprogrammed control system capable of pipelining even when executing a conditional branch instruction |
US4462073A (en) * | 1978-11-08 | 1984-07-24 | Data General Corporation | Apparatus for fetching and decoding instructions |
US4476523A (en) * | 1981-06-11 | 1984-10-09 | Data General Corporation | Fixed point and floating point computation units using commonly shared control fields |
US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
WO1989009968A1 (fr) * | 1988-04-11 | 1989-10-19 | Square D Company | Systeme de communications a processeurs multiples |
US5159674A (en) * | 1982-11-09 | 1992-10-27 | Siemens Aktiengesellschaft | Method for supplying microcommands to multiple independent functional units having a next microcommand available during execution of a current microcommand |
US5163139A (en) * | 1990-08-29 | 1992-11-10 | Hitachi America, Ltd. | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions |
US5452425A (en) * | 1989-10-13 | 1995-09-19 | Texas Instruments Incorporated | Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words |
WO2000004484A2 (fr) * | 1998-07-17 | 2000-01-27 | Intergraph Corporation | Processeur graphique a mot instruction long |
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Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3842405A (en) * | 1971-03-03 | 1974-10-15 | Ibm | Communications control unit |
US3891972A (en) * | 1972-06-09 | 1975-06-24 | Hewlett Packard Co | Synchronous sequential controller for logic outputs |
US3979727A (en) * | 1972-06-29 | 1976-09-07 | International Business Machines Corporation | Memory access control circuit |
US3959777A (en) * | 1972-07-17 | 1976-05-25 | International Business Machines Corporation | Data processor for pattern recognition and the like |
US4007444A (en) * | 1972-11-27 | 1977-02-08 | Institut Francais Du Petrole, Des Carburants Et Lubrifiants Et Entreprise De Recherches Et D'activites Petrolieres Elf | Microprogrammed computing device |
US3800293A (en) * | 1972-12-26 | 1974-03-26 | Ibm | Microprogram control subsystem |
US3956738A (en) * | 1973-09-25 | 1976-05-11 | Honeywell Information Systems, Inc. | Control unit for a microprogrammed computer with overlapping of the executive and interpretative phase of two subsequent microinstructions |
US3943495A (en) * | 1973-12-26 | 1976-03-09 | Xerox Corporation | Microprocessor with immediate and indirect addressing |
US3938098A (en) * | 1973-12-26 | 1976-02-10 | Xerox Corporation | Input/output connection arrangement for microprogrammable computer |
US4103328A (en) * | 1974-02-20 | 1978-07-25 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) | Control apparatus for controlling data flow between a control processing unit and peripheral devices |
US3972024A (en) * | 1974-03-27 | 1976-07-27 | Burroughs Corporation | Programmable microprocessor |
DE2542751A1 (de) * | 1974-09-25 | 1976-04-15 | Data General Corp | Datenverarbeitungssystem |
US3990052A (en) * | 1974-09-25 | 1976-11-02 | Data General Corporation | Central processing unit employing microprogrammable control for use in a data processing system |
DE2560129C2 (de) * | 1974-09-25 | 1982-11-04 | Data General Corp., 01581 Westboro, Mass. | Verfahren für die Erzeugung und Ausführung der Anfangsmikroinstruktion einer zur Ausführung einer Makroinstruktion dienenden Mikroinstruktionsfolge |
US4205372A (en) * | 1974-09-25 | 1980-05-27 | Data General Corporation | Central processing unit employing microprogrammable control for use in a data processing system |
US4001788A (en) * | 1975-03-26 | 1977-01-04 | Honeywell Information Systems, Inc. | Pathfinder microprogram control system |
US4110822A (en) * | 1975-03-26 | 1978-08-29 | Honeywell Information Systems, Inc. | Instruction look ahead having prefetch concurrency and pipeline features |
US4053947A (en) * | 1975-05-14 | 1977-10-11 | Telefonaktiebolaget L M Ericsson | Method and apparatus for executing sequential data processing instructions in function units of a computer |
US4156925A (en) * | 1976-04-30 | 1979-05-29 | International Business Machines Corporation | Overlapped and interleaved control store with address modifiers |
US4247904A (en) * | 1976-06-18 | 1981-01-27 | Thomson-Csf | Addressing unit for a microprogrammed memory |
US4151597A (en) * | 1976-07-23 | 1979-04-24 | Thomson-Csf | Microprogrammable control unit |
US4323964A (en) * | 1976-11-01 | 1982-04-06 | Data General Corporation | CPU Employing micro programmable control for use in a data processing system |
US4085450A (en) * | 1976-12-29 | 1978-04-18 | Burroughs Corporation | Performance invarient execution unit for non-communicative instructions |
FR2409550A1 (fr) * | 1977-11-21 | 1979-06-15 | Burroughs Corp | Appareil d'interface de la famille des gabarits |
US4161026A (en) * | 1977-11-22 | 1979-07-10 | Honeywell Information Systems Inc. | Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes |
US4197579A (en) * | 1978-06-06 | 1980-04-08 | Xebec Systems Incorporated | Multi-processor for simultaneously executing a plurality of programs in a time-interlaced manner |
US4320453A (en) * | 1978-11-02 | 1982-03-16 | Digital House, Ltd. | Dual sequencer microprocessor |
US4462073A (en) * | 1978-11-08 | 1984-07-24 | Data General Corporation | Apparatus for fetching and decoding instructions |
US4310881A (en) * | 1979-09-21 | 1982-01-12 | Bell Telephone Laboratories, Incorporated | Conditional transfer control circuit |
US4373180A (en) * | 1980-07-09 | 1983-02-08 | Sperry Corporation | Microprogrammed control system capable of pipelining even when executing a conditional branch instruction |
EP0059293A1 (fr) * | 1981-02-27 | 1982-09-08 | International Business Machines Corporation | Procédé et dispositif pour l'attribution sélective de ressources d'une unité de commande à un parmi plusieurs utilisateurs |
EP0063256A1 (fr) * | 1981-04-17 | 1982-10-27 | International Business Machines Corporation | Appareil de commande à pipeline avec mémoire d'adresse pour traitement multiple |
WO1982004148A1 (fr) * | 1981-05-22 | 1982-11-25 | Corp Burroughs | Ordinateur numerique pouvant executer des instructions en trois parties multiplexees dans le temps |
EP0079370A1 (fr) * | 1981-05-22 | 1983-05-25 | Burroughs Corp | Ordinateur numerique pouvant executer des instructions en trois parties multiplexees dans le temps. |
EP0079370A4 (fr) * | 1981-05-22 | 1986-06-05 | Burroughs Corp | Ordinateur numerique pouvant executer des instructions en trois parties multiplexees dans le temps. |
US4476523A (en) * | 1981-06-11 | 1984-10-09 | Data General Corporation | Fixed point and floating point computation units using commonly shared control fields |
US5159674A (en) * | 1982-11-09 | 1992-10-27 | Siemens Aktiengesellschaft | Method for supplying microcommands to multiple independent functional units having a next microcommand available during execution of a current microcommand |
US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
WO1989009968A1 (fr) * | 1988-04-11 | 1989-10-19 | Square D Company | Systeme de communications a processeurs multiples |
US4912623A (en) * | 1988-04-11 | 1990-03-27 | Square D Company | Multiple processor communications system |
US5452425A (en) * | 1989-10-13 | 1995-09-19 | Texas Instruments Incorporated | Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words |
US5163139A (en) * | 1990-08-29 | 1992-11-10 | Hitachi America, Ltd. | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions |
WO2000004484A2 (fr) * | 1998-07-17 | 2000-01-27 | Intergraph Corporation | Processeur graphique a mot instruction long |
WO2000004484A3 (fr) * | 1998-07-17 | 2000-07-06 | Intergraph Corp | Processeur graphique a mot instruction long |
US6577316B2 (en) | 1998-07-17 | 2003-06-10 | 3Dlabs, Inc., Ltd | Wide instruction word graphics processor |
Also Published As
Publication number | Publication date |
---|---|
JPS514381B1 (fr) | 1976-02-10 |
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