US3683383A

US3683383A - Loran receiver-indicator

Info

Publication number: US3683383A
Application number: US860354A
Authority: US
Inventors: Sidney G Knox
Original assignee: Individual
Current assignee: Individual
Priority date: 1969-09-23
Filing date: 1969-09-23
Publication date: 1972-08-08
Anticipated expiration: 1989-08-08

Abstract

A LORAN system designed especially for shipboard and aircraft installation so as to provide a navigator with accurate positional data. The system incorporates a precision time-delay circuit having incremental steps of 10 microseconds, together with an interpolator yielding an additional delay period varying from zero to nine microseconds. The end of this time delay period is the instant at which the lower sweep is initiated on the display. Also, a unique ADD-DELETE circuit either adds or subtracts pulses from the oscillator to allow a shifting of phase of the locally-generated PRF so as to match the phase of the received PRF.

Description

United States Patent Knox 1 1 Aug. 8, 1972 [54] LORAN RECEIVER-INDICATOR Primary Examiner-Benjamin A. Borchelt [72] Inventor: Sidney G. Knox, 462] South G. St., Anismm Kinberg Oxnard Calif 93030 Attorney-Richard S. Sciascia, Q. Baxter Warner and Howard J. Murray, Jr. [22] Filed: Sept. 23, 1969 21 Appl. No.: 860,354 ABSTRACT A LORAN system designed especially for shipboard [52] US. Cl ..343/l03 and aircraft installation so as to provide a navigator [5 l 1 Int. Cl ..G0ls 1/24 with accurate positional data. The system incorporates [58] Field of Search ..343/l03 a precision time-delay circuit having incremental steps of i0 microseconds, together with an interpolator Referemes Cit! yielding an additional delay period varying from zero UNKTED STATES PATENTS to nine microseconds. The end of this time delay period IS the instant at which the lower sweep IS in- 3,343,l70 9/1967 Maine ..343/l03 mated 0n h display ALSO, a unique D E E E 2,697,2 circuit eiher adds or subtracts pulses from the oscilla- 2'904'752 9/1959 Perzley 343/103 Ux tor to allow a shifting of phase of the locally-generated 2,93 l ,217 4/1960 Wendt et al. ..343/l03 X 50 as to match the phase f the received PRF' 3,332,079 7/1967 Sarratt ..343Il03 '7 Claims, 23 Drawing Figures 42 44 46 l l VIDEO VERT DEFL VERT DEFL RECEVER A p CONTROL AMP 38 I Nil 9 40 1 p 13m /GAIN RF CHANNEL 1 CONTROL vmso SELECTOR CRCUIT BALANCE 48 (TRACE sz e g m 96 1 A AFC UNEL NK "6.20

i MAN/AFC PRF SELECT SWEEP SPEED 552 9 I2 '6 I '8 $70 2? not:

1 PM 06%. Ea t 5'3? HORlZ SWP HORIZ SWP R CLOCK DELETE COUNTER GEN P z 1 l I. 20 FASTO (5sLow SWEEP osmou I DELAY DELAY 'l/LSEC COUNTER CONTROL COU N LER L INTERPOLATOR 30 FIGJG 29 32 5, 34

DELAY M ICROSECONDS PAIENIEflAm: 8 I972 SHEET DQUF 10 2 FFZ F FFI C coum I! G 5 INPUT DCO s 000 =EXTERNAL RESET Fig. 7

FROM STAGE 2 OF DECODE 6O PRF SELECT (SPECIFIC) Fig.8

PATENTEUAUG 8M2 3.683.383

SHEET 070i 10 IOCKHZG CLOCK FF! I I .k.

Pm= s G341 GATED DELAY; R )0 IOOKHZ RESET L F I g. /4

+4 TE-s- D0 I HUNDREDS; Def J I DELAY .l' RESET THousANDsoD0 VPULSE TO VERTICAL DEFLECTION 0 I82 cmcun 44 gigging) V TO AFC REC cmcuma Fig. /8

PATENTED B 8 3.683.383

SHEET 10 0F 1 0 02m FF D s C JPT'AG E NOTCHG R co F TO IOOKHZ +4 osc 6202 \b VIDEO INv UNBLANK 11- WIDE INHIBIT) CFGND IN FAST SWEEP F l g. 20

ADD PUSH BUTTON I02 G 2ll G2I2 i ADD Do PULSE J (FIG 2) FROM STAGES OF p SWEEP COUNTER SPEED FAST FROM +4 sTAGE3 DELETE 0F -Q PUSH SLOW BUTTON DELETE COUNTER I04 PULSE I G2I3 (52m LS E S 62's IOOKHZ )0 D CLOCK To PRF COUNTER I00 mg CLOCK LORAN RECEIVER-INDICATOR STATEMENT OF GOVERNMENT INTEREST The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION LORAN (long range navigation) is a radio-navigational aid of the hyperbolic type, employing a series of lines plotted by measuring differences in the respective times of arrival of synchronized pulses. The system makes it possible for navigators to obtain fixes" within I mile at distances up to approximately 700 miles in daylight and L400 miles at night.

Conventionally, a number of pairs of pulse transmitters are located at spaced points, one transmitter of each pair being a master and the other a slave.

These stations transmit a series of pulses at a constant repetition rate, differing in time by a fixed amount. The slave station pulses are delayed so as to make their time of arrival later than that of the master station pulses. The time difference therebetween indicates to the navigator how far he is from the stations. For example, if the time difference is the same as that of the transmitted pulses, he is midway between the stations. If not, the time difference is made up of the time it takes the LORAN signal to reach him-approximately 18.6 miles per I microseconds.

Charts are prepared with plot lines of constant time difference between pairs of stations, so that a navigator can determine from a given pair of stations which line he is on. By making a similar observation from another pair of stations, he can ascertain where he is located by the intersection of the lines of constant time difference for the two pairs.

The time differences are observed on a cathode-ray tube presentation in the receiver, with two traces-an upper trace for a master station, and a lower one for its slave. The navigator inserts a delay equal to the difference in arrival time of the two signals. This difference is measured by locally-generated marker pulses, respectively representing delay periods of I0, I00, and [,000 microseconds. The same measuring process is repeated for a second pair of transmitting stations.

SUMMARY OF THE INVENTION Many LORAN receiver-indicators now in use are large in size, of great weight, and require considerable amounts of input power, often reaching several hundred watts. In addition, they exhibit poor long-term stability, limited operating life, and possess overly-critical pulse and digital characteristics. Furthermore, in the event that an a-c power source is not available in the aircraft or ship on which they are installed, it is necessary to employ a rotary power converter, thereby reducing the overall efficiency of the system. The present disclosure is directed to overcoming such drawbacks in a LORAN receiver-indicator through a simplification and improvement in circuit design which increases both the accuracy of the data obtained and the reliability and operating life of the system as a whole.

OBJECTS OF THE INVENTION One object of the invention, therefore, is to provide an improved form of LORAN receiver-indicator.

Another object of the invention is to simplify the electrical circuitry of a LORAN receiver-indicator while at the same time improving its accuracy, efficiency and reliability.

A further object of the invention is to provide a LORAN receiver-indicator which requires less power than standard arrangements without sacrificing performance or stability of operation.

Other objects, advantages, and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is an electrical block diagram of a LORAN receiver-indicator designed in accordance with a preferred embodiment of the present invention;

FIG. 2 is a detailed circuit diagram of the clock generator of FIG. 1;

FIG. 3 is a detailed block diagram of the PRF counter of FIG. 1;

FIG. 4 is a detailed circuit diagram of one of the counter circuits of FIG. 3;

FIG. 5 is a detailed circuit diagram of another of the counter circuits of FIG. 3;

FIG. 6 is a detailed circuit diagram of still another of the counter circuits of FIG. 3;

FIG. 7 is a detailed circuit diagram of the binary-todecimal decoding circuit of FIG. 3;

FIG. 8 is a detailed circuit diagram of the selector switch logic circuit of FIG. 3;

FIG. 9 is a detailed circuit diagram of the PRF master reset generator of FIG. 3;

FIG. 10 is a detailed circuit diagram of the horizontal sweep generator of FIG. 1;

FIG. II is a detailed circuit diagram of the unblank amplifier of FIG. I;

FIG. 12 is a detailed circuit diagram of the horizontal sweep amplifier of FIG. 1;

FIG. 13 is a detailed diagram of the circuitry associated with the cathode-ray tube of FIG. 1;

FIG. 14 is a detailed circuit diagram of the delay counter control of FIG. 1;

FIG. I5 is a detailed diagram, mainly in block form, of the delay counter of FIG. 1;

FIG. 15a is a detailed circuit diagram of the delay reset generator of FIG. 15;

FIG. I6 is a detailed circuit diagram of the lus interpolator of FIG. 1;

FIG. 17 is a detailed diagram of the gain control circuit in the receiver of FIG. 1;

FIG. 18 is a detailed circuit diagram of the video amplifier of FIG. I;

FIG. 19 is a detailed diagram of the vertical deflection control circuit of FIG. 1;

FIG. 20 is a detailed diagram of the AFC circuit of FIG. I; and

FIG. 21 is a detailed diagram of the add-delete circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of a LORAN receiver-indicator designed in accordance with the principles of the present invention. A lkHz clock generator produces basic timing signals (preferably from a quartz crystal oscillator) and supplies them to a plurality of timing circuits (to be subsequently described) thru an ADD-DELETE circuit 12. A Pulse Repetition Frequency (PRF) counter 14 synthesizes the proper sweep recurrence rate of the receiver-indicator. Two controls 16 and 18 select the desired basic and specific recurrence rate. A sweep generator 20 produces the horizontal portion of the upper and lower traces. This sweep voltage is amplified by a sweep amplifier 22 and applied to the horizontal deflection plates of the cathode ray tube (CRT) 24. An unblank amplifier 26 allows CRT beam current to flow only during sweep time. Delay counter control 28 gates the IOOkHz clock pulses into a time delay counter 30 at the proper moment. This time delay counter 30 produces a precision time delay whose length in increments of IO microseconds (us) is determined by the numbers set into a plurality of time delay selector switches 32. At the end of the time delay, a Ins interpolator 34 produces an additional delay from 0 to 9 us as determined by another time delay selector 36. The end of this time delay is the time at which the lower sweep is initiated.

The receiver 38 is tuned to the LORAN transmitter frequency by the channel selector 40. The video output of this broadband receiver is amplified in a video amplifier 42 and applied to a vertical deflection control circuit 44. This control circuit 44 provides the vertical separation between upper (master) and lower (slave) sweeps, and adds the video and the notch (to be later described) to the vertical deflection. A vertical sweep amplifier 46 amplifies the composite vertical signal and applies it to the vertical deflection plates of the CRT 24. An automatic frequency control (AFC) 48 compares the received PRF to the PRF generated in the receiver-indicator by the l00kHz clock generator 10. If there is a difference in frequency between the two, the AFC sends a correcting signal to the clock generator 10. The ADD-DELETE circuit 12 either adds pulses or deletes pulses from the IOOkHz clock train to allow the shifting of phase of the locally-generated PRF to match the phase of the received PRF. A power supply or converter (not shown) may be employed to change the direct current available in an aircraft or ship (for example) into the various voltages required to operate the illustrated receiver-indicator. A detailed discussion of each of the circuits making up the system of FIG. 1 will now be given.

I00 kHz CLOCK GENERATOR FIG. 2 is a schematic diagram of the clock generator 10 of FIG. 1. Quartz crystal X21 determines the frequency of oscillation of field effect transistor (FET) 021. C and L21 are parallel-resonant at lOOkHz. R22 provides a DC return for the gate of 021. R23 sets the operating bias of 021. C24 bypasses R23 at the oscillation frequency. Fine-tuning voltage is applied to C21 thru isolating resistor R21. C21 is a voltage-variable capacitor coupled across X21 by C22, allowing the oscillation frequency to be changed a small amount. C23 provides a calibration adjustment to also change the frequency of oscillation slightly. The resulting signal is coupled thru C26, clamped by diode D21, and then applied to mono-stable multivibrator (single'shot) G21-G22, each integrated circuit, two-input NOR gates whose logic rules are:

a b c input input output 0 I 0 l 0 l HIGH level I 0 0 0 LOW level I 0 The output of G22 is normally a 0 due to bias resistor R24. Both inputs of G21 are normally a 0" so the output of G21 is a I charging C27. The second input to G22 is normally low. A positive-going signal from the oscillator is coupled thru C26 and applied to one input of G21 causing the output of G21 to start going to a 0." This negative-going signal cancels the effect of bias resistor R24 and G22 output goes to a I." This I is coupled back to the second input ofG21 holding the circuit in this state until C27 discharges and again permits R24 to apply a l input to G22 and hence restore the single-shot to its quiescent state with the output of G22 again LOW. The values of R24 and C27 primarily determine the length (time) of the output pulse. The l00kHz signal has a period of 10 us and the single-shot timing is set to approximately 5 us, which results in a near square-wave output. When the second input of G22 goes to a I," the single-shot action is inhibited and output of G22 remains a 0."

PRF COUNTER FIG. 3 is a functional block diagram of the PRF counter 14 of FIG. 1. The

divider chain

50, 52, 54 and 56 count the incoming IOOkHz pulses. A PRF master reset generator 58 causes the counter stages to reset when the number in the counter is equal to the number selected by the decode 60 and selector switch logic 62.

Two of the basic PRFs which may be utilized are designated LOW (25Hz) and HIGH (33 @112). These are each broken down into eight specific PRFs. These PRFs are shown below along with the number that IOOkHz must be divided by in order to obtain each PRF:

PRF CHANNEL BASIC PRF IOOkHz DESIGNATION PRF PERIOD, ms BY L0 25 Hz 40.0 4000 L1 25 Hz 39.9 3990 l L3 25 Hz. 39.7 3970 L5 25 Hz 39.5 3950 L6 25 Hz 39.4 3940 L7 25 Hz 39.3 3930 H0 33 H3 Hz 30.0 3000 H1 33 I13 Hz 29.9 2990 H2 33 I13 Hz 29.8 2980 H3 33 H3 H2 29.7 2970 H4 33 1/3 Hz 29.6 2960 H5 33 H3 Hz 295 2950 H6 33 1/3 Hz 29.4 2940 H7 33 H3 H2 29.3 2930 Two controls pennit selection of the desired PRF. One of these controls is designated in FIG. 3 by the reference numeral 64 and has L (low) and H (high) positions. The other control is not illustrated in FIG. 3 but has positions 0, l, 2, 3, 4, 5, 6 and 7. Logic circuitry associated with these two controls will be discussed subsequently in conjunction with a description of FIG. 8 of the drawings, but at this point it can be stated to allow the PRF counter to divide down the lkHz clock in accordance with the preceding table. For example, assume that channel L is selected. The table indicates that the input clock must be divided by 3,950. Referring back to FIG. 3, assume that the whole PRF counter has just been reset and all stages contain zero count. Stage one begins counting IOOkI-Iz pulses. For the moment assume stage one is a 10 stage rather than the 5 stage it actually is. The frequency out of stage one into stage two is then IOkHz, or one pulse into stage two for every 10 pulses into stage one. Stage two is a 10 counter whose output is one pulse for every 100 pulses into stage one. Similarly, stage three is also a l0 counter whose output is one pulse for every 1,000 pulses into stage one. Thus, for every 1,000 pulses into stage one, stage four receives one pulse. After 3,000 input pulses into stage one, stage four contains a three count which represents 3,000 and enables one of the three inputs to the PRF master reset generator 58 thru the selector switch logic G2. Nine-hundred input pulses later, stage three contains a nine count which enables the second input to the reset generator. Fifty input pulses later, stage two will contain a five count which satisfies the remaining input to the reset generator. At the time all three input lines are enabled (after 3,950 input pulses), the reset logic generates a PRF master reset pulse that rests all counters to zero whereupon the counting sequence begins again as just described. It is readily apparent that the frequency of the PRF master reset pulse is 1/3950 of the IOOkHz clock. Similarly, setting any other basic and specific PRF on the selector switches will cause the PRF counter to divide the l00kHz down by the new number.

In practice, a single pulse at the desired PRF is not satisfactory for operation of the other receiver-indicator circuits of FIG. 1 since some require a pulse at mid- PRF-period as well. One method for obtaining these mid-PRF-period pulses is the following: stage one is a 5 rather than a 10 counter. This change halves the numerical count at which the PRF counter resets. Thus, for the same selector switch settings as before, the counter now divides the IOOkI-Iz input by 1,975 rather than 3,950 as in the example given. The PRF master reset pulse is then twice the frequency of the desired PRF. It is only necessary now to add a simple 2 stage 66 to PRF counter triggered by the PRF master reset pulse. The output of this 2 flip-flop will be a symmetrical square wave whose frequency is the desired PRF and whose transition occurs exactly at mid-PRF. One state of the flip-flop will represent one-half of the PRF period and the other state will represent the next half of the period.

Stage one (50) is a 5 circuit shown in detail in FIG. 4. FF 1, FF2 and FF3 are integrated J-K type bistable multivibrators (flip-flops) connected as a binary counter. The J and K inputs are not used, the input on each being the clock input, c. When the DCO (forced reset) line is at logical 0," a signal transition from l to 0" on the clock line causes the flip-flop to change state. When the DCO line goes to a l," the flip-flops are reset resulting in a 0" and a l at the Q and 6 outputs, respectively. G41, G42 and G43 are NOR gates as previously described. G41 and G42 make up a lps single-shot. Counter operation is as follows: l00kI-Iz input pulses begin counting up the counter. When five pulses have been accumulated, the inputs to G43 are both 0" causing the output to go to a 1. This l" initiates the single-shot G4l-G42 which in turn forces all flip-flops to the reset state. The next input pulse begins counting up the counter and the above action repeats. Thus, the signal frequency out of the 5 stage is one-fifth the input frequency or 20kHz.

Stage two (52) of FIG. 3 is a 10 stage shown in FIG. 5. This counter is similar to the 5 counter just described in FIG. 4 except for three factors. First, there is one more flip-flop included in the stage to allow a 10 count. Second the inputs to G53 are the Sand 2signals rather than the zand Tas in the 5 stage. Third, there is an additional input into G51 which allows the 10 counter to be reset by an external signal as well as by the signal from G53. The next 10, stage three (54), is identical to the 10 stage just discussed.

The 2, 3, or 4 counter, stage four (56), is shown in detail in FIG. 6. FFl and FF2 comprise a simple 4 counter with 2 and 3 outputs. To obtain the 4 signal, the output of FF 2 is differentiated and returned to +Vcc. The only time the zoutput goes to O is after the fourth pulse into stage four. This arrangement for obtaining the zsignal waves one flipflop over conventional methods.

The binary-to-decimal decode logic 60 of FIG. 3 is shown in FIG. 7. The decimal numbers I, 2, 4 and 8 appear naturally in the counter. The decode logic provides the remaining

numbers

3, 5, 6, 7 and 9. The three is obtained from G71 using the T and 2. The T and I generate the 5 out of G72. The 2and Igenerate the 6 out of G73. In a like manner G74 and G75 generate the 7 and 9.

Re-examination of the PRF table supra shows that stage two can either end up with a 0,3, 4, 5, 6, 7, 8, or 9 in it, depending upon which PRF is selected. FIG. 8 shows the selector switch logic 62. As mentioned above, one of the PRF select switches has eight positions, designated in FIG. 8 as 0 thru 7. Note that position one of this select switch 68 is connected to the 9 count output of the decode logic 60. Position two is connected to the 8 count, position three is connected to the 7 count, etc. This is in accordance with the above table. Position zero is connected to +Vcc representing a constant logic 1" from this section of the switch into the reset generator 58. The second section of switch 68 provides a logic 0" in switch position zero and a logic l in positions one thru seven. The basic PRF switch, 64, provides a logic l in the L (LOW) position and a logic 0 in the H (HIGH) position.

The PRF master reset generator 58 of FIG. 3 is shown in FIG. 9. G91, G92 and G93 are NOR gates connected as invertors. The output of G94 goes to a l when PRF LOW-ZERO (L) is selected and stage four goes to a four count. The output of G95 goes to a 1 when I-I1 thru 1-17 (FIG. 8) is selected, and stage four gets a two count. The output of G96 goes to a l when L1 thru L7 is selected. The output of G97 goes to a logic I when HIGH-ZERO (H0) is selected. The output of G98 goes to a logic 0" when either the G96 or G97 outputs go to a l." The output of G99 goes to a l when stage three reaches a nine count. The output of G910 goes to a 0" when either the G99 output goes to a l," or L0 or 1-10 is selected. The output of G911 goes to a l when stage four gets a three count and the output of G98 is a 0." The output of G912 goes to a 0" when the outputs of either G94, G95, or G911 goes to a l The output of G913 goes to a l when the outputs of G93, G910 and G912 are all a logic 0." When the output of G913 goes to a l single-shot G914-G9l5 is initiated generating a PRF master reset pulse. Emitter follower 091 provides a high drive capability to supply stages two, three and four with the PRF master reset pulse.

HORIZONTAL SWEEP GENERATOR A schematic diagram of the horizontal sweep generator 20 of FIG. 1 is shown in FIG. 10. Transistor 0101 is a constant-current source for charging C101. R101, R102, Vcc, and either R106, R107 or R108 determine the charge current. When 0102 is OFF (non-conducting), the voltage across C 101 rises linearly according to the relationship.

e,,= i(t)dt or, since i is constant e it/ C where e, is the capacitor voltage, i is the charge current, 2 is time, and C is the value of C101. When 0102 is ON (conducting), the sweep voltage is clamped to essentially zero and remains there until 0102 is again OFF permitting C101 to again begin charging. 0102 is controlled by single-shot G101-G102 thru invertor G103. G101 receives two external inputs: one master from the PRF counter 14 and one slave from either the PRF counter 14 or the l as interpolator as determined by the sweep speed selector switch 70. The duration of the sweep is determined by C102 and either R109, R1010 or R1011 also depending upon the position of the sweep speed switch 70. Another section of this switch selects either R106, R107 or R108 to ensure that the sweep length (sweep voltage amplitude) will be proper for each sweep speed. The outputs of the sweep generator are the sweep voltage and the two unblank gates, one normal and the other inverted.

UNBLANK AMPLIFIER FIG. 11 shows the schematic diagram of the unblank amplifier 26 of FIG. 1. 0111 is normally ON due to the inverted unblank gate input thru R111. The collector voltage, which is also the output voltage to the CRT control grid, is close to zero. During sweep time the inverted unblank goes to zero tending to turn 0111 OFF. However, R112 provides a second bias path for 0111 which only allows 0111 to partially turn OFF. This prevents the output voltage from rising completely to Vcc. This feature of being able to select the amplitude of the output gate has two advantages: one, it prevents excessive CRT grid voltages and two, it allows a lower breakdown voltage transistor to be used for 0111 assuming a Vcc higher than the desired output gate voltage.

HORIZONTAL SWEEP AMPLIFIER FIG. 12 shows the schematic diagram for the horizontal sweep amplifier 22 of FIG. 1. FET 0121 is connected as a source follower to provide a very high impedance load on the sweep generator. The output stage, 0122 is biased slightly ON by R122 and R123. The sweep voltage is coupled into 0122 by C121 and diode clamp D121. The high voltage negative-going sweep voltage at the collector of 0122 is the output to the horizontal deflection plates of the CRT 24.

CATHODE RAY TUBE FIG. 13 shows the circuits associated with the CRT 24 of FIG. 1. R131, R132 and C131 form a voltage divider which is connected to one of the horizontal and one of the vertical deflection plates. This provides a reference voltage against which both horizontal and vertical deflection amplifiers work. The voltage divider consisting of R133, R134, R135 and R136 divide the +1.5 to 2.0 kv CRT high voltage down to lower voltages for use on various CRT elements. The positive unblank gate is coupled thru C132 to the CRT control grid. The CRT is normally biased OFF by R136.

DELAY COUNTER CONTROL FIG. 14 shows the delay counter control circuit 28 of FIG. 1. F F1 is a set-reset (R-S) flip-flop which is set or reset by a positive-going input on its S or R inputs respectively. The S input signal is obtained by differentiating the positive-going edge of the PRF (mid- PRF) square wave. Setting F F1 enables G141 which allows l00kI-Iz clock pulses to enter the delay counter. The delay reset pulse resets FFl, disabling G141 and shutting off the IOOkHz clock pulses.

DELAY COUNTER FIG. 15 shows a functional block diagram of the delay counter 30 of FIG. 1. Gated IOOkHz clock pulses enter stage one (72), a l0 decade. Because the lOOkI-lz clock has a period of lOps, each count accumulated in the first delay counter stage represents lOps. The IOkHz output of stage one drives stage two (74), another 10 counter. Each count in this counter represents lOQus delay. Stage three (76) is driven by the output of stage two. Each count in stage three represents l,000p.s of delay. The numbers in the three decade counters are decoded in

decimal decoders

78, 80 and 82. The outputs of the three decimal decoders are respectively connected to the three delay selector switches 84, 86 and 88. The output of the three switches provide the inputs of the delay reset generator 90. When the counter stages accumulate the time delay set into the three delay selector switches, all three inputs to the reset generator are enabled and a delay reset pulse is generated which resets the

counters

72, 74 and 76 to zero and shuts off the gated IOOkI-Iz clock pulses.

The three counters 72, 74 and 76 are identical to the counter described previously. The decimal decoders are also identical to the one described above. The three switches 84, 86 and 88 may be of the single pole, 10- position rotary type. The switch positions are indicated directly in thousands of microseconds for switch 88, hundreds of microseconds for switch 86, and tens of microseconds for switch 84. FIG. a shows a schematic diagram of the delay reset generator 90.

ONE MICROSECOND INTERPOLATOR Because of the delay counter 30 cannot resolve time to increments less than l0 .s, a l s interpolator is used to provide delays from 0 to 9 .s in steps of 1,1,3. FIG. 16 shows a circuit of the lus interpolator. Basically the interpolator is a single-shot of the type previously described. C161 and R161 thru R1610 determine the duration of the interpolator pulse. At the end of the interpolator pulse, the negative-going edge sets FF1. The positive-going output of FF1 triggers the sweep generator. The positive-going (trailing) edge of the inverted sweep gate is differentiated by Cl62-R1611 and applied to the DCO (DC reset) input of FF1. Included as part of the interpolator circuit is a sweep-notch generator. This circuit provides a reference notch on the CRT display to indicate where the delay counter is set relative to the received LORAN signals. The sweep notch generator is a single-shot consisting of G163, G164, C163 and either R1612, R1613 or R1614 depending upon the setting of the sweep speed switch 92. The actual timing of the interpolator single-shot is from one to ten microseconds depending upon the setting of the units of microseconds selector switch 94. This switch is labeled 0, 1, 2, 3, 9. The single-shot output pulse is therefore 1,1,8 longer than the switch setting indicates for each switch position. This causes the slave sweep to occur l .s later than the four delay switches indicate. However, the master sweep also incorporates a lp.s delay to compensate for this effect.

RECEIVER The receiver 38 of FIG. 1 is a conventional broadband fixed-tuned, single conversion superhetrodyne. Automatic gain control is not used because of the requirement for individual manual gain control of both sweeps (master and slave). FIG. 17 shows a schematic diagram of the manual gain control circuitry. FF1 generates a square wave one level of which represents the master sweep and the other the slave sweep. Invertors 0171 and 0172 amplify the master-slave square wave sufficiently to allow proper control of receiver gain by the balance and gain controls. The signals at the outputs of 0171 and 0172 are 180 out-of-phase with one another. The balance control 96 allows selection of either phase for application to the receiver gain control line for a particular sweep. The gain potentiometer 98 adjusts the amplitude of the control voltage. The square wave transitions occur at the end of either sweep. This allows sufficient time for the receiver to settle at the next gain control setting before the sweep starts.

VIDEO AMPLIFIER The video amplifier schematic diagram is shown in FIG. 18. Negative video from the video detector and high-pass filter in the receiver is applied to the gate of 0181. R181 sets the bias for 0181. The amplified positive video appears at the drain of 0181 and is power amplified by emittenfollower 0182. The two outputs from the emitter of 0182 go to the AFC circuit 48 and the vertical deflection control circuit 44.

VERTICAL DEFLECTION CONTROL The vertical deflection control circuit 44 sums the signals from the video amplifier, the trace separation square wave amplifier (part of gain control circuit. FIG. 17), and the notch generator single-shot. FIG. 19 shows a schematic diagram of this circuit. 0191 and 0192 form a two-input, single-collector-load, common-emitter type amplifier. R192 and R193 in the emitters allow each transistor to handle a larger input signal without saturating than would be possible with a grounded emitter configuration. The trace separation square wave amplitude is adjusted by the trace separation control 100. Video from the video amplifier is coupled into 0192 via C191. The output of 0191-0192 is summed thru R197 with the notch signal thru R198. These three signals make up the composite vertical deflection signal.

VERTICAL DEFLECTION AMPLIFIER The composite vertical deflection amplifier 46 increases the amplitude of the vertical deflection signal to a level sufficient to be applied to the vertical deflection plates of the CRT 24. The schematic diagram is essentially the same as for the horizontal sweep amplifier 22 discussed above.

AUTOMATIC FREQUENCY CONTROL (AFC) The AFC circuit 48 of FIG. 1 compares the frequency of the locally-generated PRF to the actual PRF being received from the LORAN transmitter. If the local PRF is only a few parts per million different from the received PRF, there will be an undesirable left or right drift in the CRT presentation thereby making measurements difficult for the operator. The AFC circuit, shown in FIG. 20, corrects the local PRF by applying a tuning correction voltage to the voltage-tunable capacitor (C21, FIG. 2) of the IOOkHz crystal clock 10. The comparison is made only during the fast sweep. The video is applied to overdriven amplifier 0201 and the inverted signal applied to the clock input of FF1 thru G202. G202 allows video to pass only during sweep time. The notch signal (approximately one-half as long as the fast sweep) is applied to the reset side of FF1. The notch signal is applied to the set side of the FF. G201 is a logic inverter. Thus, the flip-flop will be either set or reset each sweep depending upon where the video lies in respect to the center of the sweep (the end of the notch). The 1 or 0" output of the F side of FF1 is applied to integrator (low-pass filter) R208-C202. The resultant filtered correction voltage is applied to the IOOkHz clock oscillator. When the sweep speed selector switch is in either the SLOW or MEDIUM position, a logical l is applied to the DCO input of FF1 forcing it to the reset state. Also, 0202 is turned on thru R206. The collector load of 0202 is chosen equal to the collector load of the F side of FF1 so that the level of the Foutput in the SLOW or MEDI- UM sweep position is approximately onehalf Vcc. This clamps the output of the R208-C202 filter to an average value of the FAST sweep correction voltage.

The stage of FF! in FAST sweep is dependent upon where the video lies in respect to the beginning or end of the sweep. The video is always driven toward the center of the CRT display. Because the FFl in one state causes left movement (of the video) and in the other state causes right movement, an in-between" state causes no movement. The FFl, of course, cannot assume such a state, being a binary device. However, as the FF! is alternating from one state to the other, its output voltage is going from (approx.) zero to (approx) +4 VDC. R208 and C202 filter (average) this voltage and provide the "in-between" state. The AFC is arranged to operate only in FAST sweep. Thus, in SLOW and MEDIUM, FFl does not change, and remains in the reset state (because of the signal thru R205) which makes the output HIGH (approx. +4 VDC). If left in this condition, the filtered value would also be +4 VDC. This would cause a slow but steady drift in video on the CRT. 0202 and R207 force the output of the FFl to go to one-half the HIGH value, or about +2 VDC, the no-drift average.

ADD-DELETE When the LORAN receiver-indicator is first switched ON, or when a different PRF is selected, the PRF phasing will usually be different than is desired by the operator. Changing the frequency of the IOOkHz crystal clock is one way of causing a drift in the CRT pattern, altho this method can be quite slow especially if the phasing is very far out. A more reliable method using digital techniques is shown in FIG. 21. The adddelete circuit 12 of FIG. 1 either adds pulses or deletes pulses from the l00kl-Iz clock train. To move the video returns to the right on the CRT, the Add pushbutton 102 of FIG. 21 is depressed. This connects a relatively low frequency signal from stage 3 of the PRF counter 14 of FIG. I to the input of G211. Single shot G2ll-G2l2 generate a Ins pulse for every input to G21]. This lp.s pulse is connected to the ADD PULSE input of the IOOkHz single shot (FIG. 2). This produces the addition of one extra pulse in the XOOkHz train for every 500 normal pulses (because the output of stage 3 of the PRF counter is 1/500 of the input lOOkHz). The extra pulses in the train cause the PRF counter to generate a PRF master reset sooner than it normally would. This makes the sweep start sooner, which in effect makes the received video appear later into the sweep time (move to the right since sweep is from left to right). Similarly, to move the video left on the CRT, the DELETE pushbutton 104 is depressed, causing the low-frequency pulses to trigger lSus single shot G2l3-G2l4. The output of G214 disables G215 for lSps, deleting one IOOkHz pulse from the pulse train. This one missing pulse out of every 500 at the input of the PRF counter causes the PRF counter to generate a PRF master reset later than it normally would. Thus, the sweep will start later, which in effect makes the received video appear to move left on the CRT 24. The rate at which the video moves left or right can be varied by selecting different stages of the PRF counter to obtain the feedback pulses. The source of the feedback pulse is switched from the third stage in SLOW and MEDIUM sweeps to the fifth stage in FAST sweep (or approximately one feedback pulse for 3,000 normal clock pulses).

I claim:

I. In a LORAN receiver-indicator system designed to provide long-range navigational information by means of lines plotted by measuring differences in the respective times of arrival of pulses from a plurality of pairs of transmitters, such pulses having a constant repetition rate being spaced from one another by a fixed amount. said system including:

a cathode-ray tube indicator on the screen of which upper and lower traces are presented;

a timing signal generator producing a pulse output;

a pulse repetition frequency (PRF) counter receiving the output of said timing signal generator and yielding both basic and specific recurrence states; time-delay counter having a controllable delay period the termination of which denotes the instant at which the lower trace of the cathode-ray tube is initiated;

a delay counter control connecting the time-delay counter to the timing signal generator;

a horizontal sweep generator connected to the PRF counter for producing the horizontal portion of the upper and lower LORAN traces presented including means for switching to slow, medium or fast sweep; said switching means connecting the horizontal sweep generator to the time-delay counter during medium and fast sweep;

a broadband receiver;

a vertical deflection circuit connected to said receiver for generating the upper and lower LORAN traces including means for producing a vertical separation between the upper and lower traces;

amplifying means connecting the horizontal and vertical circuits to the cathode-ray tube;

an automatic frequency control (AFC) connected to the receiver, the horizontal sweep generator and the time-delay counter for comparing the received PRF to the PRF of the timing signal generator and for correcting the operating frequency of the latter in the event of a difference therebetween; and

an add-delete circuit interposed between the timing signal generator and the PRF counter for adding or subtracting pulses from the output of said generator to thereby shift the phase of the generated PRF to match the PRF of the incoming LORAN pulses detected by said broadband receiver.

2. The system of claim 1, further comprising an interpolator connected between said time-delay counter and both said first and second sweep generators, said interpolator acting to produce an additional amount of time delay over and above that produced by said timedelay counter.

3. The system of claim 1 in which said timing signal generator is a quartz crystal oscillator.

4. The system of claim I in which the said time-delay counter is made up of a plurality of counter stages connected in cascade, each count of the first of said stages representing a predetermined amount of time delay, with each count of each successive stage representing a different predetermined amount of time delay.

decimal decoders are respectively connected to the outputs of said plurality of counter stages. a

7. The system of claim 6 in which a delay reset generator is connected to receive the combined out puts of said plurality of decimal decoders, the output of said reset generator being fed back to each of said plurality of counter stages.

Claims

1. In a LORAN receiver-indicator system designed to provide long-range navigational information by means of lines plotted by measuring differences in the respective times of arrival of pulses from a plurality of pairs of transmitters, such pulses having a constant repetition rate being spaced from one another by a fixed amount, said system including: a cathode-ray tube indicator on the screen of which upper and lower traces are presented; a timing signal generator producing a pulse output; a pulse repetition frequency (PRF) counter receiving the output of said timing signal generator and yielding both basic and specific recurrence states; a time-delay counter having a controllable delay period the termination of which denotes the instant at which the lower trace of the cathode-ray tube is initiated; a delay counter control connecting the time-delay counter to the timing signal generator; a horizontal sweep generator connected to the PRF counter for producing the horizontal portion of the upper and lower LORAN traces presented including means for switching to slow, medium or fast sweep; said switching means connecting the horizontal sweep generator to the time-delay counter during medium and fast sweep; a broadband receiver; a vertical deflection circuit connected to said receiver for generating the upper and lower LORAN traces including means for producing a vertical separation between the upper and lower traces; amplifying means connecting the horizontal and verTical circuits to the cathode-ray tube; an automatic frequency control (AFC) connected to the receiver, the horizontal sweep generator and the time-delay counter for comparing the received PRF to the PRF of the timing signal generator and for correcting the operating frequency of the latter in the event of a difference therebetween; and an add-delete circuit interposed between the timing signal generator and the PRF counter for adding or subtracting pulses from the output of said generator to thereby shift the phase of the generated PRF to match the PRF of the incoming LORAN pulses detected by said broadband receiver.

2. The system of claim 1, further comprising an interpolator connected between said time-delay counter and both said first and second sweep generators, said interpolator acting to produce an additional amount of time delay over and above that produced by said time-delay counter.

4. The system of claim 1 in which the said time-delay counter is made up of a plurality of counter stages connected in cascade, each count of the first of said stages representing a predetermined amount of time delay, with each count of each successive stage representing a different predetermined amount of time delay.

5. The system of claim 4 in which the said time-delay counter is made up of three counter stages, each count of the first of said stages representing 10 microseconds of time delay, each count of the second of said stages representing 100 microseconds of time delay, and each count of the third of said stages representing 1, 000 microseconds of time delay.

6. The system of claim 4 in which a plurality of decimal decoders are respectively connected to the outputs of said plurality of counter stages.

7. The system of claim 6 in which a delay reset generator is connected to receive the combined outputs of said plurality of decimal decoders, the output of said reset generator being fed back to each of said plurality of counter stages.