US3681617A

US3681617A - Multistable circuit including elements preset for conduction

Info

Publication number: US3681617A
Application number: US792501*A
Authority: US
Inventors: Hiro Moriyasu
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 1969-01-21
Filing date: 1969-01-21
Publication date: 1972-08-01
Anticipated expiration: 1989-08-01
Also published as: SE356188B; GB1297531A; DE2002578C3; IL33710A0; NL170905C; FR2037322A5; DE2002578B2; NL7000815A; IL33710A; DE2002578A1; NL170905B; CH530126A

Abstract

A multistable circuit includes a plurality of latching pairs, each preferably comprising transistors connected in a feedback circuit. Each latching pair is coupled to a transistor of the next latching pair. for presetting such transistor for conduction. The latching pairs alternately receive current from a current switching means, and when the current is switched, the latching pair having the preset transistor immediately conducts.

Description

United States Patent 8 Moriyasu [54] MULTISTABLE CIRCUIT INCLUDING ELEMENTS PRESET FOR CONDUCTION [72] lnventor: Hiro Morlyasu, Portland, Oreg. [73] Assignee: Tektronix,1nc., Beaverton, Oreg. 22 Filed: Jan. 21, 1969 [21] Appl. No.: 792,501

[52] US. Cl; ..307/225, 307/223, 307/279, 307/289, 307/313 [51] Int. Cl ..H03lt 23/08, H031: 23/22, H03k 3/26 [58] Field of Search ..307/220-226, 255, 307/288, 279, 289, 291, 304, 313

[5 6] References Cited UNITED STATES PATENTS Pecar 4....307/223 R Brown ..307/288 X Ross .307/223 Harrick .307/223 Shockley ..307/221 3,081,408 3/1963 3,381,137 4/1968 2,856,544 10/1958 3,033,993 5/1962 2,967,952 l/l96l 8 1451 Aug..1, 1972 4/1965 3,319,086 5/ 1967 Yee ..307/288 3,329,834 7/1967 Klinikowski ..307/223 3,469,110 9/1969 Sherman ..307/223 OTHER PUBLICATIONS Pub 1. Helpful Transistor Analog: 4-layerpnpn 2 Transistors by Stasior in Electronics dated August 10, 1964, pages 66 to 73.

Primary Examiner-Stanley D. Miller, Jr. Attorney-Buckhorn, Blore, Klarquist and Sparkman [57] ABSTRACT A multistable circuit includes a plurality of latching pairs, each preferably comprising transistors connected in a feedback circuit. Each latching pair is cou-.

pled to a transistor of the next latching pair. for

- presetting such transistor for conduction. The latching pairs alternately receive current from a current switching means, and when the current is switched, the latching pair having the preset transistor immediately conducts.

17 Claims, 5 Drawing Figures Durio, Jr .Q ..307/223 PATENTEDAuc H972 3.681.617

sum 1 OF 3 FIG. I

m HIRO MORIYASU wvnvroes.

l Q5 BY BUG/(HORN, BLORE, KLAROU/ST 8 SPAR/(MAN ATTOR/VfYS PATENTEDMII; 1 m2 SHEET 3 OF 3 HI RO MORIYASU lNVE/VTOR B) Buck/10m BLORE, KLAROU/Sf a SPAR/(MN ATTORNEYS MULTISTABLE CIRCUIT INCLUDING ELEMENTS PRESET FOR CONDUCTION BACKGROUND OF THE INVENTION A binary divider or flip-flop is one of the basic circuits in computers, frequency counters, and other digital equipment. The conventional binary flip-flop uses charge commutative devices such as capacitors or.

is also critical as to stray capacitance and transistor high frequency parameters. Moreover, the conventional circuit is usually sensitive to the input drive rise time.

SUMMARY OF THE INVENTION According to the present invention, a multistable circuit includes a plurality of latching pairs or circuits wherein the latching pairs or circuits are adapted to operate consecutively so that only one from a number thereof is on at one time. Coupling means extend from each latching circuit to an active element of the next latching circuit for presetting the same for conduction. Current switching means transfer current between alternate latching circuits, and when switching takes place, the latching circuit including the preset element will immediately conduct. The circuit is operative at frequencies from substantially zero to 600 megahertz.

It is an object of the present invention to provide an improved multistable circuit operative over a wide frequency range.

It is another object of the present invention to provide an improved multistable or divider circuit which is substantially insensitive to input drive rise time. 7

It is another object of the present invention to provide an improved multistable circuit which does not employ commutative time constant means.

It is another object of the present invention to provide an improved multistable circuit which is relatively simple, and which is easily adapted to integrated circuit techniques. I

The subject matter which I regard as my invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. The invention, however, both as to organization and method of opera- DETAILED DESCRIPTION Referring to FIG. 1, a multistable circuit according to the present invention comprises a plurality of latching circuits preferably comprising pairs of transistors. A first such pair comprises a first transistor 0, and a second transistor Q. A second pair comprises transistors Q and 06, a third 0 and Q1, and a fourth Q and Q The transistors of each pair are intercoupled in feedback fashion so that if one transistor conducts, both will tend to conduct heavily. Thus, the collector of Q, is coupled to the base of 0 by means of resistor 10, while the collector of O is similarly connected to' the base of Q, employing resistor 12. Resistor 14 returns the base of Q, to a positive voltage, while resistor 16 returns the base of Q, to a negative voltage. Coupling means, comprising resistor 18, couples the collector of Q to the base of Q A current source, i provides current at the emitters of Q 5 and Q while a current source i provides current at the emitters of Q and Q. In the embodiment of FIG. 1, the first transistors of each pair,

i.e., transistors, Q Q Q and Q, are suitably NPN type, while the second transistor of each pair, i.e., transistors Q5, Q6, Q and Q are of complementary or PNP type.

A current switching circuit comprising transistors Q and Q is employed for providing current alternatively at theemitters of Q and Q, or at the emitters of Q and Q The emitters of Q and Q10 are connected to a cur- I rent source i while the collectors of Q and Q10 are connected to the emitters of Q and Q and the emitters of Q and 0,, respectively. The base of Q1 is returned to a negative voltage through resistor 20, and to ground via Zener diode 22. The base of O is also returned to a negative voltage employing resistor 24, while a Zener diode 26 couples the base of O to an input terminal 28.

Successive latching circuits are intercoupled in the same way as described above in connection with I latching circuits Q Q and Q Q and are arranged in tion, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings wherein like reference characters refer to like elements.

DRAWINGS circuit acconsecutive manner, with alternate transistor pairs receiving current via 0,, or via Q10. Pairs receiving current from O also receive current from source i while pairs receiving current from Q also receive current from source i Resistor 30 from the collector of Q, is connected at point Y to the base of O to provide a continuous circuit connection.

In considering operation of the circuit, let us assume that transistors Q and Q are conducting. Since the collector of each is connected to the base of the other, a feedback circuit is established, each holding the other in conduction. At this time, Q is on, providing current through transistor 0, and resistors 32 and 34 to a positive voltage source. The drop in resistor 34 insures the conduction of 0,, whereby current i;, flows through transistor Q and

resistors

36 and 38. Since the base of Q, is connected to the junction between

resistors

36 and 38, continued conduction of Q, is assured.

At the same time, 0,, being coupled to the base of 0,,

via resistor 30, provides a part of the current i 1 from Q10 through resistor 14 providing a drop in resistor 14 effective for turning Q on. At this time, Q will not be on inasmuch as no current is provided therefor. However, since 0,, conducts, the latching circuit comprising Q and Q, is preset so that when the current i, is switched, the pair 0,, Q will immediately go into feedback conduction. 0;, draws current through resistors 12 and 16 providing a voltage at the base of Q1 presetting Q, for

conduction. Thus, when a positive pulse is applied at.

terminal 28, the base of Q9 Previously in effect tied to a negative voltage, will be raised via Zener diode 26, causing Q, to conduct. Since the transistors Q, and Q are connected differentially, Q, will draw the current previously coupled through Q10, and Q10 will cease conduction. Q, will now deliver current i, to the emitter of Q and transistor Q will conduct immediately since it was preset for conduction. Q now presets Q via resistor l8. I

.Thus, when pair Q Q conducts, transistor Q of the next pair conducts and transistor Q, is preset for conduction. Q, conducts whenever and just as soon as current is provided via transistor'Q Then when the signal input again goes negative, transistor Q, will be shut off, since the negative-going signal will drive the base thereof'below cutoff, and Q will conduct. Since transistor Q, is conducting, transistor Q, will be turned on at its base, and current i, will immediately flow through transistor 0,. As a result, feedback conduction I between transistors Q, and Q. is established. In this cir- Q, and Q alternately conduct. The signal at the collectors of Q, and Q is substantially a square wave with positive altemations being designated T and T while negative alternations are designated T, and T At the time T or when Qg'first conducts, transistor Q, will conduct and provide a negative-output, as illustrated. At time T,, transistor Q, conducts providing a negativegoing output designated Q, in FIG. 2, etc. As hereinbefore mentioned,Q,"is on at the same time Q is on, but so is 0,. Q, continues to conduct at the time T, when Q, is on. Transistors Q Q Q and Q, conduct in that order and then, since Q, is connected to Q, the cycle repeats. Transistors- Q; through Q turn on and off at every other transition of the input waveform thus,

representing a binary countdown by a factorof two in terms of the input frequency. The circuit is useful for any dividing function, ring counter function, or the like. Outputs are suitably derived from the collectors of transistors Q, through Q, by means of isolating transistors (not shown in this embodiment) or alternatively from the collectors of Q, through 0,, by means of isolating transistors.

Inthe circuit of FIG. 1, only the latching circuit in- "cluding a preset transistor will come on next when the current is switched between transistors Q, and Q10- The "non-preset transistor connected tothe collector of Q or Q is biased off. As a latching circuit goes into feedback conduction, atr'ansistor of the next following pair 1 is preset for maintaining the proper sequence in each case.

The circuit is not sensitive to the frequency of input presentedat terminal 28. Thewaveform may be very slowly changing and the circuit will operate as described. However, the circuit will continue to opera'teat high frequencies. For example in integrated circuit operation, the circuit has operated up to a frequency of 600 megahertz.

In FIG. 3, another embodiment of the present invention is illustrated, wherein the latching circuits are formed slightly differently. This time, thefirst latching circuit comprises a first transistor Q, and a second transistor 0,. The remaining latching circuits comprise transistors Q, and Q Q and Q and Q and Q5, respectively. Thus, when the transistor 0 conducts, current is drawn through resistors 42 and Min series from a positive source, wherein 'thevoltage at the junction between the resistors causes transistorQ, to conduct. Similarly, transistor 0,, draws current from a positive source through resistors 46 and 48, raising the voltage at the base of Q and holding the latter transistor in a conducting state. At this time, 'it is assumed a current i, is provided through transistor 0, to transistor 04 in the same manner as hereinbefore described in connection with the embodiment of FIG. 1.

The collector of Q, is coupled to the base of Q with resistor 50 at point Z, so also at this time current is coupled from the collector of Q; through resistor 50 and resistor 52 to ground. The voltage drop across resistor 52 raises the base voltage of transistor Q, presetting transistor Q for conduction. As soon as a positivegoing signal is received at terminal 28, current is delivered through transistor Q, to the emitter of Q, and the latter immediately conducts inasmuch as it is preset for conduction. As ,0, conducts, current is drawn through

resistors

54 and 56 thereby lowering-the voltage at the base of Q6, whereby Q, conducts. As'Q, conducts, current flows through resistors 58 and 52 for maintaining the voltage across resistor52 at a value for retaining Q, in a conducting state. As the current i,- transfers from Q to Q9. the source'of current for resistor 52 shifts from Q to 0,, but is sufficient for maintaining Q, in conduction. e

A further modification of theinvention is illustrated in FIG. 4. This circuit is similar to the FIG. 3 circuit, and like elements are designated similarly. The resistor between the collector of 'a first transistor of a given latching circuit and the base of a second transistor of the same latching circuit has been eliminated. For example, the collector of first transistor Q, is directly connected to the base-of second transistor Q, without an intervening resistor, since such resistor is not necessary to circuit operation, and the schematic diagram is thereby simplified. With switch 60 in-the position shown, circuit operation will be identical to thatof the circuit of FIG. 3. That is, the feedback conduction in each latching pair presets a transistor of the next pair such that when the current shifts in response to an input signal, the next latching pair will conduct. Thus, as current shifts from Q to Q, transistors Q and Q, cease conduction while transistors Q, and Q, start conduction. However, the FIG. 4 circuit is provided with additional transistors Q Q Q and 0,. Each of the last mentioned transistors comprises an additional second transistor for each latching pair. When switch 60 is in the position shown, these additional transistors are not energized. However, when the switch is thrown from position F to position B, transistors Q Q.', Q,', and Q, are energized in place of the non-primed second transistors. In the latter event, the latching pairs comprise transistors Q and Q transistors Q, and Q transistors Q and Q and transistors Q and Q e t Let us assume that transistors Q, and Q, are conducting with switch 60 thrown into position 8. Current from the collector of Q flows through resistor 62 maintaining the conduction of transistor Q while the collector current from transistor 0,, flows through

resistors

64 and 66 for maintaining transistor Q in a conducting state. The collector of transistor Q is also coupled to the base of transistor via resistor 68 and a current flows through resistor 68 and resistor 70 7 located between the base of transistor 0;, and ground. Transistor 0;, is thus preset for conduction. Now, when a positive-going signal is received at terminal 28, and current i switches from transistor 0, to transistor Q transistor 0;, will conduct instead of transistor 0, inasmuch as transistor Q was preset through resistor 68. With succeeding transitions at input terminal 28, the multistable circuit will operate in a reverse direction such that each latching pair in succession from right to left becomes conductive and presets the next. Switch 60 is thrown to R for reverse operation, and to F for forward operation.

A further embodiment of the present invention is illustrated in FIG. and employs entirely NPN transistors. The circuit is therefore easily implemented in an integrated circuit construction. It will be appreciated by those skilled in the art that the various diodes illustrated in the circuit are easily fabricated in the same integrated circuit construction with the NPN transistors. The transistor pairs comprising latching circuits respectively comprise transistors Q and Q transistors Q and Q transistors Q and Q and transistors Q and Q In the FIG. 5 circuit, the emitters of transistors Q and Q receive current from the collector of Q while the emitters of transistors Q and Q are similarly connected to receive current from the collector of Q The collector of Q is directlyconnected to the base of Q while the emitter of 0., is returned to ground through a resistor 72. Transistor Q; is one of the differential pair of transistors and the emitter of transistor Q, is connected to the emitter of transistor On, the latter having its base connected to a source of reference voltage, R. The collector of transistor Q is returned to a positive voltage, and the collector of transistor O is coupled to the same positive voltage through resistor 74. Transistors Q and Q comprise a current switching pair or differential amplifier circuit for switching the current passing through resistor 72 so that it flows either to 0 or Q The collector of transistor O is also connected to the cathode of a Zener diode 76, the anode of which is connected to the base of transistor 0,. The anode of diode 76 is returned to ground via resistor 78. Also, the collector of transistor O is coupled to the base of transistor Q of the next latching circuit by way of Zener diode 80 having its anode connected to the base of Q as well as through resistor 82 to ground.

The collector of transistor O is coupled through resistor 84 to the emitter of an isolation transistor 86 having its base connected to the junction between a diode 88 and a resistor 90 interposed in that order between a positive voltage and ground. A resistor 92 connects the collector of transistor 86 to a positive voltage, and an output terminal 94 is also connected to the collector of transistor 86. Transistor 86 operates as a common base transistor amplifier for isolating the 0,, Q latching pair from an output load which may be connected at terminal 94.

Each of the stages is substantially identical, and the last latching pair, Q.,, Q is connected to the first latching pair at point X. The collector of transistor 0,, is connected to a positive voltage through resistor 96 and the emitter of transistor 0, is returned to ground via resistor 98. The emitter of transistor Q14 is also connected to the emitter of transistor Q while the collector of Q is connected to a positive voltage. A resistor 100 is located between the collector of transistor Q, and the emitter of an isolating transistor 102. Zener diode 104 is disposed between the collector of transistor Q and the base of transistor 0,. Also a Zener diode 106 is connected between point X and the base of 0,, the anode of the Zener diode being connected to the base of 0,.

Let us assume transistor 10 is on and that the feedback pair comprising transistors Q and Q; is operated. Transistor Q, is conducting and transistor 0,, is nonconducting. The current from the collector of Q passes through 0, and resistor 100 dropping the voltage at the base of transistor Q Transistor Q1 conducts instead of Q and voltage at the collector of O is high. The voltage level at the collector of transistor 0,, is reduced by Zener diode 104 so that it is appropriate for application at the base of transistor 0., for maintaining the conduction of Q Transistors Q4 and 0 are thus connected in a feedback arrangement. Also, the voltage at the collector of transistor O is applied at point X to Zener diode 106, located between the collector of Q and the base of Q Therefore, the voltage at the base of Q presets Q for conduction. Now, when a positive-going voltage is received at terminal 28 and current i shifts, transistor Q will conduct inasmuch as the latter is the only transistor among transistors Q Q Q and Q which has been preset for conduction. The change in the condition of Q1, of course, is coupled to terminal 94 via transistor 86.

The circuits according to thepresent invention are not encumbered by rate or rise time determining commutation components, but rather the next stage to be on is preset at the same time the previous stage goes into conduction, and therefore commutation problems are substantially nonexistent. As hereinbefore mentioned, the circuit will operate and keep step with an input changing at an exceedingly low or substantially d.c. switching rate, up to a signal of several hundred megahertz. The various multistable circuit stages themselves provide suitably divided outputs, or may be combined in various manners to produce a desired output pulse configuration. Although each of the circuits illustrated includes four 4 latching stages, it will be appreciated that stages may be added as desired. E.G., two of the-circuits of the present invention may be employed together, with the output of each circuit operating as the input of the other circuit.

While I have shown and described several embodiments of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects.

I claim:

1. A multistable circuit comprising: a plurality of latching circuits each comprising a pair of transistors interconnected in a feedback arrangement,

and means for directly and continuously coupling a first feedback pair to a control electrode of a transistor of a second feedback pair so that the transistor of the second feedback pair is preset for conduction at the time that feedback conduction takes place in the first pair.

2. The circuit according to claim 1 wherein saidtransistor of said second pair is provided current so that it conducts substantial operating current at the same time the first pair conducts.

3. The circuit according to claim 1 further including 4 conduction in one. transistor tends to predetermine the state of the other transistor,

means for coupling a collector of one transistor 0 each priorpair to the base of a transistor of a next pair in sequence for presetting that transistor of the next pair for conduction, at the time that feedback conduction takes place in the prior pair, and current switching means. for switching a predetermined supply current between alternate feedback pairs respectively coupled by said 7 coupling means so'that when current is switched, the transistor pair including the preset transistor goes into feedback conduction. 5. The circuit according .to claim 4. wherein a first transistor of each pair is connected to said current switching means and wherein said coupling means couples the collectorv of a second transistor of each pair to the base of the firsttransistor'of the next pair for resetting the same. v

6. The circuit according to claim 4 wherein the first transistor of each pair is connected to saidcurrent switching means and wherein the collector' of the first transistor of each pair is coupled by said coupling means to the second transistor in the next pair for tuming on such second transistor of the next pair and presetting the first transistor of thenext pair.

. 7. The circuit according to claim 4 further including additional second transistors wherein each-additional second transistor is also coupled with one of said first transistors to form. a. feedback pair and additional coupling means for coupling each additional second transistor to a first transistor of a prior pair,

and means for selectively providing current to said second transistors or to said additional second transistors for securing reversible presetting in said multistable circuit.

8. The circuit according to claim 4 wherein said first and second transistors are of opposite conductivity types, and wherein both transistors of a given pair are adapted to conduct at the same time during feedback operation.

9. The circuit according to claim 4 wherein the coupling means from a last transistor pair in sequence is coupled for presetting atransistor of a first transistor pair in the same sequence.

, 10. The circuit according to claim 4 wherein said first and second transistors are of complementary conductivity types, and further including a second source of current for said second transistors. I

ll.-The circuit according to claim 41 wherein said firstandsec ndtr 't rs eof sam d "t type and furthe f l c udir ig Z ier dropping means for coupling the output of each second transistor to the input of the first transistor of the same pair. i a

l2..The circuit according to claim 11 wherein said coupling means between a feedback pair and a transistor of the next pair for presetting the same comprises a Zener diode.

13. The circuit according'to claim 4 wherein said first and second transistors are of the same conductivity type and further including an additional transistor as-' sociated with each pair connected in a differential amplifier circuit with the second transistor of each pair.

14. A multistable circuitcomprising:

a plurality of latching circuits each including a feedback pair of active elements, wherein said first ones of said latching circuits are adapted to al-- temate in operating sequence of feedback conduction with second ones of said latching circuits, means for applying a voltage from a given latching circuit to one of the active elements of the next latching circuit for presetting such element atthe time when feedback conduction takes place in the given latching" circuit, 1 and meansfor providing a current to the said one element of the next latching circuit so that substantial current conduction takes place therein as the same is preset at the same time that feedback conduction takes place in the given latching circuit,

therebyenabling subsequent feedback conduction inthe next latching circuit. 15. A multistable circuit comprising:

a plurality of latching circuits, each including afeed- I means for applying a voltage from the said given feedback circuit to an active element of a=prior latching circuit in sequence,

and means for selecting between forward and reverse operation of such multistable circuit.

16. A multistable circuit comprising: I

a plurality of latching circuits each comprising a pair of transistors interconnected in a feedback arrangement, said transistors having collector electrodes and control electrodes,

and means for directly andcontinuously coupling a collector electrode of a transistor of a first feedback pair to a control electrode of a transistor of a second feedback pair so that the transistor of the second feedback pair is preset for conduction at the time that feedback conduction takes place in the first feedback pair.

17. The circuit according to claim 16 wherein said direct coupling means comprises a resistor.

l III UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,681,617 Dated Au gust 1, 1972 Inventor(s) HIRO MORIYASU' It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

C01. 3, line 35, "negative-output" should be -negative-going output-- Signed and sealed this 9th day of January 1973 (SEAL) Attest:

EDWARD M.FLETCHER,JR. I ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents FORM PO-1050 (10-69) USCOMNPDC 5O37 p6 u.s. covnnmzm' PRINTING omc: I!" o-au-J:

Claims

1. A multistable circuit comprising: a plurality of latching circuits each comprising a pair of transistors interconnected in a feedback arrangement, and means for directly and continuously coupling a first feedback pair to a control electrode of a transistor of a second feedback pair so that the transistor of the second feedback pair is preset for conduction at the time that feedback conduction takes place in the first pair.

2. The circuit according to claim 1 wherein said transistor of said second pair is provided current so that it conducts substantial operating current at the same time the first pair conducts.

3. The circuit according to claim 1 further including current switching means for switching supply current between transistors of said first and second pairs.

4. A multistable circuit comprising: a plurality of feedback circuits each comprising a first transistor and a second transistor and coupling means between said transistors so that conduction in one transistor tends to predetermine the state of the other transistor, means for coupling a collector of one transistor of each prior pair to the base of a transistor of a next pair in sequence for presetting that transistor of the next pair for conduction, at the time that feedback conduction takes place in the prior pair, and current switching means for switching a predetermined supply current between alternate feedback pairs respectively coupled by said coupling means so that when current is switched, the transistor pair including the preset transistor goes into feedback conduction.

5. The circuit according to claim 4 wherein a first transistor of each pair is connected to said current switching means and wherein said coupling means couples the collector of a second transistor of each pair to the base of the first transistor of the next pair for resetting the same.

6. The circuit according to claim 4 wherein the first transistor of each pair is connected to said current switching means and wherein the collector of the first transistor of each pair is coupled by said coupling means to the second transistor in the next pair for turning on such second transistor of the next pair and presetting the first transistor of the next pair.

7. The circuit according to claim 4 further including additional second transistors wherein each additional second transistor is also coupled with one of said first transistors to form a feedback pair and additional coupling means for coupling each additional second transistor to a first transistor of a prior pair, and means for selectively providing current to said second transistors or to said additional second transistors for securing reversible presetting in said multistable circuit.

9. The circuit according to claim 4 wherein the coupling means from a last transistor pair in sequence is coupled for presetting a transistor of a first transistor pair in the same sequence.

10. The circuit according to claim 4 wherein said first and second transistors are of complementary conductivity types, and further including a second source of current for said second transistors.

11. The circuit according to claim 4 wherein said first and second transistors are of the same conductivity type and further including Zener diode voltage dropping means for coupling the output of each second transistor to the input of the first transistor of the same pair.

12. The circuit according to claim 11 wherein said coupling means between a feedback pair and a tRansistor of the next pair for presetting the same comprises a Zener diode.

13. The circuit according to claim 4 wherein said first and second transistors are of the same conductivity type and further including an additional transistor associated with each pair connected in a differential amplifier circuit with the second transistor of each pair.

14. A multistable circuit comprising: a plurality of latching circuits each including a feedback pair of active elements, wherein said first ones of said latching circuits are adapted to alternate in operating sequence of feedback conduction with second ones of said latching circuits, means for applying a voltage from a given latching circuit to one of the active elements of the next latching circuit for presetting such element at the time when feedback conduction takes place in the given latching circuit, and means for providing a current to the said one element of the next latching circuit so that substantial current conduction takes place therein as the same is preset at the same time that feedback conduction takes place in the given latching circuit, thereby enabling subsequent feedback conduction in the next latching circuit.

15. A multistable circuit comprising: a plurality of latching circuits, each including a feedback pair of active elements, wherein first ones of said latching circuits are adapted to alternate in operating sequence of feedback conduction with second ones of said latching circuits, means for applying voltage from a given latching circuit to one of the active elements of the next latching circuit causing such element to be preset for conduction at the time when feedback conduction takes place in the given latching circuit, means for applying a voltage from the said given feedback circuit to an active element of a prior latching circuit in sequence, and means for selecting between forward and reverse operation of such multistable circuit.

16. A multistable circuit comprising: a plurality of latching circuits each comprising a pair of transistors interconnected in a feedback arrangement, said transistors having collector electrodes and control electrodes, and means for directly and continuously coupling a collector electrode of a transistor of a first feedback pair to a control electrode of a transistor of a second feedback pair so that the transistor of the second feedback pair is preset for conduction at the time that feedback conduction takes place in the first feedback pair.