US3670144A - Electronic plugboard controlled data processor - Google Patents

Electronic plugboard controlled data processor Download PDF

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Publication number
US3670144A
US3670144A US203071A US3670144DA US3670144A US 3670144 A US3670144 A US 3670144A US 203071 A US203071 A US 203071A US 3670144D A US3670144D A US 3670144DA US 3670144 A US3670144 A US 3670144A
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United States
Prior art keywords
memory
information
circuitry
plugboard
locations
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Expired - Lifetime
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US203071A
Inventor
Mary Anne Breslin
George R Cogar
Charles A Lee
Donald O Neddenriep
Albert J Romeo
Ernesto G Sevilla
Torkjell Sekse
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Sperry Corp
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Sperry Rand Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/08Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers from or to individual record carriers, e.g. punched card, memory card, integrated circuit [IC] card or smart card
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/08Digital computers in general; Data processing equipment in general using a plugboard for programming

Abstract

An electronic processing unit having solid state components and including a punched card reader, printer and punch output, and plugboard program for controlling the operations of start, stop, read, add, subtract, compare, insert, delete, print, punch, etc. The processor can perform the operations of transfer of information, add, compare, and edit. It can use 80-, 90-, or 160column cards.

Description

United States Patent Breslin et a1. 5] June 13, 1972 [54] ELECTRONIC PLUGBOARD [56] References Cited CONTROLLED DATA PROCESSOR UNITED STATES PATENTS Ihvemors= y Anne Breslin, Philadelphia; George 2,493,858 1 1950 Carroll et al., ..235 61.8 R. Cogar, Doylestown. both of 2,615,629 /1952 Dayger et al... ..235/6l9 Charles A. Lee, Stamford, Conn.; Donald 3,035,764 5/1962 Beman 235/61 9 O. Neddenriep, Willow Grove; Albert J. 2,973,141 2/1961 Berezin.... .235/61 9 Romeo, Springfield, both of Pa.; Ernesto 2,907,526 lO/ 1959 Havens.... ..235/174 G, Saving, New York Torkje" 2,910,240 Havens...: ..235/l74 Sekse, Norristown, Pa.

Primary Eraminer-Daryl W. Cook Asslghw Sperry Rand Corporahon, New York, Attorney-Charles c. English, William E. Cleaver and Charles E. McTiernan [22] Filed: June 18, 1962 ABSTRACT [21] Appl' 203071 An electronic processing unit having solid state components and including a punched card reader, printer and punch out- 52 us. c1 ..235/6l.9, 340/1725 p and p gbo p g for controlling the operations of 51] Int. Cl- ..G06f 7/12, G06f7/00,G06f /00 Start, p, read, subtract, compare, insert, delete, p

[58] Field ofSearch ..235/61.6 R,6l.9 R; 340/1725 Punch, etc. The Processor can Perform the operations of MFMORY MAR (OM/ ARA transfer of information, add, compare, and edit. It can use or column cards.

21 Claims, 438 Drawing Figures F01, F62, F63, (0/1 7804 04TH R M E E 0 6 M A a 7 5 TRANSLATE A R A T 90 x53 0 Y E p R A (C A ACC R w e a MEMOR y wsnwcrm/V 'p/I' CON/7M4 PRCEDE/VCE (WA/7790A 1 9 1 l /6o/9o 55 957 P/e/Nrfl? FKTENTEBJuu 13 m2 SHEET 03 OF 184 l rl PATENTEUM 13 2972 SHEET 05 OF 184 70 Cal.

P'A'TEN'TEBJUM 1 a me SHEET 08 OF 184 MEMORY PRECfDE/VCE AR/THMET/C" REA OER PATENTEDJUN 1 a 1972 SHEET 13 [1F 184 (Sci;

Wk WNWEYWR PATENTEUJUH 'I 3 I972 SHEET 18 []F 184 NUK m3 QM

Claims (21)

1. Plugboard controlled data processor comprising in combination: magnetic core memory means having a plurality of locations; plugboard means providing means to transmit signals therefrom and means to receive signals therein; counter means for sequentially generating a plurality of programs signals, said counter means connected to said plugboard to provide said program signals thereat; plurality of gate circuits each having control input means connected to certain of said means to receive signals on said plugboard; memory addressing circuitry connected to said magnetic core memory and to said gate circuits for selectively enabling write-in and read-out of information to and from said memory; first register means connected to said memory to receive information therefrom and to transmit information thereto; second register means; third register means; comparison circuitry connected to said first register means and said second register means to make comparison between information held respectively thereat; circuitry means connecting the said third register means to said second register means to receive information therefrom; arithmetic means connected to said second register and to said first register to receive information therefrom and to operate thereon, said adder means further having circuitry means connecting the output therefrom to said first register means; and circuitry means connecting said adder means and said memory means and said gate circuits to the said plugboard means to receive the command signals therefrom.
2. A plugboard controlled processor comprising in combination: magnetic core memory means having a plurality of locations for storing information; punched card reader means; addressing means connected to said memory means for selecting any particular location in said memory means; logic circuitry means connecting said punched card reader to said addressing means for transmitting information therethrough to be stored in said memory from said punched card reader; buffer means connected to said memory means for receiving information therefrom and transmitting information thereto; circuit means for affecting information transmitted from said memory means connected to said buffer means; said punched card reader formed to accept information from punched cards in three different codes; translation means in said card reader for automatically translating said three codes into two different machine codes in order for such information to be processed; and plugboard means connected to said magnetic core memory, to said logic circuitry means, to said circuit means for affecting information, to said punched card reader input means so that when signals are routed by said plugboard, information can be read from said punched card reader and thereafter transmitted through said memory to be acted upon and returned thereto.
3. An asynchronous, plugboard controlled processor comprising in combination: magnetic core memory means having a plurality of locations each capable of storing n bits of information where n bits of information represent a word; addressing means connected to said magnetic core memory means to enable any selected ones of said locations to be activated to receive or transmit information; card reader input means; card punch output means; printer output means; first logic circuitry means connecting said memory means to said card punch output means and to said printer output means; first circuitry means connecting said card reader input means to said addressing means and to said first logic circuitry means; plugboard means having means to route command signals and means to address the least significant and most significant locations of an operand stored in said memory means and connected to said card reader means, to said printer means, to said punch output means and to said first logic circuitry means whereby an operand can be stored into or extracted from said memory which can be any number of bits in length up to the capacity of the memory to be used in said processor; program counter means for sequentially initiating a plurality of program signals connected to said plugboard means to provide said program signals thereat; arithmetic means for performing arithmetic operations on information transmitted thereto connected to said plugboard means; second circuitry means connecting said arithmetic means to said first logic circuitry means; and instruction control signal means connected to said plugboard means and further circuitry connected to said first logic circuitry means whereby when said plugboard means is wired to transmit signals from said program counter means to said first logic circuitry means and to said instruction control signal means and to any one or all of said reader input means, said punch output means on said printer output means said processor will operate to receive information into said memory and transmit information out of said memory for purpose of having said information operated arithmetically thereon in accordance with instruction control signals generated in response to the routing of command signals on said plugboard.
4. A plugboard controlled processor to be used with punched cards which may have information coded thereon in one of three different card codes comprising in combination: memory means having a plurality of memory locations; addressing means connected to said memory means to enable particular ones of said locations to be activated to receive or transmit information; said plugboard means having output means and having means to address the least significant and most significant locations of an operand stored in said memory means connected to said addressing means whereby an operand of any variable length can be processed through said memory; punched card reader means having control circuitry connected to said plugboard means; storage address circuitry means connected to said punched card reader means and to said magnetic core memory means and formed to direct information from said punched card reader means to said magnetic core memory means in one of two machine codes depending upon which of said three different card codes is present on a card being read and said storage address circuitry means further formed to direct said information to preselected memory locations in accordance with the type of machine code present on said punched cards being read by said punched card reader means; program signal source means connected to output means on said plugboard means in order to provide program signals thereto, whereby when said plugboard is wired from said output means to said control circuitry of said punched card reader, information will be supplied to said memory in response to said punch card reader transmitting the same.
5. A plugboard controlled processor according to claim 4 wherein said program signal source means includes a program counter formed to sequentially generate program signals to said output means on said plugboard means and further includes a program counter control means connected to said program counter and to said plugboard means and formed to start said program counter at any desired count at the start of processor operation and alternatively at the end of any regularly occuring program step in response to signals applied to said plugboard means.
6. A plugboard controlled processor according to claim 5 and further including: circuitry for performing arithmetic, logical and edit operations; first circuitry means connecting said circuitry for performing arithmetic, logical and edit operations to said plugboard means and to said magnetic core memory means; first control circuitry means connected to said circuitry for performing arithmetic, logical and edit operations and to said plugboard means; printer output means; card punch output means; and precedence control circuitry connected to said printer output means, to said card punch output means and to said addressing means to make a determination of the precedence amongst said punched card reader, said printer output means and said card punch output means in order that an operation of each can be performed on a single program step.
7. A plugboard controlled processor comprising in combination memory means having a plurality of locations; addressing means connected to said memory means; plugboard means having input means connected to said addressing means to select the positions in said memory means for the most significant location as well as the least significant location for a first operand and the most significant location and the least significant location for a second operand each of said operands being selected variable in length; memory data register means connected to said memory means for accepting information signals therefrom for temporarily storing said information signals; and sequence control means connected to said addressing means and to said plugboard means and formed to cause said addressing means to sequentially activate memory locations within said memory means according to a pattern which goes from a least significant location to a most significant location and alternatively according to a pattern which goes from a most significant location to a least significant location.
8. A plugboard controlled processor according to claim 7 wherein there is further included a comparison circuit means connected to said addressing means and to said sequence control means to compare the address defined at said plugboard input means with the address currently activating said memory means in order to provide an ending address when the memory locations being activated coincide with the memory locations defined on said plugboard means.
9. A programmed controlled processor according to claim 8 wherein there is further included second control circuitry connected to said comparison circuit and to said addressing means to prevent the comparison of the memory locations activated with the address of said first operand as defined on said plugboard means after there has been an identity between the ending address of said second operand and the activated memory locations.
10. A plugboard controlled processor according to claim 7 wherein said sequence control means inclUdes first and second counters, a comparison means and first and second logic circuitry, and wherein said plugboard means has command signal input means wired and wherein said first logic circuitry connects said first counter to said plugboard means so that the starting address of an operand can be transferred from said plugboard to said first counter and thereafter to said addressing means and whereby the ending address of the first operand can be transferred from said plugboard to said first counter and thereafter to said comparison means whereby comparison will be made between the starting address of said first operand and the ending address of said first operand and if there is no comparison said information is returned to said first counter means where it is decremented and alternatively incremented depending upon whether a command signal is an ascending or a descending transfer, and further whereby the starting address of a second operand is transferred through said second counter to said addressing means and the ending address of a second operand is transferred thereafter through said second counter to said comparison means and whereby after a comparison has been made if there is no comparison said information in said addressing means is returned to said second counter and either increased or decreased depending upon whether the command signal is an ascending or a descending transfer.
11. A plugboard control processor comprising in combination: memory means having a plurality of locations each capable of storing n bits of information; addressing means connected to said memory means to enable particular ones of said locations to be activated to receive or transmit information; plugboard means providing input means to select the positions in said memory means for the most significant location and the least significant location for a first operand as well as the most significant location and a least significant location for a second operand, said operands being variable in length; memory data register means connected to said memory means to accept information therefrom and return information thereto; first accumulator means connected to said memory data register means; second accumulator means connected to said first accumulator means; adder means connected to said first accumulator means and said second accumulator means and further connected to return information to said memory data register; control circuitry means connected to said memory data register and said addressing means for selecting information from said memory to be transferred to said memory data register and further connected to said first and second accumulators to transfer information from said memory data register respectively into said first and second accumulators; circuitry means connecting said adder means to said plugboard means to enable said adder means to receive information from said first and second accumulators for the purpose of performing an arithmetic operation thereon; and further control circuitry means connected to said circuitry means connecting said adder to said memory data register to cause the information in said adder means to be transferred to said memory data register for a further transfer therefrom to said memory means.
12. Plugboard control processor according to claim 11 wherein there is further included a comparator means connected to said memory data register and to said first accumulator whereby information which is transferred to said first accumulator and second information which is transferred to said memory data register can be compared to generate a control signal to initiate a further logic operation on said information.
13. A plugboard control processor according to claim 11 wherein there is further included edit control means connected to said plugboard means and to said memory data register and wherein there is further included instruction control circuitry, said instruction control circuitry connected to said plugboard whereby when said plugboard prOvides a command signal to said edit control circuitry and alternatively wherein said instruction control circuitry provides a command signal to said edit control circuitry whereby the information in said memory data register is edited before it is transmitted therefrom.
14. A plugboard control processor comprising in combination: a memory means having a plurality of locations; memory access control means connected to said memory means for selectively enabling the write-in or read-out of information from chosen ones of said plurality of locations; temporary storage means connected to said memory means for receiving information therefrom and returning information thereto; arithmetic means connected to said temporary storage means for performing arithmetic functions upon information transmitted from said selected ones of said plurality of storage locations; punched card reader input means connected to said memory access control unit for transferring information into said memory through said memory access control unit; printer output means connected to said temporary storage means for receiving information therefrom; and plugboard means having input means connected to said memory access control means to select positions in said memory means for the most significant locations as well as the least significant locations of operands which are processed and connected to said memory means, to said memory access control means, to said punch card reader input means, to said printer output means, and to said arithmetic means for providing command signals thereto to enable information to be read from said punched card reader input means into said memory wherefrom it is transmitted to have an arithmetic operation performed thereon and returned to said memory as well as to said printer output.
15. A plugboard controlled processor comprising in combination: memory means having a plurality of locations; memory address circuitry connected to said memory means for selectively enabling the read-out and write-in of information from and to any particular ones of said locations thereby enabling operands to be variable in length for any number of bits up to the capacity of said plurality of locations; temporary storage means connected to said memory means to receive information therefrom and transmit information thereto; punched card input means connected to said memory address circuitry; printer output means connected to said temporary storage means; first circuitry means for performing arithmetic, logical, transfer, insert, and deletion operations and information transmitted from said temporary storage means; instruction input means coupled to said first circuitry means for enabling individual instructions to be formed by said first circuitry means; program counter formed to generate a plurality of initiating signals; selective circuitry means connecting said program counter to said instruction input means for selectively initiating instructions therethrough; means for changing the sequence of said initiating signals connected to said program counter and adapted to be connected to said selective circuitry means in order to enable said processor to selectively change said sequence of instruction; control circuitry means connected to said punch card input means and said printer output means; and execute order means connected to said control circuitry and adapted to be connected to said selective circuitry means whereby said control circuit enables said punch card input means and printer output means to perform certain instructions only upon receipt of an execute order from said selective circuitry means.
16. The processor defined in claim 15 wherein a first group of said memory locations are assigned for use by said reader and connected to said memory address circuitry, equal in number to the maximum number of units of information able to be derived from a punched card; a second group of memory locations are assigned for use by said printer and connected to said memory address circuitry, equal in number to the maximum number of units of information able to be printed on a single line; control circuitry connected from said reader and said printer to said memory address circuitry for controlling said memory address circuitry to access each of their assigned memory locations respectively upon receipt of an execute instruction following receipt of a print order or read order instruction; and early termination circuitry associated with and connected to each said reader and said printer for terminating said access of their said assigned memory locations after a given number of locations less than said assigned number of locations have been accessed.
17. The processor defined in claim 16 wherein early termination circuitry includes a first register means for temporarily storing an address defining the memory location ending accessed, a second register means for storing an address from said instruction input means defining the last memory location to be accessed; and means for comparing connected to said first and said second register to compare the contents of said first and second registers and provide an output signal upon coincidence of said respective first and second register contents, and circuitry means connecting an output from said comparing means to said memory address circuitry for terminating instruction then being executed.
18. A data processor comprising in combination a memory device having a plurality of separate memory locations; address circuit means connected to said memory device for selectively writing in and reading out any number of chosen ones of said memory locations; punched card reader input means connected to said memory address circuit and including a translation circuit; circuitry means connected to said translation means for deriving information from cards passed through said punch card reader in said first, second or third codes and transferring said information to said predetermined ones of said memory locations into first or second machine codes; temporary storage means connected to said memory means for receiving information therefrom and transmitting information thereto; printer output means connected to said temporary storage means for printing information received therefrom without translation; first circuitry means connected to said temporary storage means to perform arithmetic, logical, transfer, insertion or deletion operations and information being processed in said processor; sequencing signal means connected to said memory address circuit means for sequentially enabling a plurality of memory locations of said memory means; and plugboard means connected to said first circuitry means, to said printer output means, to said punch card reader means, to said memory address circuit means, to said memory means whereby instruction signals provided by said plugboard means can cause information to be transmitted from said punch card reader to said memory means through said temporary storage to said first circuitry means back to said temporary storage and to said printer output means to provide an output therefrom.
19. A data processor according to claim 18 wherein there is further included a card punch unit connected to said temporary storage means and formed to operate in a row by row or column by column manner; second logic circuitry means connecting said plugboard means to said address circuit means to cause the latter to access said memory device in a first mode when said card punch unit is operating row by row and in a second mode when said card punch unit is operating column by column.
20. A data processor according to claim 19 wherein said card punch unit is formed to punch cards according to first, second and third modes each of which is different and wherein said second logic circuitry is formed to selectively condition said memory address circuit to access different portions of said memory for each of said different codes.
21. A data processor according to claim 18 wherein there is further included memoRy precedence circuitry connected to said printer output means and to said card punch unit and wherein said memory precedence circuitry is connected to said second logic circuitry to determine the order of priority of operations between said printer output means and said punch output unit.
US203071A 1962-06-18 1962-06-18 Electronic plugboard controlled data processor Expired - Lifetime US3670144A (en)

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DE (1) DE1449567C3 (en)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6254288B1 (en) * 1995-02-17 2001-07-03 Guido Heyns Integrated circuit controlled transaction management system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2493858A (en) * 1942-11-28 1950-01-10 Ibm Alphabet printing tabulator with program controls
US2615629A (en) * 1950-12-12 1952-10-28 Ibm Record controlled machine combination
US2907526A (en) * 1956-11-02 1959-10-06 Ibm Electronic accumulator
US2910240A (en) * 1954-09-28 1959-10-27 Ibm Counting register employing plus-andminus adder means
US2973141A (en) * 1956-02-24 1961-02-28 Curtiss Wright Corp Control means with record sensing for an electronic calculator
US3035764A (en) * 1955-05-24 1962-05-22 Telecomputing Corp Point of sale recorder

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2493858A (en) * 1942-11-28 1950-01-10 Ibm Alphabet printing tabulator with program controls
US2615629A (en) * 1950-12-12 1952-10-28 Ibm Record controlled machine combination
US2910240A (en) * 1954-09-28 1959-10-27 Ibm Counting register employing plus-andminus adder means
US3035764A (en) * 1955-05-24 1962-05-22 Telecomputing Corp Point of sale recorder
US2973141A (en) * 1956-02-24 1961-02-28 Curtiss Wright Corp Control means with record sensing for an electronic calculator
US2907526A (en) * 1956-11-02 1959-10-06 Ibm Electronic accumulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6254288B1 (en) * 1995-02-17 2001-07-03 Guido Heyns Integrated circuit controlled transaction management system

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DE1449567A1 (en) 1969-05-14
BE633718A (en)
GB1015651A (en)
NL294203A (en)
FR1361640A (en) 1964-05-22
DE1449567B2 (en) 1973-11-15
DE1449567C3 (en) 1974-06-06

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