US3668661A

US3668661A - Character coding, memory, and display system

Info

Publication number: US3668661A
Application number: US836270A
Authority: US
Inventors: Duncan E Cull; Alvin E Culbertson
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp; National Cash Register Co
Priority date: 1969-06-25
Filing date: 1969-06-25
Publication date: 1972-06-06
Anticipated expiration: 1989-06-06
Also published as: JPS4823687B1; GB1259089A

Abstract

Characters each identified by a bit code are advanced serially to a memory comprising continuously cycling shift registers, one for each bit of the code. The bits for each character enter the shift registers in parallel. The character codes are placed one behind the other in the shift register memory by operation of a character counter and a second counter which is its complement. The memory is formatted for control of a cathode ray tube display operating to legibly display all characters in the memory. A major raster traces lines of character positions. A minor raster traces each character in a dot matrix at each character position.

Description

United States Patent Cull et al. 1 June 6, 1972 54] CHARACTER CODING, MEMORY, AND 3,400,334 9/1968 Hildebrandt .340/1725 x DISPLAY SYSTEM 3,413,610 11/1968 Botjer et a]. .340/172.5 3,471,835 10/1969 Gribble et al. ..340/l72.5 X [72] Inventors: Duncan E. Cull; Alvin E. Culbertson, both of Dayton, Ohio Primary Examiner-Gareth D. Shaw Assistant ExaminerSydney R. Chirlin 73 A The N ti nal h R I 1 sslgnee Daytonaozfio Cas egister Campany Attorney-Louis A, Kline and Albert L. Sessler, Jr.

[22] Filed: June 25, 1969 [57] ABSTRACT [21] Appl. No.1 836,270 Characters each identified by a bit code are advanced serially to a memory comprising continuously cycling shift registers, one for each bit of the code. The bits for each character enter [52] US. Cl. "340/1715 the shift registers in Parana]. The character codes are placed [5] Ilrl. CI. ..G06f 13/02 one behind the othcr in the Shift register memory by Permian [58] held Search "340/1725; 235/157 ofa character counter and a second counter which is its com plement. [56] References Cited The memory is formatted for control of a cathode ray tube dis- UNITED STATES PATENTS play operating to legibly display all characters in the memory. A major raster traces lines of character positions. A minor 3,235,849 2/1966 Klein 340/1725 raster traces each character in a dot matrix at each character 3,275,993 9/1966 Bartlett et al. ....340/l72.5 position 3,328,772 6/1967 Oeters ..340/l72.5 3,400,377 9/1968 Lee ..340/172.5 8 Claims, 30 Drawing Figures l 45 4" l 4I2 :1 MEMORY OUTPUT ITRANSMIT 1 BUFFER BUFFER GATES l i j l INTERFACE MEMORY INTERFACE l f 540 1 54b L RX G 225 EDUNTER e an 050005 RX COMPLEMENTARY GATES F H l H RX F COMPLEMENTARY 22?? j 1 GATES up DOWN /9 CONTROL CONTROL 1 GATE GATE COUNTER LOCKOUT 4'0 l GATE 4 l 1 LINE 400 TX INTERFACE CO TE e??? AMPLIFIERS l l i it i i (OUT) TX 1 F COMPIElFIEESNTARY l 1 H i l TX COMPLEMENTARY 1 COUNTER L T I i STROBE I GATE l ,J

PATENTED 5 9 SHEET [)2 [IF 23 FIG.3A

RECEIVER BUFFER BUFFER GATES BUFFER I GATES II II COUNTER LOCKOUT GATE COMPOSE GATES "-r TRANSMIT ATIII J INVENTORS DUNCAN E. CULL 8| SOM GATE BUFFER GATES RECEIVER AMPLIFIERS 4 INTERFACE 35\ KEYBOARD BUFFER BUFFER GATES COUNTER CONTROL LOGIC A B5 COUNTER KEYBOARD DISPLAY CLEA Tx CLEAR SEND Rx CLOCK AJ CLOCK CONTROL Rx CLEAR KEYS XTAL

CLOCK I ALVIN E. cuLBE/ZT BYW THEIR ATTORNEYS PATENTEDJIIII 8H7? 3668,6361

SHEEI 03M 23 FIG.3B

| 45 4M I 1 412 H MEMORY OUTPUT TRANsMIT- H BUFFER BUFFER GATES l I I M INTERFACE MEMORY INTERFACE i 40s I 540 54M I I Rx I G225 COUNTER e BIT 407 1 DECODE I V f l Rx I COMPLEMENTARY L GATES Rx F COMPLEMENTARY 'I STROBE I-; V GATES UP DOWN I 22:? w l LOCKOUT I GATE E 4 i I 400 TX LINE I ADVANCE L, INTERFACE I COUNTER GATE AMPLIFIERS I 1', (OUT) TX 4 I l COMPEEEEJTARY 1 i I i I TX COMPLEMENTARY i COUNTER L STROBE I GATE E l I INVENTORS DUNCAN E. CULL 8 ALVIN E CULBERTSON THEIR ATTORNEYS MTENTEDJUH 6 I972 SHEET FIG. 5A

on or 23 SIG INVENTORS DUNCAN E. CULL 8 ALVIN E. CULBERTSON W fi% BY MM THEIR AT TOR NEYS PATENTEDJUH 6|972 131568.661

sum DSUF 23 FIG. 5B 32 INVENTORS DUNCAN E. CULL 8| ALVIN Ev CULBERTSON THEIR ATTOR NEYS FIG. 6A

PATENTEDJUH 6 1912 3. 668 661 SHEET 05 0F 23 INVENTORS DUNCAN E. CULL 8 ALVIN E. CULBERTSON fuzz A THER ATTORNEYS FIG. 6B

PATENTEDJun 5 I972 SHEET INVENTORS DUNCAN E. CULL 8| ALVIN E. CULBERTSON 5X44; WM

BY H

THEIR AT TORNE YS PATENTEDM 61971 668,661

SHEET 0a or 23 FIG.?

FIG. l2

fit r ik INVENTORS E3+E4+E5 DUNCAN E. CULL 8 ALVIN E. CULBERTSON THEIR ATTORNEYS FIG. 8A

SHEET INVENTORS DUNCAN E. CULL 8| ALVIN E. CULBERTSON THEIR ATTOR NE YS PATENTEDJUH 6 1972

sum

10 or 23 wtm w.

mtm ON mtm ON INVENTORS DUNCAN E. CULL 8 ALVIN E. CULBERTSON B! X THEIR ATTORNEYS PATENTEUJUH 6 I972 sum 11 or 23 INVENTORS DUNCAN E. CULL THEIR ATTORNEYS PATENTEDJUH B 1972 FIG. IOB

SHEEI INVENTORS DUNCAN E. CULL 8| ALVIN E. CULBERTSON THEIR ATTORNE YS PATENTEDJun 6 I972 3.668.661

saw 13 or 23 INVENTORS DUNCAN E. CULL B ALVIN E. CULBEF! SON THEIR ATTORNEYS PATENTEDJUH 6|972 3.668.661

sum 1n 0F 23 FIG.|3

INVENTORS DUNCAN E. CULL a ALVIN E. CULBERTSON 4 BY MML THEIR ATTOR NEYS PATENTED JUN 6 I972 SHEET 18 OF 23 FIG. |7A

A8 sa awn INVENTORS DUNCAN E. CULL 8 ALVI CULBE Tson THEIR ATTOR NEYS PATENTED 5 2 sum 11 or 23 FIG. I78

lNVENTORS DUNCAN E. CULL 8 ALVIN E. CULB RTSON THEIR ATTORNEYS PATENTEDJun 6 I972 SHEET INVENTORS DUNCAN E. CULL 8 ALVIN E. CULBERTSON flowflm THEIR ATTORNEYS

Claims

1. In combination, a cyclic memory device having a number of code memory cells and including a first buffer, a first code source providing codes in serial relation and adapted to generate a strobe with each code, a first counter for counting said strobes, a second buffer, means responsive to each strobe to place the code provided therewith in said second buffer, clock means having different states, the number of different states of said clock means being equal to the number of code memory cells in said memory device, said clock means clocking said codes cyclically through said memory device, a second counter having a lock-up state, transfer means responsive to a selected state of said clock means to complementarily transfer the count of said first counter to said second counter whereby said second counter is set away from said lock-up state by a count equal to the count in said first counter, said clock means clocking said second counter whereby said second counter counts to its lock-up state following said transfer, means responsive to lock-up of said second counter to transfer the code then residing in said second buffer to said first buffer whereby successive codes received from said source enter successive cells of said memory device.

2. The combination of claim 1 including means to reverse the direction of count of said first counter so as to enter newly received codes in previously used memory cells.

3. The combination of claim 1 wherein said first counter comprises a plurality of bistable devices, said second counter comprises an equal number of bistable devices, and said means to complementarily transfer comprises means to transfer the complement of each bistable device in said first counter to a corresponding one of the bistable devices in said second counter.

4. The combination of claim 3 in which said bistable devices are flip-flops.

5. The combination of claim 1 including gate means to recognize a predetermined strobe count in said first counter, means responsive to said gate means upon recognition of said predetermined strobe count to augment the count in said first counter, and circuit delay means responsive to said gate means to enter a predetermined code in said first buffer after the code with which the strobe producing said recognized count was generated has been transferred to said first buffer.

6. The combination of claim 1 including a second code source providing second codes in serial relation and providing a second strobe with each second code, a third counter for counting said second strobes, a fourth counter having a lock-up state, a third buffer, means responsive to each second strobe to place the second code provided therewith in said third buffer, second transfer means responsive to a selected state of said clock means to complementarily transfer the count of said third counter to said fourth counter, said clock means clocking said fourth counter, and means responsive to lock-up of said fourth counter to transfer the second code then residing in said third buffer to said first buffer, the selected state of said clock means at which the count of said first counter is complementarily transferred to said second counter being different from the selected state of said clock means at which the count of said third counter is complementarily transferred to said fourth counter.

7. The combination of claim 6 including means to remove from said memory device those codes received from one only of said first and second code sources.

8. Circuitry for placing codes in a cyclic memory device driven by a cyclic clock having plural clock states equal in number to the cells in said memory device comprising, in combination, a code source, said source adapted to generate a strobe with each code issued therefrom, a first counter for counting said strobes, code receiver means, means responsive to each said stroBe to transfer the code provided therewith to said receiver means, a second counter having a lock-up state, means responsive to a selected state of said clock means to complementarily transfer the count of said first counter to said second counter, said clock means clocking said second counter, and means responsive to lock-up of said second counter to transfer the code from said receiver means to said memory device.