US3643222A

US3643222A - Remote supervisory system

Info

Publication number: US3643222A
Application number: US791895*A
Authority: US
Inventors: Naokazu Kimura
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1968-01-22
Filing date: 1969-01-17
Publication date: 1972-02-15
Anticipated expiration: 1989-02-15
Also published as: JPS5011021B1

Abstract

A remote supervisory system having two dynamic shift registers for storing a series of signals representing the new and the old state, respectively, of remotely supervised equipment, wherein the outputs from the dynamic shift registers are cyclically distributed to display circuits for a continuous or flickering display of the existing state of each equipment.

Description

llnite hmfiS Patent Minimum 51 Feb.15,1972

[54-] REMU'WE SUPERWSORY SYSTEM [72] lnventor: Naoliazu Kimura, Shimodate-shi, Japan [73] Assignee: Hitachi, Ltd, Tokyo, Japan [22] Filed: Jam-117, 1969 21 Appl. No; verses [30] Foreign Application Priority Data Jan. 22, 1968 Japan ..43/3259 1 [52] US. Cl .340/1725 [51] 11m. (31 [58] Field of Search ..340/l72.'5, 201, 286, 324, 331,

[56] References Cited UNITED STATES PATENTS 3,124,674 3/1964 Edwards et a] ..340/l72.5 X

R555 7' TE RM/NAL TMNSFE/i DEV/CE ..Gil6i 3/14 3,310,782 3/1967 Sinn et al ..340/172.5 3,404,377 10/1968 Frankel .....340/172 5 3,449,721 6/1969 Dertouzos et a1... .....340/l72 5 3,465,299 9/ 1969 Schellenberg ..340/ 1 72.5 3,228,020 1/1966 Gassenheimer et al. ..340/286 3,293,611 12/1966 Goldfeld et a1 .340/172 5 3,379,831 4/1968 ll'lashimoto ..340/ 324 Primary Examiner-Paul J, Henon Assistant Examiner-Harvey E. Springbom Attorney-Craig, Antonelli and Hill [57] ABSTRACT A remote supervisory system having two dynamic shift registers for storing a series of signals representing the new and the old state, respectively, of remotely supervised equipment,

wherein the outputs from the dynamic shift registers are cycli cally distributed to display circuits for a continuous or flickering display of the existing state of each equipment.

7 Claims, 7 Drawing Figures DYNAMIC SHIFT REG.

PMENIEUFEB 15 m2 3MB 0 222 SHEET 1 OF 5 FIG. /0

RESE T All/EPTEI? DYNAMIC SH/F T REG.

TRANSFER DEV/CE GATE INVENTOR ATTORNEY 5 IIIill/IO'IIE SIJIEIIVISDIIY SYSTEM BACKGROUND OF THE INVENTION This invention relates to improvements in remote supervisory systems.

A remote supervisory system is connected with a distant controlled station by a small number of transmission lines for supervising the operation of a multiplicity of pieces of equipment installed in the distant controlled station. It is therefore unable to simultaneously transmit the states of all the equipment in the distant controlled station. It is common practice to cyclically and sequentially transmit the state of each equipment or to transmit the state of a particular equipment which undergoes a change in the operating state thereof for the remote supervision of each equipment.

To this end, a control station is equipped with a memory means such as a relay corresponding. to each equipment installed in a distant controlled station and the memory means stores the newest information concerning the state of each equipment so that the state of each equipment can be known from the contents of the memory means. Thus, in a remote supervisory system of this kind, the memory device for storing the state of each equipment occupies a large proportion of the system. This tendency becomes quite marked in the case of a control station adapted for centralized supervision of a plurality of controlled stations, even in the case of a centralized remote supervisory system in which information error-detecting circuits, logical determination circuits and the like are disposed in common to all the controlled stations. Thus, the centralized remote supervisory system becomes bulky in size and expensive, which cancels substantially the advantages of centralization of the system.

On the other hand, unmanned power plants, substations, chemical plants and the like dispersedly located in various places are an increasing trend nowadays, and a small-sized and inexpensive remote supervisory system is now in strong demand.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a remote supervisory system which is adapted for serial storage of information transmitted thereto. For serial storage of information, circulating memory means such as a dynamic shift register, magnetic drum, electromagnetic delay line memory or supersonic delay line memory may be utilized. By employment of the serial storage, a reduction in the size and cost of the system has been accomplished.

Other objects, features and advantages of the present invention will be apparent from the following description of a few preferred embodiments thereof when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS:

FIGS. Ia and Ib show a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory view showing one form of information transmitted from a controlled station.

FIG. 3 is an electrical connection diagram of one form of a display circuit preferably employed in the present invention.

FIG. 4 is a diagrammatic illustration of waveforms for the explanation of the operation of the circuit shown in FIG. 3.

FIGS. 5 and 6 are partial block diagrams of other embodiments of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS:

FIGS. Ia and lb together provide a block diagram showing an arrangement of various means disposed in a control station in the remote supervisory system according to the present invention. The following description will be directed to a centralized system in which a plurality of groups of information 1),, D D,,. are cyclically and continuously sent out from each controlled station in a dual fashion as shown in FIG. 2.

However, it will be understood that the present invention is also applicable to a 1:] control system.

A receiver means II receives the information sent out from respective controlled stations and sequentially delivers the information corresponding to the respective controlled stations while discriminating the information according to a predetermined order or predetermined priority. .A bit-synchronizing circuit I2 produces a pulse for each bit of the information so received. The received information is stored in a shift register 13 by successive shift thereof by the pulses delivered from the circuit I2. The number of bits that can be stored in the register I3 may be equal to the number of bits in each group of information. The number of bits is I3 in the example shown in FIG. 2. For example, the information D in FIG. 2 means that a first equipment is on, a second equipment is on, a third equipment is off, etc.

A coincidence circuit I4 compares the successively received information with old information delivered from the shift register I3. The coincidence circuit I4 delivers an output when all the bits in each group of the new and old information coincide with each other, but does not deliver any output when any one of the bits in the new information does not coincide with the corresponding bit in the old information. A gate I5 is opened whenever an output is delivered from the coincidence circuit I4 so as to allow for passage therethrough of the information in the shift register I3. When the gate I5 is so opened, the data stored in a memory circuit I6 is replaced or renewed by the information supplied from the register I3. A counter 17 counts the number of pulses delivered from the bitsynchronizing circuit I2. A synchronizing signal detector I8 detects a synchronizing signal SYC shown in FIG. 2. The counter I7 is reset by an output from the synchronizing signal detector 18. A clock oscillation circuit 19 generates clock pulses having a frequency of, for example, several hundred kilocycles. A counter 20 counts the number of clock pulses delivered from the oscillation circuit I9. The counter 20 has a capacity of IXmXn, where l is the number of controlled stations, m is the number of information groups for each controlled station, and n is the amount of information in each group corresponding to the number of pieces of equipment in each group.

Decoders

21, 22 and 23 are provided for the in formation in each group, groups and individual controlled stations and decode the output from the counter 20 to suitably deliver respective outputs corresponding to the number of information bits in each group, the number of groups and the number of controlled stations. A group circuit 24 is operative to decode the output from the counter I7 to deliver a signal representing a specific group of the received information. A transfer device 25 is actuated by the signal delivered from the decoder 21 so as to sequentially deliver the information stored in the memory circuit I6 in accordance with a predetermined sequence.

A group coincidence detector circuit 26 delivers an output when the group signal delivered from the circuit 24l coincides with the group signal generated by the decoder 22 in the control station. A station coincidence detector circuit 27 delivers an output when the signal representing the station being selected by the receive means I1 coincides with the station signal generated by the decoder 23 in the control station. An AND-circuit 28 delivers an output when both the

circuits

26 and 27 deliver their outputs. A gate 29 is opened in response to delivery of an output from the circuit 28 so as to allow for passage therethrough of the information delivered from the scanner 25. An inhibit gate 30 is closed to inhibit passage of any information therethrough when the circuit 26 delivers an output. However, the inhibit gate 30 is. opened to allow for passage therethrough of information delivered from a circulating or serial memory means 32, such as a dynamic shift register, which is described later, when the circuit 28 does not deliver any output. The information passed through either of the

gates

29 and 30 is passed through and delivered from an OR-circuit 3I. The serial or circulating memory means 32 is advanced step by step by the signal supplied from the circuit lluln'l min 19 so as to sequentially store the information delivered from the circuit 31. The data stored in the memory means 32 is replaced or renewed by new information supplied from the gate 29 when the latter is opened. On the other hand, when the gate 29 is not opened, the gate 30 is opened to repeatedly supply the same contents to the memory means 32, which therefore stores the same information serially. A gate 33 is openedwhen a signal is supplied from a terminal 37 so as to allow for passage therethrough of the output from the OR-circuit 31. An inhibit gate'34 is closed when a signal is supplied from'the terminal 37 so as to inhibit passage therethrough of the signal. However, the inhibit gate 34 is opened when no signal is supplied from the terminal 37 so as to allow for passage therethrough of an output from a circulating or serial memory means 36, such as a dynamic shift register. The signal passed through either of the

gates

33 and 34 is passed through and delivered from an OR'gate 35. The serial memory means 36, like the memory means 32 described above, is advanced step by step by the signal supplied from the circuit 19 so as to sequentially store the signal delivered from the circuit 35. The terminal 37 is provided to supply a memory contents renewal instruction signal therethrough when it is desired to renew the data stored in the memory means 36 so that the data stored in the memory means 36 coincides with the data stored in the memory means 32.

A coincidence detector circuit 38 delivers an output when the output from the memory means 32 coincides with the output from the memory means 36. An AND-circuit 39 delivers an output when the circuit 38 delivers an output and the information output from the memory means 32 is 1. The output from the circuit 38 is supplied to an inhibit circuit 40 as an inhibit signal input thereto. Other inputs to the inhibit circuit 40 are an information output from the memory means 32 and a signal coming from a terminal 43. Therefore, the inhibit circuit 40 delivers an output when there is no inhibit signal input, that is, no output is delivered from the circuit 38, and when the information output from the memory means 32 is l and a signal appears at the terminal 43. The output from the circuit 38 is also supplied to an inhibit circuit 41 as an inhibit signal input to the latter. Other inputs to the inhibit circuit 41 are an output signal from an inverter 42 and a signal supplied from a terminal 44. The input to the inverter 42 is an information output from the memory means 32 and is inverted by the inverter 42. Therefore, the inhibit circuit 41 delivers an output when there is no inhibit signal input, that is, no output is delivered from the circuit 38, and when the information output from the memory means 32 is and a signal appears at the terminal 44. The

terminals

43 and 44 are flicker signal input terminals, that is, signals intermittently appearing and disappearing at a predetermined period are applied to these

terminals

43 and 44. The

circuits

39, 40 and 41 are connected to an OR-circuit 45 so that an output is delivered from the OR-circuit 45 when an output is delivered from any one of the

circuits

39, 40 and 41. Outputs from the OR-circuit 45, information decoder 21, group decoder 22 and station decoder 23 are supplied to an output distributor circuit 46 which acts to sequentially distribute the output from the OR-circuit 45 to predetermined display circuits L L -L,,,,,, which are determined according to a given bit information in a given group of a given controlled station. As will be described in detail with reference to FIGS. 3 and 4, the output from the OR-circuit 45 is distributed to a specific display circuit so that this display circuit is energized in response to the appearance of the output from the OR-circuit 45 and continues to display until the next period is reached.

Referring to FIGS. 3 and 4 showing one form of the display circuit and the waveforms for illustration of the operation of the circuit. theinformation is applied through the distributor circuit 46 to an input terminal 301. The information applied to the terminal 301 is then applied to the base of a transistor 302 through a resistor 303. The collector of the transistor 302 is connected to a power supply E through a resistor 304. while the emitter ofthe transistor 302 is grounded. A transistor 305 has its base connected to the collector of the transistor 302 through a capacitor 306. The collector of the transistor 305 is connected to the power supply E through a display lamp 307, while the emitter of the transistor 305 is grounded. The connection point between the capacitor 306 and the base of the transistor 305 is grounded through a diode 308.

Suppose now that an information output 1" is applied to the input terminal 301. Then, the transistor 302 is turned on and the charge stored in the capacitor 306 with a polarity as shown during the off period of the transistor 302 is discharged through the diode 308 in a very short time. Upon disappearance of the information output 1" applied to the terminal 301, the transistor 302 is turned off, and as a result, a charging current ic flows across the capacitor 306 in the direction as shown to turn on the transistor 305 thereby to energize the display lamp 307. The charging current ceases to flow after a lapse of time which is dependent upon the resistance of the resistor 304 and the capacitance of the capacitor 306. After a fixed time, the transistor 305 is turned off and the display lamp 307 is deenergized. When, therefore. the information output 1 is applied to the terminal 301 at a predetermined interval, the above operation is repeated before the lamp 307 is deenergized. In other words. the lamp 307 maintains its stably energized state as if the information output 1" is continuously applied or stored.

Waveforms

32 and 43 shown in FIG. 4 represent the information output from the memory means 32 and the flicker signal input to the terminal 43 in FIG. 1b, respectively, when they are associated with a specific display circuit. The display circuit is in no way limited to the form shown in FIG. 3 and may comprise a known analog-holding circuit.

As will be apparent from the above description, the present invention is featured by serially storing the received information in a predetermined order instead of storing the information in memory means such as relays which are arranged in a 1:] relationship with corresponding equipment. Thus. much information can be stored in a very small-sized memory means.

It will be seen from the embodiment shown in FIGS. 1a and 1b that the memory stored in the serial data means 32 is renewed each time information from each controlled station is received, while the other serial memory means 36 normally stores the memory which was kept in the memory means 32 before at least one memory cycle takes place in the memory means 32, and the memory in the memory means 36 is renewed by the same memory as that stored in the memory means 32 when an instruction signal'is applied to the terminal 37. Therefore, whether or not a change occurs in the state of the equipment in a controlled station can be identified on the basis of whether or not the same information output is given by the memory means 32 and 36. Further, the existing state of such equipment can be known from the fact that the newest information is either 1" or 0.

As will be apparent from the description with regard to the circuits 38 to 46 and the display circuits L in the embodiment shown in FIGS. 10 and 1b, the state of each equipment in a controlled station can be known from the state of a corresponding single lamp as follows:

Continuously energized: The equipment is continuously in its on state.

Continuously deenergized: The equipment is continuously in its off" state.

'Discontinuously energized (with period T The equipment is presently in its off" state as a result of a change from the On" state to the off state.

Discontinuously energized (with period ,T The equipment is presently in its on state as a result of a change from the of "state to the on state.

The period 'l in the above represents the flicker period of the flicker signal applied to the terminal 44, and the period l1, represents the flicker period of the flicker signal applied to the terminal 43.

um mu..-

After a change in state has been confirmed by the attending engineer and a necessary measure has been taken, an instruction signal may be applied to the terminal 37 to renew the memory of the memory means 36 by the same memory as that stored in the memory means 32. This results in stepping the flickering display and the lamp is either continuously energized or continuously deenergized.

While a manner of display in which a lamp is provided for each equipment has been described in the embodiment of FIGS. la and lb, another embodiment shown in FIG. 5 relates to a two-lamp display comprising a red lamp and a green lamp.

In FIG. 5, a display control section including serial memory means 32 and 36 and succeeding elements is merely shown for the sake of simplicity. The memory means 32 applies its information output to an inhibit circuit 511 as an input to the latter, while the memory means 36 applies its information output to the inhibit circuit 511 as an inhibit input to the latter. Thus, the inhibit circuit 5i delivers an output when the information out put from the memory means 32 is 11" and the information output from the memory means 36 is 6" The information outputs from the memory means 32 and 36 are also applied to an AND-circuit 52 so that the AND-circuit 52 delivers an output when both the information outputs are ll." An AND-circuit 53 receives, as its inputs, a signal applied to a terminal 54 and the output from the circuit Ell so that the AND-circuit 53 delivers an output when both the inputs are simultaneously applied thereto. The terminal 54 is a flicker signal input terminal, that is, a voltage intermittently appearing and disappearing at a predetermined interval is applied to the terminal 56. The outputs from the

circuits

53 and 52 are adapted to be applied to an OR-circuit 55 so that the OR-circuit 55 delivers an output when either the circuit 53 or the circuit 52 delivers its output. The output from the circuit 55 is used as a signal for energizing a red lamp R. An inverter 56 is provided to invert the information output from the memory means 36. The information output from the memory means 36 is applied to an in hibit circuit 57 as an input to the latter, while the information output from the memory means 32 is applied to the inhibit circuit 57 as an inhibit input to the latter. The output from the inverter 56 is applied to an inhibit circuit 56 as an input to the latter, while the information output from the memory means 32 is applied to the inhibit circuit 56 as an inhibit input to the latter. The flicker signal applied to the terminal 54 and the output from the circuit 57 are adapted to be applied to an AND-circuit 59 so that the AND-circuit 59 delivers an output when both these inputs are simultaneously applied thereto. The outputs from the

circuits

59 and 56 are adapted to be applied to an Oil-circuit 66 so that the OR-circuit 6U delivers an output when either the circuit 5'9 or the circuit 56 delivers its output. The output from the OR-circuit 66 is used as a signal for energizing a green lamp G. It will be understood that the outputs from the

circuits

55 and 60 are sequentially distributed by the distributor circuit 46 to display circuits L,,,, L,,,,, L in a manner as described with reference to FIG.

As will be apparent from the above description given with reference to FIG. 5, the information output, that is, the new information delivered from the memory means 32 must be il in order to derive an output from the circuit 55. A continuous output is delivered from the circuit 52 when the information output, that is, the old information delivered from the memory means 36 is l," and a discontinuous output is delivered from the circuits 5ll and 53 when the old information delivered from the memory means 36 is On the other hand, an output is derived from the circuit 66 when the information output from the memory means 32 is ll." A continuone output is delivered from the circuit 56 when the information output from the memory means 36 is 6," and a discontinuous output is delivered from the circuits 5? and 59 when the information output from the memory means 36 is l."

Therefore, the display by the display lamps R and G can be summarized as follows:

Red lamp R continuously energized: The equipment is continuously in its on" state.

Red lamp R discontinuously energized: The equipment is presently in its on state as a result. of a change from the "off state to the on" state.

Green lamp G continuously energized: The equipment is presently in its of state.

Green lamp G discontinuously energized: The equipment is presently in its off" state as a result of a change from the on" state to the of state.

In the embodiment shown in FIG. 5, two display lamps are em ployed for each equipment. It is therefore unnecessary to vary the period offlickering.

While the two embodiments described above are designed to store new and old information, the old information is not necessarily required and an arrangement may be made in which, in lieu of the old information, any difference between the old information and new information. may be detected and such a difference may be stored. An embodiment based on this manner of operation is shown in FIG. 6.

Referring to FIG. 6, the newest information coming from each controlled station is sequentially stored in a memory means 32 as in the embodiment shown in FIG. l. A noncoincidence detection circuit 611 compares the new information to be stored in the memory means 32 with the old information stored in the memory means 32 in the preceding cycle and delivers an output when the new information does not coincide with the old information. A terminal 37 similar to that described with reference to FIG. 1 and the circuit 611 are connected to an OR-circuit 62 so that the OR-circuit 62 delivers an output when a signal comes from either the terminal 37 or the circuit 6ll. An inhibit gate 63 has the same purpose and function as those of the inhibit gate 34 described with reference to FIGS. Ia and 1b. An OR-circuit 64 delivers an output when either the gate 63 or the circuit 61 delivers its output. A flicker signal is supplied to a terminal 56 which is connected to an AND-circuit 65, while a memory means 36 is also connected to the AND-circuit 65. Thus, the AND-circuit 65 delivers an output when both the flicker signal supplied from the terminal 54 and the output from the memory means 36 are simultaneously applied thereto. The output from the circuit 65 and the information output from the memory means 32 are applied to an AND-circuit 66. The output from the circuit 65 is also applied to an inhibit circuit 67 as an input to the latter, while the information output from the memory means 32 is also applied to the inhibit circuit 67 as an inhibit input to the latter. An inverter 68 is provided to invert the information output from the memory means 32. The information output from the memory means 36 is applied to an inhibit circuit 69 as an inhibit input to the latter, while the information output from the memory means 32 is applied to the inhibit circuit 69 as another input to the latter. The information output from the memory means 36 is also applied to an inhibit circuit 70 as an inhibit input to the latter, while the output from the inverter 66 is applied to the inhibit circuit 70 as another input to the latter. The outputs from the

circuits

66 and 69 are applied to an ()R-circuit 711. The outputs from the

circuits

67 and 70 are applied to an OR-circuit 72. The output; from the circuit '7ll is used as a signal for energizing a red lamp R, while the output from the circuit 72 is used as a signal for energizing a green lamp G. It will be understood that the outputs from the circuits 71 and 72 are sequentially distributed to display circuits L,,,, L, -L,,,,,, by the distributor circuit 46.

The embodiment shown in FIG. 6 is basically different from the embodiments shown in FIGS. Ila, lb and 5 in respect of the memory contents of the memory means 36. More precisely, in the embodiments shown in FIGS. lla, lb and 5, the memory means 36 stores the old information which was received in the preceding cycle and is older than the new information stored in the memory means 32. However, in the embodiment shown in FIG. 6, the new information to be stored in the memory means 32 is compared with the information which has already been stored in the preceding cycle and. is delivered from the memory means 32 as an output therefrom, and a signal representing whether or not the new information coincides with the old information is stored in the memory means 36. In

inun't lrluu the illustration, an output is delivered from the circuit 61 when the new information does not coincide with the old information and such output is stored in the memory means 36. However, a different arrangement may be made so that the circuit 61 delivers an output when the new information coincides with the old information. In such a case, the control circuit arrangement for the circuits 65 to 72 must be varied accordingly. Therefore, by judging the combination of the outputs from the memory means 32 and 36, it is possible to know the existing state of the equipment and the presence or absence of a change in the state of the equipment. For example, when the information output from the memory means 32 is and the information output from the memory means 36 is l, an output is delivered from the circuit 72 through the circuit 67 so that the green lamp G is discontinuously energized thereby to show the fact that the specific equipment is presently in its off" state due to a change from the on" state to the of state. Although a more detailed description will not be given herein, it should be noted that the type of display in the embodiment shown in FIG. 6 is the same as that employed in the embodiment shown in FIG. 5. It will thus be understood that the memory contents in the memory means 36 can be reset to stop the discontinuous display in response to the application of the signal to the terminal 37.

It will be apparent from the foregoing description that, in the present invention, memory means are not provided in a 1:1 relationship with each equipment in the controlled stations, but a few memory means are provided to store a series of serial information in a predetermined order. Therefore, a system of very small size can be obtained in accordance with the present invention. A remarkably excellent effect may be obtained when, for example, memory means of the circulating or serial type employing therein MOS-integrated circuits are used.

According to the present invention in which the memory is sequentially and serially led out, it is necessary to distribute the contents of the memory to respective display circuits for the display on lamps, and each display circuit must hold the preceding information therein until the succeeding information is given. However, the circulating speed of memory means is very high and memory means may only hold the information for a very short time. Thus, the system according to the present invention is sufficiently small in size compared with the prior system employing memory means in the form of relays or the like despite the fact that the inventive system includes therein the distributor circuit and information-holding circuits.

The serial delivery of information according to the present invention is advantageous in the case in which information obtained is led into a data logger so that it is processed, judged and typed out for display or in the case in which such information is introduced into an electronic computer for determining the way of processing thereof in conjunction with other conditions. in such a case, the output from the circuit 45 and the signals delivered from the

circuits

21, 22 and 23 may only be led into the distribution circuit 46 in the embodiment shown in FIGS. la and lb. Thus, the connection between the remote supervisory system and the data logger or electronic computer can very simply be effected. This will be self-evident from the fact that a number of connection wires corresponding to the number of equipment are required in the prior system in which memory means in the form of relays or the like are provided in a 1:1 relationship with each equipment. Further, the serial delivery of information is very advantageous in the case in which the skeleton of a power plant is displayed on a cathode-ray tube and the state of each equipment is displayed on the cathode-ray tube in superposed relation with the skeleton. In such a case too, the number of connection wires is quite small in accordance with the present invention.

The present invention is in no way limited to the embodiments described above and many changes and modifications may be made therein. For instance, the information from a controlled station need not be continuously transmitted and all that is needed is reception of correct information. Although one memory means 32 and one memory means 36 are provided in the control station for the storage of all the information, such memory means may be disposed in each of the controlled stations. This arrangement is convenient in that the controlled station circuit 23 can be eliminated, the circulation cycle of the memory means can be shortened and the display can be renewed in each controlled station.

Furthermore, three memory means, that is, a memory means for storing the new information, a memory means for storing the old information and a memory means for'storing the coincidence or noncoincidence between the new information and the old information may provided. This arrangement is advantageous in that the display corresponding to the old information can readily be obtained where necessary. The illustrated embodiments refer to the circulating or serial memory means in which the circulation takes place in response to application of a shift pulse. However, it will be understood that such a shift pulse is unnecessary when the memory means is a delay line memory. In such a case, a predetermined clock pulse corresponding to the shift pulse in the illustrated embodiments may be selected and the clock pulse may be obtained from, for example, a magnetic drum.

What is claimed is:

1. A remote supervisory system for supervising an operating condition of a plurality of pieces of equipment located in a controlled station comprising receiving means for cyclically and continuously receiving individual signals having values representing respective states of an operating condition of each piece of equip ment being supervised,

memory means for storing said received signals serially and cyclically, including at least a first serial memory for stor ing the latest cycle of said individual signals received and a second serial memory for storing the corresponding in dividual signals of a preceding cycle representing the same operating condition of the respective pieces of equipment,

means for controlling the application of the received individual signals to said first serial memory,

display means for generating visual indications representing the correlation between the values of the signals stored in corresponding positions in said first and second memories, and

timing means for controlling the application of said signals to said memory means in predetermined time slots of a repetitive time frame, coincidence means connected to the outputs of said first and second memories for providing an output only upon detecting coincidence between signals received from corresponding time slots of said first and second memories, and control means for actuating said display means in one manner in response to an input from said coincidence means and another manner in response to the absence of an output from said coincidence means,

said display means including an indicator element for each respective piece of equipment being supervised and distributor means for selectively connecting each indicator element to said control means in accordance with the timing of said timing means.

2. A remote supervisory system as defined in claim I, wherein said first and second memories are circulating memories.

3. A remote supervisory system as defined in claim 2, wherein said first and second memories each include a dynamic shift register.

4. A remote supervisory system as defined in claim 1, wherein said indicator elements are lamps.

S. A remote supervisory system as defined in claim 4, wherein said control means includes a capacitor associated with each lamp for storing a signal capable of energizing said lamp for a predetermined period corresponding to the cycle time of said memory means.

HllilZJ 0790 6. A remote supervisory system as defined in claim ll, wherein said control means includes first gating means for generating a first frequency signal in response to receipt of no output from said coincidence means along with a first signal value from said first memory, second gating means for generating a second frequency signal in response to receipt of no output from said coincidence means along with a second signal value from said first memory, and third gating means for generating a DC signal in response to receipt of an output ill

Claims

1. A remote supervisory system for supervising an operating condition of a plurality of pieces of equipment located in a controlled station comprising receiving means for cyclically and continuously receiving individual signals having values representing respective states of an operating condition of each piece of equipment being supervised, memory means for storing said received signals serially and cyclically, including at least a first serial memory for storing the latest cycle of said individual signals received and a second serial memory for storing the corresponding individual signals of a preceding cycle representing the same operating condition of the respective pieces of equipment, means for controlling the application of the received individual signals to said first serial memory, display means for generating visual indications representing the correlation between the values of the signals stored in corresponding positions in said first and second memories, and timing means for controlling the application of said signals to said memory means in predetermined time slots of a repetitive time frame, coincidence means connected to the outputs of said first and second memories for providing an output only upon detecting coincidence between signals received from corresponding time slots of said first and second memories, and control means for actuating said display means in one manner in response to an input from said coincidence means and another manner in response to the absence of an output from said coincidence means, said display means including an indicator element for each respective piece of equipment being supervised and distributor means for selectively connecting each indicator element to said control means in accordance with the timing of said timing means.

2. A remote supervisory system as defined in claim 1, wherein said first and second memories are circulating memories.

5. A remote supervisory system as defined in claim 4, wherein said control means includes a capacitor associated with each lamp for storing a signal capable of energizing said lamp for a predetermined period corresponding to the cycle time of said memory means.

6. A remote supervisory system as defined in claim 1, wherein said control means includes first gating means for generating a first frequency signal in response to receipt of no output from said coincidence means along with a first signal value from said first memory, second gating means for generating a second frequency signal in response to receipt of no output from said coincidence means along with a second signal value from said first memory, and third gating means for generating a DC signal in response to receipt of an output from said coincidence circuit along with said first signal value from said first memory, the outputs of said first, second and third gating means being connected to said distributor means.

7. A remote supervisory system as defined in claim 1, wherein a gate interconnects the input of said first memory to the input of said second memory, said gate havIng a control input for selectively gating data applied to said first memory also to said second memory.