US3641556A - Character addressing system - Google Patents

Character addressing system Download PDF

Info

Publication number
US3641556A
US3641556A US837790A US3641556DA US3641556A US 3641556 A US3641556 A US 3641556A US 837790 A US837790 A US 837790A US 3641556D A US3641556D A US 3641556DA US 3641556 A US3641556 A US 3641556A
Authority
US
United States
Prior art keywords
character
deflection
resolution
signals
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US837790A
Other languages
English (en)
Inventor
Richard A Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of US3641556A publication Critical patent/US3641556A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/08—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system
    • G09G1/10—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system the deflection signals being produced by essentially digital means, e.g. incrementally

Definitions

  • ..340/324 A 315/18 characters be generated e divided into two groups [51] "Goa 3/14 representing the two directions of deflection.
  • a first group 5 Field of Search 340/324 24 A. 315/1 2 provides a linear region in which uniform deflection steps are 178763 3 generated for each signal increment, while a second group provides a nonlinear region in which varied deflection incre- [56] Reerem Cited ments are generated for each signal increment.
  • the nonuniform regions provide higher resolution in those areas where UNITED STATES PATENTS curves nonnally occur and less resolution in the remaining areas thus providing higher character resolution in specified 3,1 19,949 1/ 1964 Greatbatch et a].
  • the nonuniform deflection 3,422,304 1/1969 is obtained from associated decoders through a weighted ad- 3479453 11/1969 dressing system which provides nonuniform current increments independent of the digital data input.
  • FIG. 3b I IG-3c- CHARACTER ADDRESSING SYSTEM BACKGROUND OF THE INVENTION 1.
  • the invention relates to a display device'and more particularly to an improved character generatordeflection system suitable for use with cathode-ray tubes for displaying the generated characters.
  • digital signals indicative of characters to be generated on a CRT display are decoded into analog signals suitable for'deflecting the beam of the cathode-ray tube.
  • the present invention utilizes a linear deflection for onecoordinate of the character (the horizontal), and a nonlinear deflection for the second coordinate of the character. This nonlinear deflection is obtained by weighting the individual decoded deflection signals such that smaller deflection units aflording higher resolution are provided at those areas where the curved segments of most characters tend to occur. Those areas of the matrix not normally associated with curved characters utilize higher deflection units resulting in greater spacing without character degradation.
  • a primary object of the present invention is to provide an improved character generator circuit.
  • Another object of the present invention is to provide an improved deflection system for improving the resolution of specific character areas by modifying the deflection control to provide a nonuniform deflection in one of the character coordinates.
  • Another object of the present invention is to provide an improved character generator'having a linear and nonlinear addressable grid system designed to improve the aesthetic appearance of characters.
  • FIG. 1 illustrates in block logical form a preferred embodiment of the present invention.
  • FIG. 2a illustrates in schematic form a binary weighted decoder shown in block form in FIG. 1.
  • FIG. 2! illustrates in schematic form a nonlinear weighted decoder shown in block form in FIG. 1.
  • FIG. 3 illustrates character display formats
  • FIG. 3a illustrates a character generated by using the conventional addressable grid matrix.
  • FIGS. 3b and 3c illustrate characters generated in accordance with the addressable matrix of the present invention.
  • binary coded signals are applied from a data source which might comprise, for example, a data processor such as Central Processing Unit 11 through input lines 21 and 23 to the X input register 25 and the Y input register 27, respectively.
  • a data byte comprising six binary bits is used for each character stroke, three bits for the horizontal deflection and three hits for the vertical deflection.
  • the preferred embodiment of the present invention utilizes an 8X8 character matrix which can be provided by three bits for each coordinate, each three-bit signal designating the end point of the vector.
  • the contents of the X and Y input register are transferred through conductor pairs labeled X1, X2, X3 and Y1, Y2 and Y3, with X1 and Y1 representing the lowest order binary bits, to the'X and Y Position Registers 33 and 35, respectively.
  • the preferred embodiment of the instant invention is described as operating in double-ended, push-pull configuration such that each binary designation utilizes separate lines to represent the l and 0 states.
  • the X and Y position registers 33 and 35 comprise count-up, countdown counters or registers which are incremented or decremented in accordance with the input signals applied from the associated input registers.
  • a +X signal on line 34 will increment Position Register 33 by one, a -X signal on line 36 will decrement the counter by one. While various count-up, countdown counters are known in the art, one preferred embodiment is shown in US. Pat. No. 3,403,286 (IBM Docket 16866009), Digital Cathode Ray Deflection System" filed by F. R. Carlock et al., Dec. 27, 1966. Since the present invention is directed only to character generation, the initial positioning for each character has been omitted as unnecessaryto an understanding of the present invention. However, either a separate deflection coil could be utilized to initially position the beam for character generation, oralternatively, the Xand Y position registers 33 and 35 could be large .enough to accommodate both the character position and individual stroke deflection signals.
  • the horizontal decoder 43 is a conventional binary weighted linear decoder in which uniform increments or decrements of current are provided for each positive of negative signal applied to the X position register 33.
  • the vertical decoder 45 in the preferred embodiment of the instant invention is a nonlinear decoder in which the digital addresses, when decoded, generate nonuniform incremental steps to provide higher resolution in the upper, lower and center areas and lesser resolution in the noncritical intermediate area as more fully described hereinafter.
  • the cumulative X signals on lines 47 and 49 from horizontal linear decoder 43 are transferred via lines 47 and 49 to their respective buffer transistors 51 and 53, respectively.
  • Buffer transistors 51 and 53 function to isolate the decoder output from the associated deflection drive circuits 55 and 57, respectively.
  • the output from the deflection drivers 55 and 57 are then applied to the horizontal yoke winding 59 of CRT 61.
  • the output from the vertical decoder 45 on lines 60 and 62 is applied through associated buffer transistors 63 and 65 and associated deflection drivers 67 and 69 to the vertical yoke winding 71 of CRT 61.
  • the grid 73 is maintained unblanked by means of intensity control circuit 75.
  • Intensity control circuits for maintaining a CRT beam in the unblarrked condition during character generation are well known in the art such that a block showing is considered to constitute adequate description.
  • one conventional method is to include an extra bit in the end point data for intensity control information.
  • FIG. 2a there is illustrated in block schematic form details of the horizontal linear decoder shown as block 43 in FIG. 1.
  • the decoder as shown is a double-ended decoder operating on three bits ranging from the lowest order bit XI through X2 and X3. Since the decoder operates in a push-pull fashion, a latch register comprising latch circuits 81, 83 and 85 is employed, each stage having binary l and outputs, the respective outputs of which in turn are connected to binary weighted resistors 87, 89 and 91 and 87, 89' and 91'.
  • Latch circuits are well-known components in a data processor, are similar to flip-flops or triggers except for timing considerations related to reversal of state.
  • the horizontal decoders provide uniform horizontal deflection increments for each input signal permutation. Since the characters or character segments may be generated either from left to right or right to left, depending on the specific character configuration, the decoder 43 responds to the output from the X position register 33 (Fig. l) which may be incremented or decremented in single steps heretofore described.
  • the nonlinear vertical decoder 45 utilized in the preferred embodiment of the invention is shown in block schematic fonn.
  • the three-bit coded signals for each character segment are applied to the appropriate latch register stages 93, 95 or 97, the individual outputs of which are connected to resistors 101, 103 and 105 and 101, 103 and 105'.
  • the vertical decoder stages are weighted in a ratio of 1:315 to reflect the expansion factor of l which has been added to the weighting values corresponding to the binary place values of 2 and 4. The weighting value corresponding to the place value of 1 has not been expanded.
  • the low order bit of decoder 45 is also designated as 4R, the next more significant bit as 4/3 R, and the most significant bit 4/5 R.
  • the relative ratio of the currents for the eight possible input combinations to the decoder is shown in decreasing binary increments in the table below, the tabulated coded values corresponding to those shown in Figures 3b and 30.
  • nonlinear decoder 45 are applied through associated conductors 60 and 62 to the vertical winding 71 of the magnetic yoke.
  • FIG. 3 there is illustrated a sequence of characters including one generated by the conventional rectangular grid and several characters generated in accordance with the preferred embodiment of the present invention, all characters being generated on an 8X8 matrix.
  • the character 5 is shown on an 8X8 coordinate matrix, eight segments representing the maximum resolution which can be achieved from a three-bit by three-bit word.
  • the numeral 5 has been selected as exemplary of problems associated with the conventional coordinate grid matrix. As shown thereon, and particularly at the normally curved center and lower portions of the figure, the limited resolution provides a very poor image quality such that the numeral 5" cannot be readily distinguished from the letter Further, purely from a human factors standpoint, the appearance of the character is undesirable.
  • One way and the conventional way of improving image quality is to increase the resolution of the available grid from 8X8 to some higher number depending on the degree of resolution desired.
  • this requires a larger word size, and the entire system including the input registers, the position registers, decoders, buffer and even the data processor transmitting the data bytes would all necessarily be larger to accommodate the larger word such that this solution from an economic standpoint is impractical.
  • FIG. 3 A practical solution for improving character quality is provided by the instant invention.
  • the drawings of FIG. 3 are not intended to indicate a precise character size, but are enlarged and exaggerated to identify the problem. However, the relative proportions correspond to characters generated by the instant invention.
  • FIGS. 3b and 30 there are shown several characters generated on a variation of an 8X8 matrix utilizing the principles of the instant invention. It will be noted that the upper lines of the matrix (111, the lower lines (000,001) each have areas of fine resolution and that a series of fine resolution lines are shown in the center portion (010, 011, 100, 101). However, both the intermediate lower (001 to 010) and intermediate upper (101 to 110) sections provide a relatively gross resolution in this area. However, it is apparent from FIGS.
  • a cathode-ray tube having beam deflection means and intensity control means
  • first and second decoder means for converting said video data into deflection signals
  • said first decoder means being adapted to produce uniformly weighted linear signals
  • a method for decoding digital signals each having a plurality of groups representing coordinates of display stroke end points of a character to be displayed with increased resolution comprising the steps of: p
  • Steps '1 through 6 for each digital signal representing a display stroke end point of a character to be displayed whereby said character has a high resolution concentrated in upper, medial, and lower regions, and has a lower resolution between said upper and said medial and between said medial and said lower regions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
US837790A 1969-06-30 1969-06-30 Character addressing system Expired - Lifetime US3641556A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83779069A 1969-06-30 1969-06-30

Publications (1)

Publication Number Publication Date
US3641556A true US3641556A (en) 1972-02-08

Family

ID=25275435

Family Applications (1)

Application Number Title Priority Date Filing Date
US837790A Expired - Lifetime US3641556A (en) 1969-06-30 1969-06-30 Character addressing system

Country Status (5)

Country Link
US (1) US3641556A (enExample)
JP (1) JPS4947702B1 (enExample)
DE (1) DE2029628C3 (enExample)
FR (1) FR2052385A5 (enExample)
GB (1) GB1294162A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3746913A (en) * 1971-12-22 1973-07-17 Ibm Cathode ray deflection system using field effect transistors

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147502U (enExample) * 1976-04-30 1977-11-09

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3119949A (en) * 1961-02-06 1964-01-28 Jr William H Greatbatch Television type selected raster lines display
US3165729A (en) * 1961-07-24 1965-01-12 Robert L Richman Crt display system having logic circuits controlled by weighted resistors in the deflection circuitry
US3335416A (en) * 1963-08-07 1967-08-08 Ferranti Ltd Character display systems
US3403286A (en) * 1966-12-27 1968-09-24 Ibm Digital cathode ray tube deflection system
US3422304A (en) * 1967-09-15 1969-01-14 Ibm Logic controlled deflection system
US3479453A (en) * 1965-01-04 1969-11-18 Xerox Corp Facsimile resolution improvement by utilization of a variable velocity sweep signal
US3491200A (en) * 1966-09-21 1970-01-20 United Aircraft Corp Variable scan rate high resolution image transmission system
US3497760A (en) * 1968-06-10 1970-02-24 Sperry Rand Corp Logical expansion circuitry for display systems
US3521241A (en) * 1967-01-03 1970-07-21 Ibm Two-dimensional data compression

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3119949A (en) * 1961-02-06 1964-01-28 Jr William H Greatbatch Television type selected raster lines display
US3165729A (en) * 1961-07-24 1965-01-12 Robert L Richman Crt display system having logic circuits controlled by weighted resistors in the deflection circuitry
US3335416A (en) * 1963-08-07 1967-08-08 Ferranti Ltd Character display systems
US3479453A (en) * 1965-01-04 1969-11-18 Xerox Corp Facsimile resolution improvement by utilization of a variable velocity sweep signal
US3491200A (en) * 1966-09-21 1970-01-20 United Aircraft Corp Variable scan rate high resolution image transmission system
US3403286A (en) * 1966-12-27 1968-09-24 Ibm Digital cathode ray tube deflection system
US3521241A (en) * 1967-01-03 1970-07-21 Ibm Two-dimensional data compression
US3422304A (en) * 1967-09-15 1969-01-14 Ibm Logic controlled deflection system
US3497760A (en) * 1968-06-10 1970-02-24 Sperry Rand Corp Logical expansion circuitry for display systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3746913A (en) * 1971-12-22 1973-07-17 Ibm Cathode ray deflection system using field effect transistors

Also Published As

Publication number Publication date
JPS4947702B1 (enExample) 1974-12-17
GB1294162A (en) 1972-10-25
DE2029628C3 (de) 1978-06-01
DE2029628A1 (de) 1971-01-14
DE2029628B2 (de) 1977-10-06
FR2052385A5 (enExample) 1971-04-09

Similar Documents

Publication Publication Date Title
US4442503A (en) Device for storing and displaying graphic information
CA1140679A (en) Complex character generator
US4158838A (en) In-raster symbol smoothing system
US3771155A (en) Color display system
US4217577A (en) Character graphics color display system
US3699531A (en) Digital data selection and display system
US3400377A (en) Character display system
EP0098868A1 (en) Color display device controller.
US3624634A (en) Color display
US3325803A (en) Deflection control circuit
US3952296A (en) Video signal generating apparatus with separate and simultaneous processing of odd and even video bits
US3735383A (en) Display apparatus utilizing cathode ray tubes
US4677575A (en) Arrangement to generate different figures in a computer controlled presentation system on a screen
US3955189A (en) Data display terminal having data storage and transfer apparatus employing matrix notation addressing
JP2761890B2 (ja) 線発生装置及びディスプレイ装置
US4309700A (en) Cathode ray tube controller
US4563677A (en) Digital character display
JPS5837685A (ja) 高分解能の図形平滑化
US3587083A (en) Character generation and display system
US3329947A (en) Electronic character generator
US3641556A (en) Character addressing system
US3335415A (en) Digital display
US4146877A (en) Character generator for video display
US4205309A (en) Character generator
US4231032A (en) Variable accuracy trend graph display apparatus