US3638035A

US3638035A - Primary and secondary shunt paths for dissipating an electrical charge

Info

Publication number: US3638035A
Authority: US
Inventors: John N Murphy; Merle L Bowser
Original assignee: US Department of the Interior
Current assignee: US Department of the Interior
Priority date: 1971-03-23
Filing date: 1971-03-23
Publication date: 1972-01-25
Anticipated expiration: 1989-01-25

Abstract

A permissible blasting machine employs a capacitive discharge circuit for electrically detonating an explosion in a hazardous environment. Protective circuitry prevents capacitor discharge until full charge is reached. After detonation, redundant circuitry dissipates any charge remaining in the circuit. A failure of the dissipating circuitry disables the discharge system.

Description

United States Patent [is] 3,638,035 Murphy et al. 14 Jan. 25, 1972 [54] PRIMARY AND SECONDARY SHUNT 1 References Cited PATHS FOR DISSIPATING AN UNITED STATES PATENTS ELECTRICAL CHARGE 3,397,323 8/1968 Hirsch ..307/l41 [72] In entors: John N. Murphy, Pittsburg M r 3,424,924 1/1969 Leisinger et al. .317/80 X Bethel Park, both Of P 3,541,393 1 H1970 Diswood ..3 17/80 [73] Assignee: The United States of America as r E A D 6 tdbt zmay xamner-.. ll'lfl fipresen e y he secretary of the Inter Attorney-Ernest S. Cohen and Albert A. Kashinski [22] Filed: Mar. 23, 1971 [57] ABSTRACT [21] App1.No.: 127,112 A permissible blasting machine employs a capacitive discharge circuit for electrically detonating an explosion in a hazardous environment. Protective circuitry prevents capaci- [52] U.S.Cl. ..307/14l,1O0/70.2R,313Zgg, tor discharge um full charge is reached After detonation, redundant circuitry dissipates any charge remaining in the circuit. A failure of the dissipating circuitry disables the 51 Int. Cl ..F42d 5/00 discharge System. [58] Field ofSearch l02/70.2 R; 317/80; 320/1;

8 Claims, 3 Drawing Figures MERLE L. BOWSEI? M 5@&

BY W4.

ATTORNEYS PAENTH) JAN sum 2 or 3 BACKGROUND OF THE INVENTION In underground mines an electrical charge is commonly used to detonate explosives. After a detonator ignites, a short time, which is a function of the delay period of the detonator, lapses before the explosion occurs. To prevent secondary explosions of gases and fine combustible particles, it is necessary to effectively quench the electrical charge within this short lapse between ignition and explosion. US. Bureau of Mines Schedule 16E requires that the voltage across the terminals of an electrical blasting machine be reduced to a level precluding accidental post firing ignition within milliseconds after initial detonating contact is made. A device operating within the 15 millisecond limitation is classified as a permissible blasting machine.

Because of extreme hazards incident to underground blasting, operating safety is a primary consideration in the design and use of permissible blasting machines. Close scrutiny of new designs by the Bureau of Mines safeguards operators of permissible machines in proper working order operating within design limitations. Yet, hard use under unfavorable conditions often deteriorates the machines, resulting in unsafe operation. With prior permissible blasting machines there is no assurance that the charge quenching circuitry is functioning properly, and no indication of potentially unsafe operation. To overcome this defect of the prior art, this invention was made.

SUMMARY OF THE INVENTION Our invention is a permissible blasting machine for safely detonating explosions in hazardous atmospheres. To provide 1 the required 15 millisecond period. As a backup, a second shunt circuit activates shortly afterward, again within the 15 millisecond period. If sufficient current passes through the secondary shunt due to a defect in the primary shunt, the entire blasting machine is automatically disabled.

One potential hazard in operating a blasting machine is the possibility of detonating only a fraction of the total number of detonators employed. With the high number of detonators our machine is capable of detonating, this possibility becomes extremely undesirable. A common cause of failure to initiate all detonators is the discharge of the energy storage capacitors before full charge is reached. To preclude this possibility, our invention employs a lookout circuit which prevents firing of the blasting machine until the capacitors are fully charged. These and other features of our invention result in a safe and efficient machine for underground blasting.

Therefore, one object of our invention is a blasting machine with redundant shunt circuits for removing a voltage from a load within a predictable period.

Another object of our invention is a blasting machine which is automatically disabled if an operating defect occurs.

Another object of our invention is a blasting machine in which firing is prevented until sufficient charge for complete detonation is available.

These and other objects of our invention are evident in this specification and drawing.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic detonation circuit of a blasting machine.

FIG. 2 is a schematic timing circuit of a blasting machine.

FIG. 3 is a schematic SCR drive circuit of a blasting machine.

DESCRIPTION OF THE PREFERRED EMBODIMENT The detonating circuit 10 of a permissible blasting machine is shown in FIG. 1. To energize a series of electrical detonators, represented by a resistor R, between terminals T, and T,, i

an electrical current from a battery 12 first charges two series capacitors C, and C in parallel with R,. During charging, current flow through the detonators is prevented by a silicon-controlled rectifier SCR, in series with R,. When the detonating circuit is fired, a gate signal permits SCR, to conduct current, enabling C, and C to discharge through the detonator circuit R, with sufficient energy for detonating an explosion.

To produce the high voltage required for initiating detonators R,, battery 12, through a normally open charging switch S is connected in series with the medium voltage inputs of a medium-to-high-voltage DC converter 14. High-voltage DC appearing at the converter output terminals is fed to capacitors C, and C through a limiting resistor R and a buffer diode D,. Two large resistors R,, and R,, in parallel with C, and C, respectively, serve as bleeders and a voltage divider to improve capacitor charging performance.

In actual operation of detonating circuit 10, capacitors C, and C, are charged by closing charging switch S Discharge, or firing, is controlled by a lockout circuit incorporated in the detonator circuit. The lockout circuit prevents firing until C,

and C are fully charged, insuring adequate firing potential for detonators R,, and preventing hazardous misfires. Indirectly, through a timing circuit, a unijunction transistor 0, in the lockout circuit controls the gate signal to SCR,. Four zener diodes Z,-Z., in series with a neon glow lamp NE, are joined in parallel with series capacitors C, and C with one diode Z, between the glow lamp and the ground terminal of battery 14. Between the glow lamp and Z,, the emitter of unijunction transistor '0, is connected through a normally open firing switch S When C, and C are sufficiently charged, the neon glow lamp conducts, and voltage to trigger Q, appears at S The neon glow lamp acts both as a lockout to prevent firing with insufficient charge on the capacitors, and as a visual indicator that the circuit is ready to trigger.

Driving potential for transistor Q, is derived from a lowvoltage terminal V between a resistor R and a zener diode Z in series with battery 12 and switch S The zener diode regulates the potential between V,, and the battery ground to a stable level suitable for unijunction operation. Because switch S must be closed to produce an output at V, triggering of the unijunction is prevented unless charging potential appears across capacitors C, and C This construction operates as an additional safeguard against misfiring of the detonator circuit.

To fire the detonator circuit, switch S is first closed until lamp NE, glows, indicating that firing potential has been reached across C, and C Firing switch S is then closed to trigger transistor 0, and ultimately gate SCR,. With low-voltage terminal V,, connected to one base lead, triggering of Q, causes a signal to appear at the other base lead 16 and at an output terminal T,. A resistor R in parallel with a capacitor C carries this signal to ground and provides a time constant suffrcient to prevent firing by spurious signals appearing at terminal T From terminal T, the firing signal is fed to a timing circuit for controlling the gate signal input to SCR, to regulate buildup and reduction of power consumption in R,.

US. Bureau of Mines Schedule 16E requires that the voltage across terminals T, and T of the electrical blasting machine be reduced to a level precluding accidental post firing ignition within 15 milliseconds after initial detonating contact is made. Initial detonating contact occurs when, at a time t SCR, receives a gating pulse from the timing circuit through a terminal T Inresponse to the gate pulse, SCR, conducts, discharging capacitors C, and C through R,. Within 15 milliseconds after initiating the discharge, all voltage between terminals T, and T must be removed. For this purpose a small primary shunt resistor R in parallel with R,, and also with C, and C is used to provide a short time constant for discharging the capacitors.

Shortly after gating pulse t reaches SCR,, a second gating pulse t is transmitted from the timing circuit, through a terminal T to a second silicon-controlled rectifier SCR which completes the primary shunt circuit in series with R After detonators R have fired, the gating pulse t, opens SCR to rapidly dissipate through R, any charge remaining across C and C A diode D across terminals T and T provides a circuit path for dissipating any residual inductive or capacitive potential remaining across T and T Within a short time the entire charge on capacitors C and C is safely dissipated.

Safe operation of the electrical blasting machine requires that the potential across capacitors C, and C be dissipated without fail shortly after initiating capacitor discharge. With R and SCR, as the only shunt path available for this purpose, any defect in these elements has potentially catastrophic consequences. To preclude this result, a secondary shunt path, including a resistor R in series with a silicon-controlled rectifier SCR is provided in parallel with R, and SCR to act as a backup. Shortly after gating pulse t reaches SCR to shunt current through R a third gating pulse t passes from the timing circuit, through a terminal T to gate SCR Under normal conditions, little or no current flows through this path. But if the primary shunt circuit fails to operate, the secondary circuit reduces the voltage across terminals T and T within the required millisecond period. To disable the charging circuit if the primary shunt fails to operate, a fuse F, is connected between the primary and secondary shunts. If the primary shunt fails, dissipation of the capacitor charge in R causes sufficient current flow to blow F preventing capacitor recharge until the defect is corrected. In parallel with the fuse, a neon glow lamp NE, in series with a large resistor R illuminates after the fuse blows to indicate the defective condition.

A timing circuit suitable for supplying to the detonator circuit the three precisely spaced signals t -t is shown in FIG. 2. At the left side of the timing circuit the firing signal from the unijunction transistor Q, in the lockout circuit shown in FIG. 1 is input at terminal T From T the firing signal passes simultaneously to three independent time delay generators 18-22. Timing is generated by integrated circuit (IC) logic chips which respond to the trigger signal from the unijunction. From terminal T the trigger signal travels through a conductor 24 to generator 18, where it is input to a logic chip IC,. Upon receiving the signal, the logic chip initiates charging of a capacitor C in series between IC, and a resistor R The free end of R is joined to low-voltage terminal V,,, derived from FIG. 1, to bias a second logic chip IC connected by a conductor 26 between C, and R When the voltage across C overcomes the bias, the voltage input at conductor 26 is transmitted by IC to a conductor 28. From output conductor 28 this voltage is fed forward to an integrated circuit amplifier [C and back to IC through a conductor 30. At IC the signal resets the timing generator. Amplifier 1C provides isolation and signal gain, delivering a timing pulse t through a capacitor C to an output tenninal T-,.

In timing generators and 22 additional logic chips are employed to provide variable time delay. To obviate unnecessary repetitious description, elements with corresponding functions in the three generators are similarly numbered. From terminal T the trigger signal travels through a conductor 32 to generator 20, where it is input to a logic chip IC,. Upon receiving the signal, the logic chip initiates charging of a capacitor C in series between IC a fixed resistor R and a variable resistor R The free end of R is joined to low-voltage terminal V to bias a logic chip IC with inputs connected between C, and R for operation in a manner similar to [C in generator 18. While the delay time of generator 18 is fixed, however, variable resistor R enables variation of the charging time constant of C so that the delay between receipt of the firing signal at IC, and transmission of a pulse from IC through an output conductor 34 can be precisely regulated. From conductor 34 the output pulse of IQ, is fed back through a conductor 36 to reset IC.,, and forward to an intermediate logic chip 1C At the output of [C a capacitor C in series with a grounded resistor R receives the signal for input,

through a conductor 24 between C and R to a series of elements duplicating timing generator 18. Ultimately a control pulse arrives at a timing output terminal T at a time I, shortly after the initial timing pulse t In a similar manner a third timing pulse 1 is produced at output terminal T in generator 22 shortly after pulse t,.

From terminals T-,T in FIG. 2 the three timing pulses are fed to an SCR drive circuit shown in FIG. 3. Because SCR,SCR shown in FIG. 1, require a higher gate current than available at the timing circuit output, an intermediate gate drive stage 40 is required for raising each timing pulse to the required level. Three similar circuits, one for each timing pulse, are employed for this purpose. Corresponding circuit elements in each gate circuit are shown with similar reference numerals.

In gate drive stage 40 a medium driving voltage is input to a conductor 42 from a terminal V connected to switch S as shown in FIGS. 1 and 3. Between conductor 42 and ground are connected a cutoff resistor R and a capacitor C Under steady-state conditions the voltage V is stored on C Between R and C is connected the anode of a silicon-controlled rectifier SCR When a timing pulse, t for example, appears at the associated input terminal, T in this case, it is fed to the gate of SCR., by a conductor 44. The timing pulse gates the SCR, causing current to flow from C through the SCR cathode to the appropriate input terminal in the detonator circuit, terminal T in the case of timing pulse t As C discharges the voltage across R rises, preventing continuous current flow through the SCR. Between the cathode of SCR and the detonator input terminal the gating current passes through a decoupling capacitor C and a diode D which prevents feedback between the individual SCRs in the gate drive and detonator circuits. A gate holdoff resistor R between the cathode and gate of SCR provides a gate to cathode current path while preventing spontaneous gating. Gate holdoff resistors R between the detonator circuit SCR gates and ground perform a similar function. A resistor R passing from between C and D to ground, dissipates residual voltage across D when the detonator gating pulse ceases. In this way the detonator gating pulses to SCR,SCR are held to a short predictable duration.

As is apparent in the above description, our invention enables safe and efficient blasting in hazardous atmospheres. To exemplify the safety features of the invention, the basic operation will now be summarized. First, switch S is closed to charge energy storage capacitors C and C Until glow lamp NE illuminates, the lockout circuit prevents discharge so that the hazards of firing with insufficient voltage are avoided. When the capacitors are fully charged NE, illuminates, indicating that the detonator circuit is prepared for firing, and also making voltage available at the firing switch 8,. Firing switch S is then closed. Then, only if charge switch S remains closed, unijunction Q triggers, producing a firing signal at terminal T and simultaneously activating timing generators 18-22. In a short time a first timing pulse t is transmitted from generator terminal T-, to gate SCR in the detonator circuit and cause discharge of C, and C through the detonators R Shortly afterward, a second timing pulse t, gates SCR to provide a primary shunt path around R Then, within the 15 millisecond allowable period, a third timing pulse gates SCR in the secondary shunt path around R If, for some reason, the primary shunt fails to operate, current flow through the secondary shunt blows fuse F disabling the detonator circuit and illuminating glow lamp NE to signal the defect.

Although construction of our invention is not limited to a particular circuit, the following values of circuit elements were used effectively in the preferred embodiment:

SCR,-SCR ClOfiBl D,D, PSOSZD Z,-Z IN305 l B Z, lN30l6B Z lN704 IC, l/2MC788 l-2.4.3.6 l/4-MC7l7 CAPACITORS C,,C, 240 p.f., 450 v. DC C, st, 5v. DC C,,C. l fl, 3v. DC C, lp.f., 20v. DC C, 3,300 pf., 50v. DC

RESISTORS (in ohms) R, Indefinite R, IOK 2 watt R,,R, lOOK, 1 watt R, 430, 1 watt R,. R,,-R,, IK, Vnvat! 1- s l0, watt 2M, 1 watt m 5K. 'riiwatt R 499, %watt R 1K, Bourns 3067P-l-l03 R 10K, iwatt R I 50K, Vtwatt MISCELLANEOUS NE DIALCO 249-7840-1431-504 NE, DlALCO 249-7846-1433-504 F, %A 3A6 SB B, 2 Eveready batteries IOIBHSOOT Converter Advance Power Supply G. 24v., DC to l,000v.,. DC 100 ma. converter,

While our invention is described as a specific preferred embodiment, with specific circuit parameters given in addition, equivalent designs and elements are expected. For this reason, the scope of the invention is limited only by the following claims:

We claim:

1. An apparatus for applying an electrical charge across a pair of terminals and for removing the charge within a short, definite duration comprising:

a capacitive discharge circuit,

means for storing an electrical charge in the capacitive discharge circuit,

a pair of terminals,

means for applying the electrical charge across the pair of terminals at a time t primary shunt means for applying a first low-resistance shunt across the capacitive discharge circuit at a later time t to rapidly dissipate the electrical charge,

secondary shunt means for applying a second low-resistance shunt across the capacitive discharge circuit at a still later time to rapidly dissipate any remaining electrical charge.

2. An apparatus as claimed in claim 1, further comprising:

means for preventing the application of the charge across the pair of terminals until a specific quantity of charge is stored in the capacitive discharge circuit.

3. An apparatus as claimed in claim 1, further comprising:

means for preventing storage of charge in the capacitive discharge circuit after a predetermined value of current flows in the secondary shunt means.

4. An apparatus as claimed in claim 2, further comprising:

5. An apparatus as claimed in claim 1 in which:

the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with the pair of terminals and gated by the first timing generator,

the primary shunt means includes a second timing generator activated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator, and

the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third siliconcontrolled rectifier in series with the second low-resistance shunt and gated by the third timing generator.

6. An apparatus as claimed in claim 2 in which:

' the means for applying includes a semiconductor switch, a

first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with the pair of terminals and gated by the first timing generator,

the primary shunt means includes a second timing generator actuated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator,

the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third siliconcontrolled rectifier in series with the second low-resistance shunt and gated by the third timing generator, and

the means for preventing the application of the charge includes means for regulating a trigger voltage available for actuating the semiconductor switch in proportion to the amount of charge stored in the capacitive discharge circuit.

7. An apparatus as claimed in claim 3 in which:

the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with a pair of terminals and gated by the first timing generator,

the means for preventing the application of the charge in: cludes means for regulating a trigger voltage available for actuating the semiconductor switch in proportion to the amount of charge stored in the capacitive discharge cir cuit, and

the means for preventing storage of charge includes a circuit interrupter connected between the means for storing charges on the capacitive discharge circuit and the secondary shunt means on one side, and the means for applying and the primary shunt means on the other side, in such a manner that all charge stored in the capacitive discharge circuit and all charge dissipated in the secondary shunt means passes through the circuit interrupter.

8. An apparatus as claimed in claim 4 in which:

charge on the capacitive discharge circuit and the secondary shunt means on one side, and the means for applying and the primary shunt means on the other side, in such a manner that all charge stored in the capacitive discharge circuit and all charge dissipated in the secondary shunt means passes through the circuit interrupter.

Claims

1. An apparatus for applying an electrical charge across a pair of terminals and for removing the charge within a short, definite duration comprising: a capacitive discharge circuit, means for storing an electrical charge in the capacitive discharge circuit, a pair of terminals, means for applying the electrical charge across the pair of terminals at a time t0, primary shunt means for applying a first low-resistance shunt across the capacitive discharge circuit at a later time t1, to rapidly dissipate the electrical charge, secondary shunt means for applying a second low-resistance shunt across the capacitive discharge circuit at a still later time t2, to rapidly dissipate any remaining electrical charge.

2. An apparatus as claimed in claim 1, further comprising: means for preventing the application of the charge across the pair of terminals until a specific quantity of charge is stored in the capacitive discharge circuit.

3. An apparatus as claimed in claim 1, further comprising: means for preventing storage of charge in the capacitive discharge circuit after a predetermined value of current flows in the secondary shunt means.

4. An apparatus as claimed in claim 2, further comprising: means for preventing storage of charge in the capacitive discharge circuit after a predetermined value of current flows in the secondary shunt means.

5. An apparatus as claimed in claim 1 in which: the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with the pair of terminals and gated by the first timing generator, the primary shunt means includes a second timing generator activated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator, and the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third silicon-controlled rectifier in series with the second low-resistance shunt and gated by the third timing generator.

6. An apparatus as claimed in claim 2 in which: the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconducTor switch, and a first silicon-controlled rectifier in series with the pair of terminals and gated by the first timing generator, the primary shunt means includes a second timing generator actuated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator, the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third silicon-controlled rectifier in series with the second low-resistance shunt and gated by the third timing generator, and the means for preventing the application of the charge includes means for regulating a trigger voltage available for actuating the semiconductor switch in proportion to the amount of charge stored in the capacitive discharge circuit.

7. An apparatus as claimed in claim 3 in which: the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with a pair of terminals and gated by the first timing generator, the primary shunt means includes a second timing generator actuated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator, the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third silicon-controlled rectifier in series with the second low-resistance shunt and gated by the third timing generator, and the means for preventing the application of the charge includes means for regulating a trigger voltage available for actuating the semiconductor switch in proportion to the amount of charge stored in the capacitive discharge circuit, and the means for preventing storage of charge includes a circuit interrupter connected between the means for storing charges on the capacitive discharge circuit and the secondary shunt means on one side, and the means for applying and the primary shunt means on the other side, in such a manner that all charge stored in the capacitive discharge circuit and all charge dissipated in the secondary shunt means passes through the circuit interrupter.

8. An apparatus as claimed in claim 4 in which: the means for applying includes a semiconductor switch, a first timing generator actuated by the semiconductor switch, and a first silicon-controlled rectifier in series with a pair of terminals and gated by the first timing generator, the primary shunt means includes a second timing generator actuated by the semiconductor switch, and a second silicon-controlled rectifier in series with the first low-resistance shunt and gated by the second timing generator, the secondary shunt means includes a third timing generator actuated by the semiconductor switch, and a third silicon-controlled rectifier in series with the second low-resistance shunt and gated by the third timing generator, and the means for preventing the application of the charge includes means for regulating a trigger voltage available for actuating the semiconductor switch in proportion to the amount of charge stored in the capacitive discharge circuit, and the means for preventing storage of charge includes a circuit interrupter connected between the means for storing charge on the capacitive discharge circuit and the secondary shunt means on one side, and the means for applying and the primary shunt means on the other side, in such a manner that all charge stored in the capacitive discharge circuit and all charge dissipated in the secondary shunt means passes through the circuit interrupter.