US3626427A - Large-scale data processing system - Google Patents
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- US3626427A US3626427A US609238A US3626427DA US3626427A US 3626427 A US3626427 A US 3626427A US 609238 A US609238 A US 609238A US 3626427D A US3626427D A US 3626427DA US 3626427 A US3626427 A US 3626427A
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- 230000000977 initiatory effect Effects 0.000 claims 11
- 230000002159 abnormal effect Effects 0.000 claims 6
- 230000000903 blocking effect Effects 0.000 claims 6
- 238000011084 recovery Methods 0.000 claims 6
- 230000005540 biological transmission Effects 0.000 claims 4
- 230000007613 environmental effect Effects 0.000 abstract 3
- 238000012423 maintenance Methods 0.000 abstract 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The specification discloses an illustrative embodiment for the invention comprising a large-scale data processing system of the type which is composed of a plurality of quasi-independent units. The environmental data processing system includes a central processing unit or portion, which is herein referred to as a CPU, a plurality of storage units, a plurality of input/output control devices referred to herein as channels, as well as control and maintenance facilities which are found in a power distribution unit, herein referred to as a PDU. The CPU of the environmental system includes a control or instruction unit hereinafter referred to as an I-unit, and an arithmetic and logic or execution unit, hereinafter referred to as an E-unit. The I-unit includes controls for instruction fetching, branching, interruption handling, communication with the input/output channels, and other related functions. The E-unit of the environmental system can perform algebraic and logical operations, moving, shifting, and other functions.
Claims (62)
1. In a data processing system having a plurAlity of addressable storage locations for storing, inter alia, manifestations of instructions to be performed by said system, said manifestations hereinafter referred to as instructions, said system including addressing means and storage request means for controlling the fetching and storing of data from and to said storage locations, said storage locations sending an accept signal in response to accepted requests, certain of said instructions calling for a branch from a point in a sequence of instructions to a different point, said points being defined by the addresses of storage locations in which said instructions are stored, a branch control device, comprising: means responsive at a first period of system operation to the presence of a branch instruction to cause a fetch for the subject instruction thereof; a data buffer register, said buffer register being connected to said storage locations so as to be capable of receiving manifestations therefrom; instruction buffer registers, said instruction buffer registers being responsive directly to said storage locations and to said data buffer register; control means in said system for transferring from instruction predecoding to instruction execution, said control means being settable after sensing of a branch instruction only in response to an accept signal from said storage locations; branch testing means effective after said transfer for determining the presence or absence of conditions upon which branching is to be effected; and means responsive to a successful branch for loading said instruction buffer registers from said storage or from said data buffer register, alternatively, in dependence upon the time at which the successfulness of said branch is known.
2. A device described in claim 1 additionally comprising: means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.
3. A device described in claim 2 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.
4. A device described in claim 3 additionally comprising: means to cancel said additional branch fetch in the event that the branch fetch resulted in branch instruction.
5. In a data processing system in which addressable storage locations are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising: means for sensing an instruction which calls for a branch, said means including means to determine a condition upon which branching is to be effected; means responsive to said sensing means to initiate a storage fetch for the subject instruction; a data buffer register and instruction buffer register means, said buffer registers all being responsive to said storage means, said instruction buffer register means being responsive to said data buffer register conditionally, in dependence upon branch control thereover; accept means in said storage means for indicating the fact that it will provide a storage word in response to said branch fetch; means responsive to said accept means to perform operations which determine the fulfillment of the branch condition; and routing means for controlling the route of said branch instruction, said routing means directing the storage word resulting from said branch fetch directly to said instruction buffers in the event that said storage word is available at the input to said buffers after the determination of fulfillment of the branch is made, said routing means routing said storage word to said data buffer prior to the determination of the fulfillment of said branch, and said routing means directing said storage word from said data buffer to said instruction buffers when the determination of the fulfillment of the branch is known only following the routing of said storage word to said data buffer.
6. The device described in claim 5 wherein said storage word is automatically routed to said data buffer, whether or not it is simultaneously routed through said instruction buffer means.
7. In a data processing system in which addressable storage locations are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising: means for sensing an instruction which calls for a branch, said means including means to determine the condition upon which branching is to be effected; means responsive to said sensing means to initiate a storage fetch for the subject instruction; a data buffer register and instruction buffer register means, said buffer registers all being responsive to said storage means, said instruction buffer register means being responsive to said data buffer register conditionally, in dependence upon branch control thereover; means to perform operations which determine the successfulness of the branch instruction; routing means for controlling the route of said branch instruction, said routing means directing the storage word resulting from said branch fetch directly to said instruction buffers in the event that said storage word is available at the input to said buffers after the determination of successfulness of the branch is made, said routing means routing said storage word to said data bus prior to the determination of the successfulness of said branch, and said routing means directing said storage word from said data buffers to said instruction buffers when the determination of the successfulness of the branch is known only following the routing of said storage word to said data buffer.
8. The device described in claim 7 wherein said storage word is automatically routed to said data buffer, whether or not it is simultaneously routed through said instruction buffer means.
9. In a data processing system having a plurality of storage locations which are accessible by storage control means including addressing means and fetch request means, said data processing system operating in an overlapped execution fashion, whereby certain functions performed in the execution of a first instruction are overlapped in time with the performance of other functions for a second instruction, said system including controls for effectively transferring control over two groups of functions from a first instruction to a second instruction, a first group of functions being transferred from a previous instruction to a first instruction concurrently with a second group of functions being transferred from a first instruction to a second instruction, said transfer hereinafter referred to as I to E transfer, said system including an accept manifestation indicating that a storage request has been accepted, a branch control apparatus, comprising: means for sensing the presence of a branch instruction and for sensing a condition upon which said branch is to be effected, said condition if met resulting in a successful branch, the failure of said condition to be met resulting in an unsuccessful branch; means responsive to said sensing means to initiate a fetch request for the subject instruction of a branch instruction; means responsive to an accept signal resulting from said branch request to commit said I to E transfer, whereby functions to determine the successfulness of said branch may be performed; a data buffer register connected to said storage means; instruction buffer registers connected to said storage means and to said data buffer register; means responsive to various functions in said system for designating a successful branch; and deriving means responsive to said last-named means providing a storage word to said data buffer register and to said instruction buffer means in response to a successful branch, for routing said storage word to said buffer register in response to a lack of indication from said last-named means as to whether or not the branch was successful, for Routing said storage word from said data buffer register to said instruction buffers in the event that the successfulness of said branch is indicated by said last-named means after said storage word is loaded in said buffer, said storage word not being routed from said data buffer register in the event an unsuccessful branch is determined after the setting of said storage word into said data buffer register, said routing means also blocking the transfer of said storage word to either said data buffer register or said instruction buffer means in the event that the unsuccessful character of said branch is determined at the time said storage word becomes available to said buffers.
10. The device described in claim 9 additionally comprising: means responsive to the I to E transfer to provide an additional branch plus one fetch request to a storage word next in sequence to the storage word related to said branch request.
11. A device described in claim 10 wherein the storage word resulting from said branch plus one fetch is not routed in the event of the unsuccessfulness of said branch.
12. A device described in claim 11 additionally comprising: means concurrently responsive to said accept signals and to said sensing means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.
13. In a data processing system having storage means and a plurality of functional units capable of accessing said storage means, said storage means comprising at least two portions, said portions being independently operable so that storage references may be made alternately to first one and then the other, said storage references being performed in an interleaved fashion, said data processing system including a storage control device for initiating storage references, and for generating a select signal upon the initiation of a storage reference, said storage devices generating an advance signal indicative of the performance of a storage reference by the related storage device, a storage return control apparatus, comprising: a first binary trigger having first and second alternate states of operation, responsive to said select signals for alternating states in response to successive select signals received thereby; a second binary trigger having two alternate states of operation, responsive to said advance signals for alternating states in response to successive advance signals received thereby; a pair of registers, one of said registers being responsive to said functional units to store manifestations indicative of a functional unit which has initiated a storage reference when said first trigger is in said first state, the other of said registers being responsive to said functional units to store manifestations indicative of a functional unit which has initiated a storage reference when said first trigger is in said second state; connection means responsive to both of said registers, said connection means being selectively responsive to either a first one of said registers or to the second one of said registers, alternatively, in dependence upon the setting of said second binary trigger; means for checking, at identifiable times, the states of said first and second binary triggers; and means for indicating an error in the event that said triggers do not exhibit a proper phase relationship with one another.
14. In a data processing system in which addressable storage means are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising: means for sensing at a first period of system operation, the presence of a branch instruction and for causing a fetch for the subject instruction thereof; a buffer register, said buffer register being connected to said storage means so as to be capable of receiving manifestations therefrom; instruction buffer registers, said instruction buffer registers being responsive directly to Said storage means and to said buffer register; branch testing means responsive to conditions within said data processing system for determining the presence or absence of conditions upon which branching is to be effected; means responsive to a successful branch for loading said instruction buffer registers from said storage or from said buffer register, alternatively; and means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.
15. A device described in claim 14 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.
16. A device described in claim 15 additionally comprising: means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.
17. In a data processing system in which addressable storage means are referenced in order to derive instructions which govern the operation of said system, a branch control means for sensing the presence of a branch instruction to cause a fetch for the subject instruction thereof; a buffer register, said buffer register being connected to said storage means so as to be capable of receiving manifestations therefrom; instruction buffer registers, said instruction buffer registers being responsive directly to said storage means and to said buffer register; branch testing means responsive to conditions within said data processing system for determining the presence or absence of conditions upon which branching is to be effected; means responsive to a successful branch for loading said instruction buffer registers from said buffer register; and means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.
18. A device described in claim 17 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.
19. A device described in claim 18 additionally comprising: means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.
20. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the storage address register, said system having a PSW register, an other register and means for checking the PSW, a control device for the handling of interruptions and for providing other functions to said system, comprising: means including first gating means connected between said addressing adder and said storage address register; means including second gating means connected between one half of said PSW register and said other register; means including third gating means connected between the other half of said PSW register and said other register; means including fourth gating means connected between a first half of said PSW register and said means for checking; means including fifth gating means connected between the second half of said PSW register and said means for checking; a plurality of stable stages, each of said stages providing certain functions when in a first state, only one of said stages at a time being in said first state, each of said stages performing no function when in a second state, said stages being as follows: stage 1 provides address bits to the addressing adder and provides a signal to enable said first gating means to gate the addressing adder to the storage address register, stage 2 initiates a storage request, stage 3 provides a further address manifestation to the addressing adder, and provides signals to enable said first and second gating means to gate the addressing adder to the storage address regIster and to gate the right-hand half of the PSW to said other register, stage 4 initiates a storage request and also provides a signal to enable said third gating means to gate the left-hand half of the PSW to corresponding parts of said other register, the PSW half previously loaded into said other register being shifted to the low-order portion thereof, stage 5 receives new storage word from storage, loads it in said PSW register and provides a signal to enable said fourth gating means, half of said PSW register being gated to said means for checking, stage 6 provides signals to restore conditions established by said stages 1 through 5 and enable said fifth gating means to cause the other half of said PSW register to be gated to said means for checking, last stage resets blocking conditions and resumes normal system operations; and means to select from among said stages.
21. The device described in claim 20 additionally comprising; means for generating a timer advance request to select said first and second stages; means responsive to said second stage to decrement a storage word fetched thereby; means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation said last stage.
22. The device described in claim 20 additionally comprising: means to sense a machine failure; means responsive to said last-named means to reset portions of said system and to generate a starting signal; means responsive to said starting signal to select said first stage.
23. The device described in claim 20 additionally comprising: means external to said system for generating a stable external interruption signal; and means responsive to said last-named means for selecting said first stage.
24. The device described in claim 20 additionally comprising: input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means; means responsive to said signal generated by said last-named means to select said first stage; means responsive to said first stage to generate a channel interrupt response signal for transmission to said input/output means said input/output means presenting to said system in response thereto, a channel release signal; means responsive to said channel release signal for selecting said second stage.
25. The device described in claim 20 additionally comprising: IPL means for initiating an initial program loading operating for said system; means responsive to said last-named means for selecting said first stage; means responsive to said IPL means and to said second stage for setting an initial program load buffer device; means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth stage.
26. The device described in claim 20 additionally comprising: instruction-responsive means for selecting said first stage.
27. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the storage address register, said system including a PSW register, an other register and a point for checking the PSW a control device for the handling of interruptions and for providing other functions to said system, comprising: means including first gating means connected between said addressing adder and said storage address register; means including second gating means connected between one half of said PSW register and said other register; means including third gating means connected between the other half of said PSW register and said other register; means including fourth gating means connected between a fIrst half of said PSW register and said point for checking; means including fifth gating means connected between the second half of said PSW register and said point for checking; first means to provide address bits to the addressing adder and to enable said first gating means to gate the addressing adder to the storage address register; second means to initiate a storage request; third means to provide a further address manifestation to the addressing adder, and to enable said first gating means to gate the addressing adder to the storage address register, and to enable said second gating means to gate the right half of the PSW register to said other register; fourth means to initiate a storage request, to enable said third gating means to gate the left half of said PSW to a corresponding part of said other register, to shift the PSW half previously loaded into said other register to the low-order portion thereof; fifth means to receive a new storage word from storage and to store it in said PSW register, and to enable said fourth gating means to gate half of said PSW register to said point for checking thereof; sixth means to reset conditions established by said first through fifth means and to enable said fifth gating means to cause the other half of said PSW register to be gated to said point where it can be checked; and last means to reset blocking conditions and resume normal, operations.
28. The device described in claim 27 additionally comprising: means for generating a timer advance request to select said first and second means; means responsive to said second means to decrement a storage word fetched thereby; means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation of said last means.
29. The device described in claim 27 additionally comprising: means to sense a machine failure; means responsive to said last-named means to reset portions of said system and to generate a starting signal; means responsive to said starting signal to select said first means.
30. The device described in claim 27 additionally comprising: means external to said system for generating a stable external interruption signal; and means responsive to said last-named means for selecting said first means.
31. The device described in claim 27, additionally comprising: input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means; means responsive to said signal generated by said last-named means to select said first means; means responsive to said first means to generate a channel interrupt response signal for transmission to said input/output means, said input/output means presenting to said system in response thereto, a channel release signal; and means responsive to said channel release signal for selecting said second means.
32. The device described in claim 27, additionally comprising: IPL means for initiating an initial program loading operation for said system; means responsive to said last-named means for selecting said first means; means responsive to said IPL means and to said second means for setting an initial program load buffer device; and means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth means.
33. The device described in claim 27 additionally comprising: instruction responsive means for selecting said first means.
34. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provisions of an addressing adder which provides address manifestations to the storage address register, said system having a PSW register, an other register and means for checking the PSW A control device for handling of interruptions and for providing other functions to said system, comprising: means including first gating means connected between said addressing adder and said storage address register; means including second gating means connected between one half of said PSW register and said other register; a plurality of stable stages, each of said stages providing certain functions when in a first state, only one of said stages at a time being in said first state, each of said staged performing no function when in a second state, said stages being as follows: stage 1 provides address bits to the addressing adder and enables said first gating means to gate the addressing adder to the storage address register, stage 2 initiates a storage request, stage 3 provides a further address manifestation to the addressing adder, and enables said first gating means to gate the addressing adder to the storage address register, stage 4 initiates a storage request and also enables said second gating means to gate the left-hand half of the PSW to corresponding parts of said other register, stage 5 receives new storage word from storage and loads it in said PSW register, stage 6 restores conditions established by said stages 1 through 5, last stage resets blocking conditions and resumes normal system operations; and means to select from among said stages.
35. The device described in claim 34 additionally comprising: means for generating a timer advance request to select said first and second stages; means responsive to said second stage to decrement a storage word fetched thereby; means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation said last stage.
36. The device described in claim 34 additionally comprising: means to sense a machine failure; means responsive to said last-named means to reset portions of said system and to generate a starting signal; means responsive to said starting signal to select said first stage.
37. The device described in claim 34 additionally comprising: means external to said system for generating a stable external interruption signal; and means responsive to said last-named means for selecting said first stage.
38. The deice described in claim 34 additionally comprising: input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means; means responsive to said signal generated by said last-named means to select said first stage; means responsive to said first stage to generate a channel interrupt response signal for transmission to said input/output means, said input/output means presenting to said system in response thereto, a channel release signal; means responsive to said channel release signal for selecting said second stage.
39. The device described in claim 34 additionally comprising: IPL means for initiating an initial program loading operation for said system; means responsive to said last-named means for selecting said first stage; means responsive to said IPL means and to said second stage for setting an initial program load buffer device; means responsive to said initial program load buffer device and to the reset of a new PSW to select said sixth stage.
40. The device described in claim 34 additionally comprising: instruction responsive means for selecting said first stage.
41. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the address register, said system including a PSW register and another register, a control device for the handling of interruptions and for providing other functions to said system, comprising: first means to provide address bits to the addressing adder and gate the addressing adder to the storage address register; second means to initiate a storage request; third means to provide a further address manifestation to the addressing adder, and gate the addressing adder to the storage address register, fourth means to initiate a storage request, fifth means to receive a new storage word from storage and to store it in said PSW register; sixth means to reset conditions established by said first through fifth means; and last means to reset blocking conditions and resume normal operations.
42. The device described in claim 41 additionally comprising: means for generating a timer advance request to select said first and second means; means responsive to said second means to decrement a storage word fetched thereby; and means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation of said last means.
43. The device described in claim 41 additionally comprising: means to sense a machine failure; means responsive to said last-named means to reset portions of said system and to generate a starting signal; means responsive to said starting signal to select said first means.
44. The device described in claim 41 additionally comprising: means external to said system for generating a stable external interruption signal; and means responsive to said last-named means for selecting said first means.
45. The device described in claim 41 additionally comprising: input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means; means responsive to said signal generated by said last-named means to select said first means; means responsive to said first means to generate a channel interrupt response signal for transmission to said input/output device, said input/output device presenting to said system in response thereto, a channel release signal; and means responsive to said channel release signal for selecting said second means.
46. The device described in claim 41 additionally comprising: IPL means for initiating an initial program loading operation for said system; means responsive to said last-named means for selecting said first means; means responsive to said IPL means and to said second means for setting an initial program load buffer device; and means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth means.
47. The device described in claim 41 additionally comprising: instruction responsive means for selecting said first means.
48. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery means, comprising: means for comparing a fetch address and a store address; means responsive to said last-named means for manifesting, in a stable condition, the result of said comparison; an interruption entrance latch; means responsive to said manifested result for testing said system for interruptions and for conditionally setting said interruption entrance latch; and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.
49. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising: instruction responsive means for designating a single step branch instruction; a recovery-required latch; means rEsponsive to said last-named means for setting said recovery-required latch; means responsive to said recovery-required latch for testing said system for interruptions; means alternatively responsive to interruptions or to said recovery-required latch for entering into an interruption sequence; means responsive to said interruption sequence for selectively resetting a portion of said indicating means; fewer of said indicating means being reset in the absence of an interruption when said recovery-required latch is set than would otherwise be reset thereby; and means operative after said last-named means for fetching an instruction.
50. In a data processing system which includes a plurality of multistate indicating means for indication conditions in said system, one state of each of said indicating means being a reset state: means for comparing a fetch address and a store address; means responsive to said last-named means for manifesting, in a stable condition, the result of said comparison; an interruption entrance latch; means responsive to said manifested result for setting said interruption entrance latch; and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.
51. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising: instruction means for designating a single step branch instruction; a recovery-required latch; means responsive to said last-named means for setting said recovery-required latch; means responsive to said recovery-required latch for testing said system for interruptions; means responsive to said recovery-required latch in the absence of an interruption for entering into an interruption sequence; means responsive to said interruption sequence for selectively resetting a portion of said indicating means; and means operative after said last-named means for fetching an instruction.
52. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery means, comprising: instruction responsive means for designating a single step branch instruction; means responsive to said last-named means for manifesting, in a stable condition, an execute operation; an interruption entrance latch; means responsive to said execute operation for testing said system for interruptions and for conditionally setting said interruption entrance latch; and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.
53. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising: means for comparing a fetch address and a store address; a recovery-required latch; means responsive to said last-named means for setting said recovery-required latch; means responsive to said recovery-required latch for testing said system for interruptions; means alternatively responsive to interruptions or to said recovery-required latch for entering into an interruption sequence; means responsive to said interruption sequence for selectively resetting a portion of said indicating means; fewer of said indicating being reset in the absence of an interruption when said recovery-required latch is set than would otherwise be reset thereby; and means operative after said last-named means for fetching an instruction.
54. In a data processing system which includes a plurality of multistate indicating means for indicating conditions In said system, one state of each of said indicating means being a reset state: instruction means for designating a single step branch instruction; means responsive to said last-named means for manifesting, in a stable condition, an execute operation; an interruption entrance latch; means responsive to said execute operation for setting said interruption entrance latch; and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.
55. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising: means for comparing a fetch address and a store address; a recovery-required latch; means responsive to said last-named means for setting said recovery-required latch; means responsive to said recovery-required latch for testing said system for interruption; means responsive to said recovery-required latch in the absence of an interruption for entering into an interruption sequence; means responsive to said interruption sequence for selectively resetting a portion of said indicating means; and means operative after said last-named means for fetching an instruction.
56. In a data processing system, apparatus for moving groups of data from a source point in said system to a result location therein, comprising: means to sense boundary conditions of source point of said data and the result location of said data; means responsive to like boundary conditions for moving said data a plurality of groups at a time, in parallel; and means responsive to unlike boundary conditions for moving said data one group at a time.
57. The device described in claim 56, additionally comprising: means operative during a multigroup move to sense unlike boundary conditions after moving one set of groups; and means responsive to said last-named means for moving data one group at a time.
58. The device described in claim 57 additionally comprising: means operative during a multicharacter move to sense unlike boundary conditions at terminal boundaries thereof; and means responsive to said last-named means for moving data in single-character groups.
59. In a data processing system, apparatus for moving data from one point in said data system to another, comprising: means to sense boundary conditions of the source of said data and the result location of said date; and instruction responsive means responsive to like boundary conditions for moving said data in multicharacter groups and responsive to unlike boundary conditions for moving said data in single-character groups.
60. In a data processing system, apparatus for moving groups of data from one multigroup location in said data system to another multigroup location therein, comprising: means to sense boundary conditions of the source of said data and the result location of said data; and means responsive to said boundary conditions being coextensive with said locations for moving said data in multigroup sets, each set coextensive with said locations, said means responsive to unlike boundary conditions for moving one group at a time.
61. The device described in claim 60, additionally comprising: means operative during a multigroup move to sense unlike boundary conditions after moving between a first pair of locations; and means responsive to said last-named means for moving one group at a time.
62. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the address register, said system including a PSW register and another register, a control device for the handling of Interruptions and for providing other functions to said system, comprising: means to provide address bits to the addressing adder, gate the addressing adder to the storage address register, and to initiate a storage request; means to provide a further address manifestation to the addressing adder, gate the addressing adder to the storage address register, and to initiate a storage request; and means to receive a new storage word from storage, to reset certain conditions in said system, and to reset blocking conditions and resume normal operations.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60923867A | 1967-01-13 | 1967-01-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3626427A true US3626427A (en) | 1971-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US609238A Expired - Lifetime US3626427A (en) | 1967-01-13 | 1967-01-13 | Large-scale data processing system |
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| US (1) | US3626427A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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|---|---|---|---|---|
| US4843543A (en) * | 1986-04-25 | 1989-06-27 | 501 Hitachi, Ltd. | Storage control method and apparatus |
| US5924128A (en) * | 1996-06-20 | 1999-07-13 | International Business Machines Corporation | Pseudo zero cycle address generator and fast memory access |
| US6314493B1 (en) | 1998-02-03 | 2001-11-06 | International Business Machines Corporation | Branch history cache |
| US6834353B2 (en) | 2001-10-22 | 2004-12-21 | International Business Machines Corporation | Method and apparatus for reducing power consumption of a processing integrated circuit |
| US7395445B1 (en) * | 2004-03-26 | 2008-07-01 | Analog Devices, Inc. | Controller for power supplies |
| US20070260662A1 (en) * | 2006-05-05 | 2007-11-08 | Dockser Kenneth A | Controlled-Precision Iterative Arithmetic Logic Unit |
| US9146706B2 (en) * | 2006-05-05 | 2015-09-29 | Qualcomm Incorporated | Controlled-precision iterative arithmetic logic unit |
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| US20090300602A1 (en) * | 2008-06-03 | 2009-12-03 | Burke Michael R | Determining application distribution based on application state tracking information |
| US10521231B2 (en) * | 2010-06-24 | 2019-12-31 | International Business Machines Corporation | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor |
| AU2010355814B2 (en) * | 2010-06-24 | 2014-05-15 | International Business Machines Corporation | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor |
| US9851969B2 (en) | 2010-06-24 | 2017-12-26 | International Business Machines Corporation | Function virtualization facility for function query of a processor |
| US20110320773A1 (en) * | 2010-06-24 | 2011-12-29 | International Business Machines Corporation | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor |
| US10664269B2 (en) | 2010-06-24 | 2020-05-26 | International Business Machines Corporation | Function virtualization facility for function query of a processor |
| US11086624B2 (en) | 2010-06-24 | 2021-08-10 | International Business Machines Corporation | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor |
| US11188326B2 (en) | 2010-06-24 | 2021-11-30 | International Business Machines Corporation | Function virtualization facility for function query of a processor |
| US11809870B2 (en) | 2010-06-24 | 2023-11-07 | International Business Machines Corporation | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor |
| US20150058572A1 (en) * | 2013-08-20 | 2015-02-26 | Apple Inc. | Intelligent caching for an operand cache |
| US9459869B2 (en) * | 2013-08-20 | 2016-10-04 | Apple Inc. | Intelligent caching for an operand cache |
| US10380034B2 (en) * | 2017-07-14 | 2019-08-13 | International Business Machines Corporation | Cache return order optimization |
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