US3624838A - Address counter stage circuitry - Google Patents

Abstract

BISTABLE DEVICE IS IN THE SECOND CONDITION BOTH OF THE CONDUCTING ELEMENTS OF THE BIDIRECTIONAL DRIVER ARE TURNED OFF.

THE PRESENT DEVICE IS A STAGE OF A DATA PROCESSING REGISTER WHICH IS CAPABLE OF EITHER INCREMENTING OR DECREMENTING, DEPENDING UPON THE CONDITIONS OF THE PREVIOUS OR SUCCEEDING STAGES. THE PRESENT DEVICE INCORPORATES A BISTABLE DEVICE WHICH PROVIDES TWO IDENTICAL OUTPUT SIGNALS WHEN THE BISTABLE DEVICE IS IN ONE CONDITION AND PROVIDES TWO OTHER KINDS OF OUTPUT SIGNALS EACH OF WHICH IS DIFFERENT FROM THE OTHER AND DIFFERENT FROM THE FIRST MENTIONED OUTPUT SIGNAL WHEN THE BISTABLE DEVICE OPERATES IN THE SECOND CONDITION. THE OUTPUT SIGNALS ARE COUPLED TO A BIDIRECTIONAL CURRENT DRIVER COMPOSED OF TWO CONDUCTING ELEMENTS AND OPERATE ON THAT BIDIRECTIONAL CURRENT DRIVER SUCH THAT WHEN THE BISTABLE DEVICE IS IN THE FIRST CONDITION THE BIDIRECTIONAL CURRENT DRIVER HAS EITHER CONDUCTING ELEMENT AVAILABLE FOR OPERATION WHILE WHEN THE

Description

United States Patent lnventor George R. Cogar RD. #3, Frankfort, N.Y. 13340 [21] Appl. No. 534,583 [22] Filed Feb. 28, 1966 [45] Patented Nov. 30, 1971 [54] ADDRESS COUNTER STAGE CIRCUITRY 8 Claims, 1 Drawing Fig.

[52] U.S.C1 307/221, 307/247, 307/255, 307/288 [51] Int. Cl Gllc 19 00, H03k 21/00 [50] Field ofSearch 307/221, 224, 247, 255, 289, 270; 328/37, 51; 340/166, 174 SR, 174 M, 174.12, 174.1 K, 174.1 L

[56] References Cited UNITED STATES PATENTS 2,577,015 12/1951 Johnson 328/206 X 3,020,418 2/1962 Emile, Jr. 307/238 3,031,588 4/1962 Hilsenrath 307/255 X COUNT UP PRIOR Primary Examiner-Donald D. Forrer Assistant Examiner-John Zazworsky AnarneysCharles C. English, William E. Cleaver, Sheldon Kapustin and Griffin and Branigan This application filed under Rule 47.

when the bistable device operates in the second condition.

The output signals are coupled to a bidirectional current driver composed of two conducting elements and operate on that bidirectional current driver such that when the bistable device is in the first condition the bidirectional current driver has either conducting element available for operation while when the bistable device is in the second condition both of the conducting elements of the bidirectional driver are turned off.

STAGE cou111 61 1101111 F' 29 43 41 15 11 succrromc 56 STAGE 27 35 /2; 49 CLEAR, 28 T SWITCH 65 65 -L 31 l g5 w rosuccrrnmc AND PRlOR STAGES C 67 READ WRITE CURRENT CURRENT ggy;

DRIVER DRIVER P/IIEIITEIIIII so Ian 3; 624,838

25 19 25 COUNT 55 59 PRIOR I STAGE T I I M N1 COUNT 57 -61 21 DOWN Q H 29 43 13 4? 15] SUCCEEDING 56 I W STAGE 27 35 35 i 49 CLEAR 28 SWITCH '65 L 63 l I 51 41 37 v g5 M To SUCCEEDING AND PRIOR STAGES READ wRITE ACTIVE CURRENT CURRENT DRIvER DRIVER STAGE- INVENTOR GEORGE R. COG AR A TTORNE Y ADDRESS COUNTER STAGE CIRCUITRY This invention relates to memory address registers, and, more particularly, to the circuitry employed in the single stage thereof.

It is the normal practice to use address registers in conjunction with data processor memories for the purpose of effecting the selection of a particular part of the data processor memory. In the normal mode of operation, there is a column address register and a row address register. The row address register is generally set in a particular position, for instance, column 1, and remains in that position while the column address register is advanced through the number of positions that represents the number of columns. In other words, in a memory which might have 8 rows and 8 columns, the column address register would have three flip'flop stages connected as a counter which would enable it to count up to eight. The row address register would have three flip-flop stages connected as a counter which would enable it to count up to eight. In a normal operation the row address register would be set in its one position and thereafter the column address register would be advanced one through eight, before the row address register is advanced to its second stage. In some embodiment it is desirable to provide address registers which are not only advanced, or incremented, but also are decremented. ln such arrangements the column address register might well be stepped from eight through one and thereafter the row register would be decremented or stepped in a downward direction.

The present invention involves a stage of an address register which provides a means for having the stage act to either increment or decrement the address register depending upon the conditions of the previous or succeeding stages. In addition, the present invention incorporates a means for providing a bidirectional current drive. The bidirectional current drive is used to provide read and write current, respectively, through the cores of the memory device with which it is used. The present invention has the advantage of using an on-on bistable device which acts to simultaneously turn on and turn off a pair of complementary transistors which are connected to act as a bidirectional current gate. Hence the storage element (the on-on" bistable circuit) not only acts to remember the condition of the stage but activates a bidirectional current gate. In addition, the present circuit provides a means for driving an external indicator (lamp) load without requiring an additional amplifier.

The operation and the advantages of the invention will be apparent to those skilled in the art from the following detailed description taken in conjunction with the appended drawing which shows a schematic diagram of one stage of an address register.

In the FIGURE transistors 11 and 13 are shown connected together to provide a circuit which is often identified as an on-on bistable device. Such a bistable device is so labeled because in one of its bistable states both the transistor 1 l and transistor 13 are conducting, while in the other stable state, both of the transistors are turned off.

Consider first that the transistors 11 and 13 are turned off. In this state, the resistance network made up of resistors l5, l7 and 19 operates between the plus voltage supply 21 and the negative voltage supply 23 to provide a relatively positive potential at point 25. With the relatively positive potential at point 25 there is a positive potential applied to the base of transistor 11, thereby holding transistor 11 in a turned off state. It should be noted at this point that if the clear switch 27 is closed there is ground potential applied to the emitter of transistor 11. 7

With transistor 11 turned off, the voltage at point 29 is very close to the negative voltage appearing at the negative source 31. The foregoing is true because the resistor network made up of resistors 33, 35, 37 and 39, as well as the lamp 4! is designed such that resistors 37 and 39 are relatively small, while the resistors 33 and 35 are extremely large. Hence, a relatively negative voltage appears at point 43, i.e., the base of transistor 13. Accordingly, the transistor 13 is held in a tumed-off condition.

It should be further noted at this point that when transistor ll is turned off the lamp 4] conducts some small amount of current, but not a sufficient amount of current to have the lamp appear in a lighted condition. In addition, since the transistor 11 is turned off, and there is a relatively negative voltage appearing at point 29, the transistor 45 is held turned off. In a like manner, since the transistor 13 is turned off and there is a relatively positive voltage appearing at point 47 the transistor 49 is held in a turned-off condition.

Consider now that the circuit which is represented by the FIGURE is the third stage of an address register wherein the second stage has been turned on. Further consider that we are going to advance this address register and hence we want to transfer the active condition of the second stage to the third stage.

In accordance with the hypothetical just set forth terminal 51 would have a positive, or ground, potential applied thereto from the second stage, while terminal 53 prior to receiving a control signal would be experiencing a negative potential. The ground potential at terminal 51 is received from a terminal of the previous stage which is the counterpart of terminal 38 as shown in the FlGURE. Accordingly, the condenser 55 would be charged as shown by the positive and negative signs in the FIGURE Thereafter, when the register is to be advanced a control signal identified as a count-up" signal is applied to the terminal 53. The count-up" signal is a positive-going signal and in our particular mode of operation is ground potential. Hence the point 57 experiences a shift in potential in a positive direction which is proportional to the charge developed across the capacitor 55. The RC time constant existing in relation to the capacitor 55 and the resistor 59 is of a sufficiently long period of time that the positive potential at point 57 is experienced for a discrete period. In accordance with the operation of the present circuit, just prior to any of the stages being advanced or decremented, the clear switch is opened which stops the tran istor action of transistor 11, or any counterpart transistor which may be conducting, and hence turns all of the stages of the register into the off condition. Since the RC time constant of the condenser 55 and the resistor 59 is sufliciently long, these input circuits act as a memory. In other words, a stage which has been turned on will create a condition in the stage which precedes it and in the stage which succeeds it, which condition will remember that the intermediate stage has been turned on. Accordingly, a command signal after the clear signal will cause the address register to either advance or decrement.

ln our particular case, the positive signal at the terminal 51 charged the condenser 55 and hence when the count-up signal is applied to terminal 53, a positive voltage shift occurs at terminal 57 and the transistor 13 is turned on. When the transistor 13 is turned on, the feedback circuit through the resistor 17 along the line 61 to the base of transistor 11 causes the transistor 11 to turn on. This might be considered in another way. When transistor 13 is turned on, ground potential appears at terminal 47, and hence the voltage divider network made up of resistor 17 and 19 between the ground potential at 47 and the negative voltage supply at 23 causes a negative voltage shift at the point 25 and hence the transistor 11 is turned on. When transistor 11 is turned on, and the clear switch is closed, ground potential appears at terminal 29, and accordingly provides a sufficient voltage drop across the lamp 41 to cause the lamp to glow. in addition, the ground potential at point 29 enables the positive voltage supply 28 to develop a relatively positive potential at the base of transistor 13 and hence keep transistor 13 conducting.

With transistors 11 and 13 both conducting, there is ground potential applied to the bases of the respective transistors 45 and 49; and, hence each of these transistors is made ready for transistor action. Transistors 45 and 49 are complementary transistors which are connected emitter to emitter and collector to collector to provide a bidirectional current gate.

As the circuit is normally employed, a read-write driver is connected to the common emitter connection 63 and hence there is selectively applied either a positive or a negative potential to the common connection 63 to effect either read or write current. lf a positive potential is applied to the terminal 63 and the output line 64 is ultimately connected to ground through a transistor similar to transistor 45, only in another coordinate stage, then the transistor 49 becomes active and conducts current through the cores 65 and 66 in one direction. On the other hand, if a negative potential is applied to the terminal 63 the transistor 45 becomes active and conducts current from the active stage 67 through the load (in our instance, the cores 65 and 66) along 64 through the transistor 45 to the negative potential at 63.

Accordingly, the register stage incorporates a bidirectional switch which has two active elements and both of which are activated or deactivated simultaneously by associated transistors of the bistable device. if the stage had employed the usual on-off flip-flop and even connected thebidirectional current gate to the one active transistor such a circuit would not function as does the present circuit. if the foregoing circuit arrangement were provided the transistor of the bidirectional gate might be turned off when the active transistor was turned off but this in turn would drive the other transistor of the bidirectional gate harder. The present circuit employs a pair of complementary transistors in the form of an "on-on flipflop to control a pair of cpmplementary transistors in the bidirectional gate, hence botli halves of the bidirectional current gate can be turned off and on simultaneously.

Normally such a stage has employed an amplifier connected to an active driver to effect a turning on of an indicator such as lamp 41. By making lamp 4] the most significant part of the load for transistor 11 thereis asaving in components.

It should be understood that a count-down procedure is identical to the above-described count-up procedure excepting that a countdown control signal would be applied to terminal54. v k

it is to be understood that what has been described is considered to be only a specific illustration of the invention and various and numerous other arrangements maybe devised by one skilled in the art without departing from the spiritand scope thereof.

The embodiments of the invention in which an exclusive property or privilege is claimed are'defined as'follows: l. A shift register stage comprising in combination: a. a bistable device capable of functioning in first ,and

second conditions, said bistable device providing two first output signals of the same voltage value while functioning in said first condition and providing second and third out:

put signals while functioning in said second condition, said first, second and third outputsignals having different voltage values from each other;

b. input signal means connectedto said bistable device to cause said bistable device to be transferred from said second condition to said first condition;

c. clear signal means connected tosaid bistable device to cause said bistable device to be'transferred from said first condition to said second condition;

d. bidirectional current gate means comprising first and second sections, said first section having input and output means and being capable of driving DC having input current in a first direction, the said second section having input and output means and being capable of driving DC electrical current in a second direction, said first and second sections being connected together such that the output means of said first section is coupled to the input means of said second section and the output means of said second section is coupled to the input means of said first section; e. gate output circuitry means adapted to be connected to a load and being connected to the connection between said output means of said first section and said input means of said second section; gate input circuitry means connected to the connection between said input means of said first section and said output means of said second section, Q g. control circuitry means connected to said first and second sections of said bidirectional current gate means and to said bistable device to (l) transmit simultaneously both of said first output signals to saidbidirectional current gate means whereby in response thereto DC drive current is alternatively transmitted through said first section in a first direction to said load and throughsaid second section in a second direction from said load, and to (2) transmit simultaneously both said second and third output signals, respectively, to said first and second sections whereby in response thereto electrical current flow through said load is prohibited 2. A shift register stage according to claim I wherein said bistable device comprises a pair of complementary transistors connectedin an "on-on flip-flop arrangement.

3. A shift register stage according to claim 1 wherein said bistable device comprises a PNP transistor and an NPN transistor and circuitry meansconnecting the collector of said NPN transistor to the base of said PNP transistor as well as connecting the collector of said PNP transistor tothe base of said NPN transistor, said circuitry means further adapted to connect voltage sources to the respective. bases of said PNP transistor and said NPN transistor as well as the collector of said NPN transistor and the emitter of said PNP transistor.-

4A shift ,register stage according to claim 9 wherein there is an indicator light connected to said bistable device as a load.

5. A shift register stage according to claim 1 wherein said input signal means comprises first and second input circuits, said firstinput circuit comprising a first capacitor, a first resistor, and a first diode connected such that one terminal of said first capacitor and one terminal of said first resistor are common-connected at the anode of said first diode, said second input'circuit comprising a second capacitor, 21 second resistor and a second diode connected such that one terminal of said second capacitor and one terminal of said second resistor are common-connected to the anode of said second diode, said first and second input circuits further connected such that the cathodes of each of the first and second diodes are common-connected.

6. A shift resistor stage according to claim 5 wherein said first input circuit has the second terminal of said first capacitor adapted to be connected to a count-up control signal source and the. second terminal of said second resistor adapted to be connected to a prior stage signal source, and wherein the second terminal of said second capacitor is adapted to be connected to a count-down control signal source and the second terminal of said second resistor is adapted to be connected to a succeeding stage signal source.

7. A shift register stage according to claim 1 wherein said bidirectional current gate means comprises a pair of complementary PNP and NPN transistors connected such that the emitters of said transistors are connected together and the collectors of said transistors are connected together and further including read-write current drive means connected to the last mentioned common-connected emitters.

8. A shift register stage according to claim 1 wherein there are further included means connected to said bistable device which are adapted to be further connected to a prior stage or a succeeding stage in order to respectively effect a count-up or a count-down operation.

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