US3621371A - Current pulse stabilizer for variable loads - Google Patents

Current pulse stabilizer for variable loads Download PDF

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Publication number
US3621371A
US3621371A US25007A US3621371DA US3621371A US 3621371 A US3621371 A US 3621371A US 25007 A US25007 A US 25007A US 3621371D A US3621371D A US 3621371DA US 3621371 A US3621371 A US 3621371A
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winding
current
load
transformer
power
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US25007A
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English (en)
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Wayne R Brumm
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Electronic Memories and Magnetics Corp
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Electronic Memories and Magnetics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/45—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

Definitions

  • a. transformer having a m first winding connected in series between a pulse voltage [54] CURRENT PULSE STABILIZER FOR VARIABLE source and a variable load.
  • a square loop hysteresis core of LOADS the transformer is biased with regulated DC current in a 12 Chhns3Dnwing m second winding through a choke coil which stores energy while the bias field is being overcome by a voltage pulse, and [52] US. Cl 323/17, restores energy to a power Supply for the current pulse source 323/56 323/66 323/89 340/174 TB at the end of the current pulse.
  • a fast-rise current pulse to a load with a substantially constant amplitude under varying load conditions.
  • a given N-bit word is read from a group of N cores by selectively applying coincident current pulses to drive lines which pass through all cores of the group.
  • the word is read out in parallel by sensing voltage pulses produced on N separate sense lines when cores of the group are switched from a binary-l state to a binary-O) state. Since the number of cores in a binary-l state at any one time may vary from to N, the load on the drive current pulse source may vary. Consequently, accurate control of current amplitude is difiicult to achieve. A substantially constant rise time of drive current is also difficult to achieve.
  • An object of this invention is to provide an improved pulsed current source for use with a variable load.
  • Another object is to provide an improved control of amplitude for pulsed currents applied to core memory systems.
  • Another object is to provide a common amplitude control system for a plurality of independent pulsed current sources, each source connected to a different load.
  • Another object is to provide an amplitude control system for a plurality of independent pulsed current sources, which system allows setting the control for all pulsed current sources from a single point.
  • Still another object is to provide an amplitude control system for pulsed current sources in tight controlled current loops to avoid oscillations and minimize noise.
  • Yet another object is to provide a pulsed current source for variable loads with fast and substantially constant rise times.
  • Yet another object is to provide a pulsed current source with an amplitude regulation system for core memory systems with reduced power requirements for the total system and reduced power dissipation in the regulation system by restoring both positive and negative energy to the power supply in a substantially balanced manner.
  • a first winding of a transformer having a hysteresis loop core and a first winding in series with a variable load and a voltage source of a given polarity at one end, and a switch for initiating a current pulse through the load connected to a voltage source of opposite polarity at the other end.
  • a second winding of the hysteresis loop transformer is connected in series with high inductance and a source of regulated DC cur rent to bias the hysteresis loop transformer with a magnetic field of a given polarity.
  • the core of the transformer is selected to have a long switching period in relation to the current pulse period.
  • a current pulse through the first winding produces a magnetic field of opposite polarity to overcome the DC bias field and increase the applied magnetic field to an upper coercivity level of the hysteresis loop core.
  • the hysteresis loop transformer is quickly transformed from a low to a high impedance element to limit the amplitude of the current pulse to the load.
  • the inductance in series with the second winding stores energy while the core is thus being driven and returns a substantial part of that energy through a switching diode at the load end of the transfonner to the system power supply once the current pulse is terminated on the first winding. While energy is thus being returned by current through the second winding, the core is driven back below its lower coercivity level in order that the hysteresis loop transformer may once again function as a stabilizer for a subsequent current pulse: to be delivered to the load.
  • a plurality of hysteresis loop transformers may be provided, such as one for each bit drive line to selectively read out a word of N bits.
  • the second winding of each hysteresis loop transformer is connected in series with the second winding of all other hysteresis loop transformers and a source of regulated DC current.
  • the bias for all hysteresis loop transformers may then be adjusted from a single point by adjusting the bias current from the regulated DC current source.
  • a second switch is connected in series between the stabilizing transfonner and the load (core drive line of the magnetic memory). Both switches are initially turned on to provide a drive voltage of'2 v. during the current rise time.
  • the first switch is turned off during the flat top of the current pulse.
  • a switching diode connected between circuit ground and a junction between the first switch and the transformer provides a current path to return energy to the power supply.
  • That provides a direct current path for return of current from the positive power supply at the end of one bit line to the negative power supply at the end of the other paired bit line, thereby allowing current to be sustained in the paired bit lines at the maximum level in a tight-controlled loop.
  • FIG. I is a schematic diagram of the present invention for applying controlled current pulses to a variable load.
  • FIG. 2 is a graph of applied magnetic field versus flux density in the core of a hysteresis loop transformer biased for operation in accordance with the present invention.
  • FIG. 3 illustrates a plurality of hysteresis loop transformers employed to stabilize current pulses selectively applied to bit drive lines of a magnetic core memory.
  • FIG. 1 a circuit is shown for obtaining a stabilized amplitude for fast-rise current pulses to a variable load It), such as drive line of a magnetic core memory, through a first winding W, of a transformer T having a core with a hysteresis loop which is substantially square as shown by the curve in the graph of FIG. 2. That curve passes through points a, b, c and e upon being switched from one saturation state (point a) to a second saturation state (point e). If the applied magnetic field H is then decreased, the curve will follow the upper line passing through points 1, g and h back to the point a.
  • the core of the transformer can thus have two remnant states.
  • the core of the transformer T is made of steel in the form of a toroid with a switch time in the order of l microsecond for current pulses of periods substantially less than 1 microsecond, such as /4 of a microsecond. That will assure that the core will not be driven from the one saturation state at point a to the second saturation state at point e during a current pulse period. Instead, the core is driven through only points a, b, c and d. Between points a and b, the impedance of the transformer winding W, is low to allow a rapid rise of the current pulse through the load to a predetermined maximum amplitude determined by the bias which separates points a and 12.
  • the transformer winding W presents a high impedance to limit the current thereby producing a current pulse with a fast rise time and a flat top.
  • transistors Q, and Q are turned off to remove current drive through the load. The result is a current pulse with a fast fall time from the flat top as the core is returned to point a along the dotted line from point d to g.
  • a source 1 l of regulated DC current is applied to a second winding of the transformer T, through a choke coil 12 which presents sufficiently high inductance to stabilize bias current to the second winding W, of the transformer.
  • the regulated DC current from the source 1] establishes a DC bias field represented in FIG. 2 by a dotted line H
  • This DC bias field is stable under static conditions due to the regulation of current from the source 11, and under dynamic conditions due to the inductance of the choke coil 12.
  • the transistor 0, is connected as a series switch in a form conventional in a core memory system, namely a floating transformer coupled transistor switch employed as a voltage switch by having its emitter connected to a negative terminal (-V) of a DC power supply and a transformer T, having its secondary winding connected across the base-emitter junction of the transistor 0,.
  • the transistor Q is similarly connected as a series switch with its collector connected to the positive terminal of aDC power supply 14 and a transformer across its base-emitter junction.
  • a switching diode D When the transistor 0, is later turned off, at a time before the core of the transformer T, is switched to the second saturation point e, a switching diode D will also become forward biased to return negative energy to the power supply 13, as will be presently described more fully. In that manner, the hysteresis loop of the core in the transformer T, stabilizes the amplitude of the resulting current pulse to a predetermined level under various load conditions of the load 10.
  • FIG. 2 indicates the effect of the square loop characteristics of the transfonner 12 in stabilizing the current pulse.
  • the core of the transformer T While the core of the transformer T, is being driven from point a toward point d and then back to point a, some energy is dissipated in the core, and some stored in the magnetic field of the choke coil 12 is returned to the power supply 13. Thus, when the transistor Q, is turned off, the polarity and density of the core flux will then change over the path d-g-h-a. As is well known, the energy within the hysteresis loop represents energy dissipated as heat in the transfonner T,. Therefore, the material for the core should ideally be selected to have as thin a loop as possible, and yet be sufiiciently slow to avoid driving it to its second saturation point before the current pulse is terminated.
  • the voltage pulse induced in the first winding W forward biases the diodes D, and D, to return energy to the power supply 13.
  • the second winding W of the transformer T may be connected in series with the corresponding second winding of other hysteresis loop transformers employed to stabilize current pulses from independent sources through separate loads.
  • FIG. 3 shows (by way of example, and not by way of limitation) a portion of a three wire, 2 %D coincident current core memory having a plurality N of bit lines for a matrix of MN cores arranged in M groups of N cores such that the bit cores of any one group may be switched to the zero state to read out a given N-bit word in response to a current pulse in a given orthogonal word line (not shown) and a positive current is driven through the bit line L, in a direction indicated by an arrow +I when transistors are actuated in the manner described with reference to FIG.
  • the core is switched.
  • the word line pulse is delayed until the bit line pulse has reached its flat top in order that the binary digit read may be sensed on the bit line L (by means not shown) as a pulse if the digit is a binary-1.
  • a second bit line L, of the matrix is shown to better illustrate how the present invention may be used to restorenegative and positive energy to the power supplies l3 and 14 (FIG. 1) in a balanced manner during a memory cycle.
  • Transistors Q and Q are connected as floating transformer switches to selection diodes D, and D, through the line L, for read and write memory cycles.
  • the transistor 0; is turned on while transistors Q, and Q, are on. This provides an initial drive voltage of 2 v. through the diode D
  • the transistor Q is turned 011' to provide a pulse sustaining voltage of l v. the transistor Q, is turned off with the transistor Q, to complete a read cycle.
  • Negative energy stored by the inductor l2, and other inductance associated with the bias circuit is then returned to the power supply 13 via the diode D,.
  • a read cycle is usually followed immediately by a write cycle in a memory access cycle.
  • transistors Q, to Q are actuated in the same manner as transistors Q, to 0 using a separate transformer T, to stabilize the resulting negative current pulse.
  • the winding of the transformer T, in series with the bias stabilizing inductor 12 will induce a voltage across the winding connected to switching diodes D and D, to forward bias the diode D,,. In that manner, positive energy is restored through the diode D to the power supply 14 (FIG. I).
  • Transistors O and Q are similarly actuated with transistor Q,, for a selective positive read current pulse through a trans former T and the line L Transistors Q,,, to 0,, are actuated like transistors Q, to for a selective negative write current pulse through a transformer T, and a line L Other lines are selectively driven using cycle control transistors like transistors 0 and Q, and separate positive and negative current pulse stabilizing arrangement for each line.
  • All of the bias windings of the stabilizing transformers are connected in series with the inductor l2 and the constant current source 11.
  • not more than approximately six transformers should be so connected in a group without some series inductance between groups to store energy. in other words, the storage inductance for the series connected transformers should be distributed between groups of not more than about six.
  • FIG. 3 may be used for word drive lines in a similar manner. However, since only one line is driven at any given time, the return path for the current pulse is through circuit ground, and not through another line as in the case of conjugate bit drive lines. However, other advantages, including the balanced return of energy to the power supplies, are retained.
  • the balanced return results from the operation of oppositely poled read pulse stabilizers associated with conjugate lines for all lines during a read cycle.
  • current will be driven through only those lines storing a bit 1. Therefore, the balance is not complete during any given write cycle, but is complete over a large number of cycles. For instance, if a bit 0 is to be stored in line L, while a bit 1 is stored in line L only the transistor 0, is turned, and not the transistor 0,.
  • the return path for negative current through the line L is through a diode D, and circuit ground once the transistor 010 is turned off. When the transistor 0,, is turned off, energy is restored in the positive power supply through diode D Energy is not simultaneously restored in the negative power supply.
  • a bit 1 may be stored in the line L, and not in the line L, so that energy is then restored only in the negative power supply. Thus, over a large number of write cycles, the balance will be substantially complete.
  • each read cycle is normally followed by a write cycle.
  • the positive ener gy restored in one cycle balances the negative energy restored in the other cycle.
  • control of all current pulse sources is achieved from a single point. That allows variation of the amplitude of all current pulse sources with a common control on the regulated DC source 11, i.e., with a common control of the bias field for all hysteresis loop transformers.
  • the present invention may be employed in a two wire, 2%D memory system.
  • Other modifications may include additional levels of selection switches, and other switching arrangements including the arrangement for the switching diodes.
  • energy can be returned to the positive power supply by connecting the diode D to circuit ground and the diode D, to the positive power supply. If that is done, the switch 0-, could be omitted if a drive voltage of 2 v. is to be retained throughout the entire pulse period.
  • Apparatus for stabilizing a pulse of current fonn a source of DC power through a variable load comprising:
  • means including inductance in series with said second winding for driving regulated DC bias current through said second winding to saturate said core at said given polariy;
  • switching means for coupling said source of DC power in a series circuit with said load and said first winding to drive current through said load in a given direction, the polarity of said first winding relative to said second winding being such that current through said first winding will drive said core from saturation at said given polarity toward saturation at said opposite polarity, said switching means being active to drive said current through said load for a period of time sufficient to reach said coercivity level of current and less than necessary to drive said core to saturation at said opposite polarity;
  • a current pulse stabilizer for a variable load comprising:
  • a source of regulated DC bias current connected in series with said choke coil and said second winding for driving current through said second winding in a direction for biasing said core beyond a saturation point of a given polarity
  • a source of DC power having one terminal at a given polarity and another terminal connected to circuit ground;
  • switching means for DC coupling said one terminal of said power supply to said load through said first winding to drive current in a given direction through said load to circuit ground, the polarity of said first winding relative to said second winding being such that current through said first winding will cancel fiux in said core produced by bias current in said second winding, said switching means being active to produce said current pulse for a period of time less than necessary to drive said core through said saturation point of said given polarity to a saturation point of opposite polarity;
  • a pair of diodes connected to opposite ends of said first winding, one of said diodes being connected between circuit ground and one terminal of said first winding adjacent said source of power, and the other of said diodes being connected between said one terminal of said source of power and the other terminal of said first winding adjacent said load, said pair of diodes being poled for forward conduction in response to induced current from said second winding when current through said load is terminated by said switching means, whereby energy stored in said coil while current is driven through said load is returned to said source of power.
  • a second transformer with a square-loop hysteresis core having first and second windings, said second winding being connected in series with said choke coil to receive said bias current
  • a second source of power having one tenninal of a polarity opposite said given polarity and another tenninal connected to circuit ground;
  • a load through which a fast-rise current pulse is to be driven with a stable amplitude for different values of load impedance, said load being DC coupled at one end to circuit ground;
  • means including a choke coil for driving regulated DC bias current through said second winding in a direction for biasing said core beyond a saturation point of a given polarity;
  • a source of DC power having one terminal at a given polarity and another terminal connected to circuit ground;
  • first switching means at one end of said first winding for DC coupling said first winding in series with said load
  • first and second switching means connected to said one terminal of said source of power for DC coupling said source of power to said first winding to drive current in a given direction through said load to circuit ground, the polarity of said first winding relative to said second winding being such that current through said first winding will cancel flux in said core produced by bias current in said second winding, said first and second switching means being active for a period of time less than necessary to drive said core through said saturation point of said given polarity to a saturation point of opposite polarity;
  • first diode connected between circuit ground and said one end of said first winding, and a second diode connected between said one terminal of said source of power and said first winding at an end thereof opposite said one end, said first and second diodes being poled for forward conduction in response to induced current from said second winding when current through said load is terminated by said first and second switching means, whereby energy stored in said coil while current is driven through said load is returned to said source of power.
  • said means coupling said one end of said load to said circuit ground includes a second source of power having one terminal of polarity opposite said given polarity DC coupled to said load and another terminal connected to circuit ground, and wherein said first and second switching means are separately controlled, whereby both switching means may be activated initially to provide a drive voltage for current through said load equal to the sum of output voltages from said sources of power coupled to opposite ends of said load, and said first switching means at said one end of said first transformer winding may be deactivated at the end of the rise time of current through said load to reduce the drive voltage to that coupled to the end of said first transformer winding through said load until the end of the current pulse, at which time said second switching means may be deactivated.
  • said load is a core drive line of a magnetic core through which current must be driven in either direction, further including:
  • a second transformer with a square-loop hysteresis core having a first winding and a second winding, said second winding being connected in series with said choke coil and said second winding of said first transformer to receive bias current;
  • separately controlled switching means at each end of said first winding of said second transformer coupling said first winding in series with said load at the end thereof opposite said one end, and in series with said source of power of opposite polarity for operation in substantially the same manner as corresponding switching means connected to said first winding of said first transformer, the polarity of said first winding of said first transformer being such that current therethrough will cancel flux in said core of said second transformer produced by bias current in said second winding of said second transformer for current through said load in a direction opposite said given direction;
  • a bipolar current drive system for bit drive lines of a magnetic core memory wherein said drive lines are divided into two groups with current in lines are divided into two groups with current in lines of one group opposite current in lines of the other group, and wherein a given line in one group is paired with a given line in the other, a pair of current pulse stabilizers comprising:
  • first and second transformers each with a square-loop hysteresis core having a predetermined coercivity level of current required for switching it from saturation at a given polarity to saturation at an opposite polarity;
  • bias means including inductance in series with said second winding for driving regulated DC bias current through the second winding of each transformer in series to saturate each transformer at said given polarity;
  • negative and positive sources of DC power said negative source having one terminal connected to circuit ground said positive source having one terminal connected to circuit ground, whereby negative and positive current drive potentials are provided with respect to circuit ground;
  • first and second switching means for coupling said first and second sources of power in series circuits with respective ones of said paired lines and said first winding of said first and second transformers, respectively, to drive current through said paired lines in opposite directions, the polarity of said first winding relative to said second winding in each of said first and second transformers being such that current through said first winding will drive said core from saturation at said given polarity toward saturation at said opposite polarity, said first and second switching means being active to drive said currents through said given lines for a period of time sufficient to reach said coercivity level of current and less than necessary to drive said core to saturation at said opposite polarity; and
  • each pair of diodes being poled for forward conduction in response to induced current in said first winding to which connected when said first and second switching means terminate currents through said lines, whereby energy stored in said bias means is returned to said sources of power in a substantially balanced manner from said inductance in said bias means.
  • each line of said pair remote from said transformers is coupled to circuit ground by respective first and second switching means and said positive and negative sources of power
  • a given one of said first and second switching means comprises a first series switch at one end of said first winding of a transformer coupled to a source of power and a second series switch at the other end of said first winding of a transformer coupled to a line
  • said first and second switches of a given switching means may be activated simultaneously to initiate current with a drive voltage equal to twice the potential of a given power source
  • said first switch may be deactivated before said second switch to maintain drive current with a drive voltage equal to the potential of a given power source, said drive current being maintained through one of said paired diodes connected to circuit ground, whereby a tight-controlled pulsed current loop is maintained from one to the other of said paired lines through said diodes connected to circuit ground.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)
  • Digital Magnetic Recording (AREA)
US25007A 1970-04-02 1970-04-02 Current pulse stabilizer for variable loads Expired - Lifetime US3621371A (en)

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US2500770A 1970-04-02 1970-04-02

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US (1) US3621371A (enExample)
BE (1) BE765239A (enExample)
CA (1) CA939061A (enExample)
DE (2) DE2166079A1 (enExample)
FR (1) FR2088994A5 (enExample)
GB (1) GB1341498A (enExample)
SE (1) SE365330B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975672A (en) * 1974-10-18 1976-08-17 Rca Corporation Power supply with means to reduce on and off switching times of series regulated device
US3984799A (en) * 1974-12-17 1976-10-05 Nasa DC-to-DC converters employing staggered-phase power switches with two-loop control

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2882482A (en) * 1956-05-28 1959-04-14 Bell Telephone Labor Inc Magnetic core current regulating circuit
US3233114A (en) * 1960-06-14 1966-02-01 Ibm Magnetic core transistor logic circuit
US3263125A (en) * 1963-05-01 1966-07-26 Gen Electric Current limiting circuits and apparatus for operating electric discharge devices and other loads

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2882482A (en) * 1956-05-28 1959-04-14 Bell Telephone Labor Inc Magnetic core current regulating circuit
US3233114A (en) * 1960-06-14 1966-02-01 Ibm Magnetic core transistor logic circuit
US3263125A (en) * 1963-05-01 1966-07-26 Gen Electric Current limiting circuits and apparatus for operating electric discharge devices and other loads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975672A (en) * 1974-10-18 1976-08-17 Rca Corporation Power supply with means to reduce on and off switching times of series regulated device
US3984799A (en) * 1974-12-17 1976-10-05 Nasa DC-to-DC converters employing staggered-phase power switches with two-loop control

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SE365330B (enExample) 1974-03-18
GB1341498A (en) 1973-12-19
DE2116255A1 (de) 1971-10-14
CA939061A (en) 1973-12-25
DE2166079A1 (de) 1973-06-07
DE2116255B2 (de) 1973-10-31
BE765239A (fr) 1971-08-30
FR2088994A5 (enExample) 1972-01-07

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