US3605005A

US3605005A - Inverters

Info

Publication number: US3605005A
Application number: US71000A
Authority: US
Inventors: Albert Donald Stolzy
Original assignee: Deutsche ITT Industries GmbH
Current assignee: TDK Micronas GmbH; ITT Inc
Priority date: 1970-09-10
Filing date: 1970-09-10
Publication date: 1971-09-14
Anticipated expiration: 1988-09-14
Also published as: DE2145085A1; FR2106433A1; NL7112385A; FR2106433B1

Abstract

An inverter which can eliminate lower harmonics of a fundamental by switch timing. However, any number of harmonics may, in fact, be eliminated. Filter design is thus much less complex and expensive and, in some cases, a filter may be eliminated. It is an outstanding feature of the invention that the embodiments of FIGS. 1, 2 and 5 may be entirely and easily incorporated in an integrated circuit.

Description

A United States Patent a 25 i 1.35, r PULSE -0eAY L Isawaznroe SHOT 8/l970 Howelletal....... l 1/1970 Johnston OTHER REFERENCES IEEE Transactions, Selected Harmonic Reduction in Static DC-AC Inverters, pp. 374- 378, July I964, Copy in Class 321-9 A.

Primary Examiner-William H. Beha, .Ir,

AttorneysC. Cornell Remsen, Jr., Walter J. Baum, Paul W.

Hemminger, Charles L. Johnson, Jr. and Thomas E. Kristofferson ABSTRACT: An inverter which can eliminate lower harmonies of a fundamental by switch timing. However, any number of harmonics may, in fact, be eliminated. Filter design is thus much less complex and expensive and, in some cases, a filter may be eliminated. It is an outstanding feature of the invention that the embodiments of FIGS. 1, 2 and 5 may be entirely and easily incorporated in an integrated circuit.

. sari I 1 sero X I To gmrgm ear 1 1 esr 2 Z a I [r0 swircm 35 l PATENTED SEPI 41911 SHEET 1 0F 4 OUTPUT i FILTER OUTPUT CIRCUIT PATENTEDSEPMISYI 3.605.005

SHEET 3 OF 4 TO LEADING EDGE l l" 0F wexr succeome W H- PULSE (Posmvz) To LEADING wee M OF NEXT PQECEDING i5b +24iif 5o I 0 PULSE (NEGATIVE) Pr r r L661} EL h x f- TO swncues |5 15 l r42 1... I 4/ DELAY BUFFER.

I SWITCHING 1 I DELAY BUFFER. I 44 D .vl 4.5 we TO swn'c uas 175 l8 0 DELAY BDFFER DELAY BUFFER.

ee 7o e7 c DELAY BUFFER DELAY BUFFER ea V2 es 7a INPUT I .50

mvsn'rsns BACKGROUND OF THE INVENTION This invention relates to devices for converting DC voltages or currents into AC voltages or currents, and more particularly, to economical and high performance inverters.

The output of an inverter is normally filtered in an attempt to suppress the harmonics of the fundamental. These filters are very expensive, especially when designed to attenuate the lower harmonics.

In the past, inverters have been provided to suppress all harmonics below the third or fifth before filtering. For example, see U.S. Pat Nos. 3,324,374; 3,423,662 and 3,523,236. However, the elimination of such a small number of harmonics leaves much to be desired in reducing the complexity and cost of filter design.

SUMMARY OF THE INVENTION In accordance with the device of the present invention, the above-described and other disadvantages of the prior art are overcome by providing an inverter which produces sets of at least four positive pulses and at least four negative pulses.

The inverters of the invention can eliminate any number of harmonics. The reason it does so will be explained hereinafter.

The nature of switching periods is an outstanding feature of the inverters of the present invention.

Another outstanding feature of the inverters of the present invention is that the outputs thereof may be varied and the amplitude of any number of harmonics will remain equal to zero for every variation in the output signal magnitude.

Still another outstanding advantage of the invention resides in the fact that the size and logic of a binary counter and the logic of the invention may be reduced by 50 percent.

The above-described and other advantages of the invention will be better understood from the following description when considered in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are to be regarded as merely illustrative:

FIG. 1 is a schematic diagram of a portion of an inverter of the present invention;

FIG. 2 is a block diagram of the remainder of the inverter of FIG. 1;

FIG. 3 is a truth table of a counter shown in FIG. 2;

FIG. 4 is a graph of a waveform characteristic of the operation of the invention;

FIG. 5 is a block diagram of one alternative embodiment of the present invention;

FIG. 6 is a graph of a waveform characteristic of the operation of the embodiment shown in FIG. 5; and FIGS. 7, 8, 9 and 10 are block diagrams of other embodiments of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the drawings, in FIG. 1, a direct current source of potential is indicated at 10. Source 10 is shown as a variable source of potential. The invention may be practiced wherein a potential source is provided that has a constant DC output voltage which is not variable. However, a variable source of potential may be usefully employed in the embodiment of FIG. 10, for example, if desired. Source 10 has a positive output terminal 11 and a negative output terminal 12. A switch 13 is connected to terminal 11 to an output terminal 14. A switch 15 is connected from terminal 12 to an output terminal 16. A switch 17 is connected from terminal 11 to terminal 16. A switch 18 is connected from terminal 12 to terminal 14. Switches 13, I5, 17 and 18 may be entirely conventional switches. They are preferably electronic switches such as silicon-controlled rectifiers or the like, but they may be electromechanical or other switches. Switches 13 and I5 are controlled by a signal on a lead 19 from a flip-flop X shown in FIG. 2.

Switches

13 and 15 are closed simultaneously and opened simultaneously. Similarly,

switches

17 and 18 are closed simultaneously and opened simultaneously. However, if output tenninals l4 and 16 are connected to a filter 20, shown in FIG. I, through a transformer, not shown, or to the transformer through the filter, and if capacitors are used as storage devices, as is conventional, switches 13 and I5 need not open and close at the same time. The same is true of

switches

17 and 18. It is only important at what time a complete circuit is made through one pair of switches from source l0 to terminals 14 and 16.

Switches

13 and 15 are opened and closed simultaneously by a signal on an output lead 19 from a flip-flop X, shown in FIG. 2.

Switches

17 and 18 are opened and closed simultaneously by a signal on an output lead 21 from a flip-flop Y shown in FIG. 2.

A conventional binary counter 22 is provided including a logic circuit 23 and flip-flops A, B, C and D. Counter 22 is entirely conventional and is fed clock pulses from a clock pulse generator 24 through a delay 25. Counter 22 has a zero state and counts to 14. Counter 22 is reset to zero by an AND gate 26. AND

gates

27, 28, 29 and 30 receive inputs from flip-flops A, B, C and D and supply outputs to an OR gate 31. The logic of the gates will be apparent by inspection of the diagram of FIG. 2. A truth table for counter 22 is shown in FIG. 3. Thus, AND gate 27 produces a positive high output on the count of zero. AND gate 28 produces a positive high output on the count of three. AND gate 29 produces a positive high output on the count of five. AND gate 30 produces a positive high output on the count of eight. OR gate 31 has four inputs. Each of the outputs of gates 27 28, 29 and 30 are connected to the input of OR gate 31. The output of OR gate 31 is connected to the input of an AND gate 38. AND gate 38 also receives an input from the output of delay 25.

AND gate 38 produces the leading edge of output pulses at terminals 14 and 16in a certain time relationship. That is, the output of AND gate 38 sets one of the flip-flops X and Y at a time to the I state through AND

gates

32 and 33. The other inputs to AND

gates

32 and 33 come from a flip-flop Z which prevents one flip-flop X and Y from closing one pair of switches, shown in FIG. 1, while the other pair is closed. Flipflop Z merely changes state each time a reset pulse is produced at the output of AND gate 26. A one shot multivibrator 36 is provided for two reasons. Multivibrator 36 sets both flip-flops X and Y to the zero state after a predetermined period. The pulses at the terminals 14 and 16 are thus thereby terminated. Moreover, multivibrator 36 has a rotatable hand wheel 37 to adjust the time delay thereof.

OPERATION OF THE EMBODIMENT OF FIGS. 1 AND 2 In the operation of the present invention, clock pulse generator 24 produces eight clock pulses for each cycle of the fundamental appearing at terminals 14 and 16. Delay 25 is provided merely to ensure that multivibrator 36 has changed to the I state before flip-flops X and Y are set. Counter 22 counts in the conventional way and counts to 14 and is reset over and over again. AND gate 38 produces output pulses at the end of each of the following counts: 0, 3, 5 and 8.

First flip-flop X is set to the I state on the count of zero. The width of the pulse at the output of flip'fiop X is determined by multivibrator 36. Again, flip-flop X is set to the I state on the count of three. Again, the flip-flop X is set to zero by multivibrator 36. Setting and resetting then occurs again at the count of five and again at the count of eight. Flip-flop X is then turned off by flip-flop Z, and flip-flop Y counts in a manner identical to the manner in which flip-flop X has counted.

Output pulses produced at terminal 14 relative to ground terminal 16 are shown in FIG. 4. The time positions of the leading edges of all the pulses are invariant and occur at the positions shown. The degrees indicated are electrical degrees. The leading edge of the first pulse in a positive group of four pulsesis always spaced I from the leading edge of the first pulse in the next preceding and succeeding group of four posilive pulses. The same is true of the negative pulses. The polarity of one group of four is always opposite that of the next succeeding group of four. The pulses may thus be generated ad infinitum with alternate groups of opposite polarities.

The time positions of the trailing edges of all the pulses may be adjusted by turning wheel 37. The widths of all the pulses may thus be changed simultaneously to change the amplitude of the fundamental appearing across terminals 14 and 16.

It is an outstanding feature of the invention that multiple 2, multiple 3 and multiple harmonics are absolutely eliminated when the pulse width of all the pulses is varied over the range 24 Note that wheel 37 varies the widths of all the pulses simultaneously. One pulse is always the same width as each of the others. One pulse also has the same amplitude as each of the others. The leading or trailing edges of the pulses may be varied, or both. Only the relationship shown in FIG. 4 must be maintained,

PROOF A Fourier analysis of the wavefonn of FIG. 4 will reveal that this waveform has no multiple 2, 3 and 5 harmonics. This means that the waveform of FIG. 4 eliminates all of the harmonies 2. 3. 4, 5 and 6, and that the lowest harmonic which exists in the waveform is the seventh hannonic.

In order to demonstrate the outstanding advantages of the invention, a Fourier analysis of the waveform of FIG. 4 is,

therefore, made in the following.

From any textbook, the Fourier analysis of the waveform of the present invention is where A A, and B, are constants, and

x =2 1rT/ T where,

rr=3. l4l6, l time, 1' the tin t between the leading edges of the first positive pulse in eac' I l we successive groups of four positive pulses (the period o ht fundamental of the fundamental frequency, f,wheref=l/l.

By inspection of the present waveform, the average is zero and A =0 The present waveform is only piecewise continuous and must be integrated that way. Note the following is repeated.

Combining (10) and (11), sin nip-sin n(15+) =2 cos gus /+2 sm -15 The first and fourth terms, the second and fifth, and the third and sixth are combinable by the trigonometric identity,

cos s-cos t- 2 sin 5 (8+1) sm (a-t) (14) 0 Note that A, equals zero for all even harmonics (r r=2k where k=l, 2, 3, 4 because sinn/4(30)'=0 and For further treatment of multiple 3 and multiple 5 harmonies, substitute Frr/IS. For multiple 3 harmonics sub stitute n=3k.

A,1m 5k 5k 5k ignoring the even harmonics of k=2, 4, 6, 8 which have al- 20 2E +2 Sm cos --c0 ("2 (29) ready been eliminated. Note from equations (l7) and (18) that only the middle term in the brackets of [6) remains. 51 (2 .+.'I+5k That is, 2 2

ICT sin(21 3L,t)+sin(3 +w) 0 25 '0OS(- -+5k)iSln 5k (30) 5hr 3k 3k 2 T) icos T (20) The sum of the right-hand terms of equation (29) are thus 30 equal to zero because,

$2sin(5kd /2) cos 5k I /2) =Tsin5k l (31 Thus, A,,=0 for multiple 5 harmonics. The proof of B,,=0 for The plus sign is for k=l 5, 9, l3 The minus sign IS for k=3, multiple and 5 harmonics is similan l l I 5 The, The B, equivalent of equation (16) is,

, 35 sin $1 for odd harmonics$ gg =i2 sin '=+12 sin gsin x[cos e1 (i 1 5k, m an" an) 2 2 21) 40 (7 W' T- 1 3k: 3h- 3k:- cos( 2 +3k)-+ sin 31:4: (22) sm -+3k) sm The signs are for the same values of k as before.

From the trigonometric identity,

For multiple 3 harmonies,

Thus, A,,=0 for all multiple 3 harmonics.

To prove that A =0 for all multiple 5 harmonics, substitute 5k for 3k in equation l6) Again, Bu=0 for even harmonics because,

Combining equations (32). (33 34 35) and t 36),

From the trigonometric identity,

cos 2y=12 sin y (38) Therefore, B,,= for multiple 3 harmonics.

The 8,, equivalent of equation (32) for multiple harmomcs is as follows,

5 k 5k 35k: 2 sin 2 X[cos 2 a) +cos( 6 2 +cos 30 2 (3 Again, B.,=0 for the even harmonics because,

sin =0 when k is even. k

when k is odd. 85k 5k 5k Zik 51%) 155k; 5k) cos( 6 2 +cos( 30 .0

. 5k1r sin +5k)=icos 5k (43) Combining Equations 39 to 43, inclusive,

Thus, B,,=0 for multiple -5 harmonics.

THE ALTERNATIVE EMBODIMENT OF FIG. 5

In FIG. 2, the polarity control may be described as an output circuit as indicated by the dotted lines at 39.

In FIG. I, the entire circuit, with or without filter 20, may be described as a switching circuit indicated at 40.

In accordance with the foregoing, it is to be noted that each of the circuit components shown in FIG. 2 are also employed in FIG. 5. All that has been added is switching circuit 40 which may be identical to circuit 40 shown in FIG. 1 with or without filter 20. The connections from circuit 39 to circuit 40 in FIG. 5 are identical to those between circuit 39 in FIG. 2 and cir cuit 40 in FIG. 1. Thus, except for the connections between flip-flops A, B, C and D and

gates

27, 28, 29 and 30, the entire arrangement of FIG. 5 may be identical to that shown in FIGS. I and 2.

The purpose of the modification of FIG. 5 is to produce the waveform of FIG. 6. As before, the relative positions of the second, third and fourth negative pulse relative to the first negative pulse may be identical to the relative positions of the second, third and fourth positive pulse relative to the first positive pulse.

The amplitude of the positive pulses is equal to that of the negative pulses since the source I0 produces a substantially constant DC output voltage. As before, the trailing edges of all of the pulses shown in FIG. 6 may be varied in time relative to their leading edges by multivibrator hand wheel 37. However, all the pulses have the same pulse width, as before. The pulse width of the pulses shown in FIG. 6 must not exceed 12 electrical degrees, whereas the pulses shown in FIG. 4 may reach a pulse width maximum of 24.

The word degree" as used in any form herein refers to electrical degrees. As is conventional, I electrical degree is defined as a time equal to T/360 where T is the time between the first pulse in one set of positive pulses to the first pulse in the next succeeding set of positive pulses. T may also be defined as follows:

T=l/f where, f is the fundamental frequency in the output of the inverter.

From the foregoing, it will be appreciated that in FIG. 5, gate 27 produces a high output on the count of zero, as before. Gate 28, however, produces a high output on the count of 5, in FIG. 5. Gate 29, in FIG. 5, produces a high output on the count of 9. Gate 30, in FIG. 5, produces a high output on the count of I4.

It is another outstanding feature of the invention that the waveform of FIG. 6 has no multiple 2, multiple 3 and multiple 5 harmonics. A Fourier analysis of the waveform of FIG. 6 may be perfonned in the same manner that this analysis was performed on the waveform of FIG. 4.

It is an outstanding advantage of the waveforms of FIGS. 4 and 6, that the pulse width in each case may be varied, and that the said multiple 2, multiple 3 and multiple 5 harmonics in each case will have amplitudes equal to zero independent of any pulse width variation.

ELIMINATION OF ANY NUMBER OF HARMONICS In FIG. 7, a control circuit 41 supplies two outputs to two

corresponding delay devices

42 and 43, which, in turn, are impressed upon a switching circuit 44 through respective buffers 45 and 46. Buffers not only receive the outputs of

corresponding delays

42 and 43, but also receive inputs directly from corresponding outputs of control circuit 41 via

leads

47 and 48, respectively.

Control circuit 4] may be identical to FIG. 2. Alternatively, control circuit 41 may be identical to FIG. 5 without switching circuit 40. Thus, in the latter case, output circuit 39 in FIG. 5 would be connected to the inputs to

delays

42 and 43, respectively, and to the

leads

47 and 48, respectively. In either case, delays 42 and 43 may be identical. Each may provide a time delay equal to m7/ 1 4, where m equals any positive odd integer not 7 or a multiple thereof. In some cases, it may be especially advantageous if m equals unity. In such a case, delays 42 and 43 each would provide a time delay of T/ 14.

Buffers 45 and 46 each may be any conventional buffer amplifier or OR gate. Switching circuit 44 may be identical to circuit 40 with or without filter 20.

Note will be taken that in FIG. 7, as before, each negative set of pulses is, more or less, identical to each set of positive pulses. Further, the undelayed input to buffer 45 provides the regular group of four pulses. The delayed group of pulses at the input to buffer 45 provides a second group of four pulses, more or less identical to the other group of pulse inputs thereto, but delayed mT/l4 or T/I4, if desired. The same is true of buffer 46.

A dotted box 49, shown in FIG. 7, may be expanded, as shown in FIGS. 8 and 9. The chain may be increased to any extent, as desired. The output of switching circuit 44 in FIG. 7 does not contain any of the

harmonics

2, 3, 4, 5, 6, 7, 8, 9 and I and does not contain any multiple of 2, 3, and 7 harmonics. The circuit 50, shown in FIG. 8, will produce an output from circuit 44 when connected thereto which does not contain any of the

harmonics

2, 3, 4, 5, 6, 7, 8, 9, 10, II, and I2, and does not contain any multiple 2, 3, 5, 7, and l I harmonics.

Similarly, the circuit 51, indicated in FIG. 9, when connected between control circuit 41 and switching circuit 44, will leave the output of switching circuit 44 free from

harmonics

2, 3, 4, 5, 6, 7, 8, 9,10, 1l,l2,l3,l4, l5 and 16 and free from multiple 2, 3, 5, 7, II and I3 harmonics.

In FIG. 8, a delay 66, a buffer 70, a delay 67 and a buffer 71 are adapted to be connected in succession from circuit 41 to circuit 44. Also in FIG. 8, delay 68, bufi'er 72, delay 69 and buffer 73 are adapted to be connected in succession from circuit 41 to circuit 44.

In FIG. 9, delay 74, buffer 80, delay 75, buffer 81, delay 76 and buffer 82 are adapted to be connected in succession from circuit 41 to circuit 44. Again in FIG. 9, delay 77, buffer 83, delay 78, buffer 84, delay 79 and buffer 85 are adapted to be connected in succession from circuit 41 to circuit 44.

Delays 66 and 68 provide time delays equal to mT/14.

Delays

67, 69, 75 and 78 provide time delays equal to rT/22, where r is any positive integer not 11 or a multiple thereof. Delays 76 and 79 provide the delays equal to s T/26, where s, is any positive integer not 13 or a multiple thereof.

'The manner in which the chain may be designed for any length is by the general formula s,T/2A,, where s, is any positive integer. This is an expression which gives the design of all

delays succeeding buffers

82 and 85. For the first pair of such delays t=l for the second pair, F2; for the third pair, t=3, etc. A, is always a prime number having an order number B such that B =t+7. Thus, s, is always any positive integer not equal to A and not equal to any multiple of A,.

Note will be taken that all of the alternative embodiments described in connection with FIGS. 7, 8 and 9 reside in the use for circuit 41 of any one of the two embodiments described in FIG. 2 and FIG. 5 minus switching circuit 40. That is, of course, control circuit 41 cannot be two embodiments at the same time. For this reason, the embodiments of FIGS. 7, 8 and 9 produce output pulses in groups of four, each group matching a positive or negative group of four shown in one of the FIGS. 4 and 6. However, if the embodiment of FIG. 2 is employed in control circuit 41, all groups of four pulses in the output of circuit 44 will be of the type shown in FIG. 4 and not of the type shown in FIG. 6. Conversely, if the control circuit 41 is of the type shown in FIG. 5, minus circuit 40, all the groups of four pulses will be of the type shown in FIG. 6, and not of the type shown in FIG. 4. Moreover, it should be realind that depending upon the value of m, r, s, or s which is selected, one group of pulses may or may not be intermingled with those of another. Whether the pulses are intermingled or not does not in any way effect the advantageous operation of the invention or the elimination of any of the harmonics as described herein. That is, note ill be taken that, for example,

in FIG. 7, ifm is equal to unity, and the embodiment of FIG. 2 is employed in control circuit 41, that, most certainly, the first pulse of the delayed group will be positioned in between the first and second pulses of the undelayed group. Furthermore, the second and third pulses of the undelayed group would be located between the first and second pulses of the delayed group.

It is possible to eliminate the second, third, fourth, fifth, sixth, seventh, eighth, ninth and [0th harmonics by the embodiment shown in FIG. 10. This embodiment combines the waveforms of FIGS. 4 and 6 to eliminate the said harmonics. More harmonics than are eliminated by the embodiment of FIG. 10 may be eliminated by combining one or more waveforms of the type shown in FIG. 6 with one or more of the waveforms of FIG. 4, or vice versa. However, only the embodiment of FIG. 10 is disclosed as an example.

In FIG. 10, a clock pulse generator 52 provides an output to a delay device 53, a monostable multivibrator 54 and a monostable multivibrator 55. The output of delay 53 provides inputs to both of

control circuits

56 and 57. The outputs of

control circuits

56 and 57 with the outputs of

multivibrators

54 and 55 are impressed upon the

output circuits

58 and 59. Output circuit 58 is directly connected to a switching circuit 60. Output circuit 59 is connected to a switching circuit 61 through delays 62 and 63. The outputs of switching

circuits

60 and 61 are connected in parallel.

Control circuits

56 and 57 are always different. Control circuit 56 may have a first alternative construction of the type shown in FIG. 2, minus generator 24, delay 25, multivibrator 36 and circuit 39. Control circuit 56 may have a second alternative construction of the type shown in FIG. 5, minus the same components and minus switching circuit 40. Control circuit 57 may include the same said alternative constructions. However, the alternative construction selected for control circuit 56 must be different from that selected for control circuit 57 and vice versa.

Output circuits

58 and 59 are each identical to output circuit 39.

Switching circuits

60 and 61 are each identical to switching circuit 40, without filter 20.

The time delay provided by delay 62 is equal to the time delay provided by delay 63. When control circuit 56 is of the type shown in FIG. 2, the time delay provided by each of the delays 62 and 63 is T/70( 3+l0p), where p is any positive integer. When control circuit 56 is of the type shown in FIG. 5, the time delay provided by each of the delays 62 and 63 is T179 7+10q) Where q is any positive integer.

Due to the fact that the seventh harmonicof the waveform of FIG. 4 has neither an amplitude nor a relative phase which is the same as that of the seventh harmonic of the waveform of FIG. 6, a certain relationship must be maintained to ensure that the combined outputs of switching

circuits

60 and 61 do not have any seventh harmonic component. When control circuit 56 is of the type shown in FIG. 2, the following expression must be maintained equal to unity to eliminate the seventh harmonic:

E) 17 )1/2(cos 36) E1 1 7(1): 605 72 where,

E, is the output voltage of the DC source of circuit 61,

E, is the output voltage of the DC source of circuit 60,

I is the pulse width of the output pulses of circuit 61, and

Q, is the pulse width of the output pulses of circuit 60.

Note that the output pulses of circuit 60 are adjustable by multivibrator hand wheel 64, and the output pulses of circuit 61 are adjustable in width by multivibrator handwheel 65. The DC sources in

circuits

60 and 61 may also be variable, if desired. Note that source 10 is adjustable in FIG. 1. However, the same is not necessary. Further, if properly constructed, no DC source or one shot multivibrator need be variable in any construction of the present invention.

When control circuit 56 is of the type shown in FIG. 5, in order to eliminate the seventh harmonic from the output of the arrangement shown in FIG. 10, the following expression must be maintained equal to unity:

However, in this expression,

E is the output voltage of the DC source in circuit 60,

E is the output voltage of the DC source in circuit 61,

(I is the pulse width of the output pulses of circuit 60 variable with handwheel 65, and

D is the pulse width of the output pulses of circuit 61 variable with handwheel 64.

From the foregoing, it will be appreciated that a set of positive pulses is always employed with a set of negative pulses. The number of pulses in each positive set is always equal to the number of pulses in each negative set. The number of pulses in any set is always equal toll where n is any positive integer larger than unity. The embodiments of at least FIGS. 1, 2, 5, 7, 8 and 9 can eliminate lower harmonics simply by successively eliminating harmonics corresponding to prime numbers.

Where the widths of all the pulses are the same, it really does not matter from which point in a pulse the pulse spacing is measured. However, when the pulses are of different widths, the pulse spacing must be measured from the center of each pulse.

Comparison of FIG. 4 with FIG. 6 will reveal that regardless of the spacing, the waveforms are similar. Thus, the spacing between the first and second pulses is always aT/30. The spacing between the second and third pulses is always bT/30, where a is either 3 or and b is either 2or 4. However, when a is 3, b is always 2, and vice versa. Further, when a is 5, b is always 4, and vice versa.

Filter 20 may conveniently be adapted to attenuate some or many or all harmonics of the fundamental frequency, f, if not otherwise suppressed. Filter 20 may have a pass band with an upper cutoff frequency lower than f and lower than f where f equals Nf, and N is a prime number having an order number N, where

prime numbers

1, 2, 3, 5, 7, etc., have order numbers l, 2, 3, 4, 5, etc., N being defined by N =n +3.

From the foregoing, it will be appreciated that all embodimerits of the present invention may be described generically. For example, the counters may produce outputs for counts d, e, f and g, respectively, where de=h, ef=i, fg=v, h being one of the

numbers

3 and 5,1 being one of the

numbers

2 and 4, and v being one of the

numbers

3 and 5. h=3 only when i=2 and v=3. i=2 only when h=3 and v=3.'v =3 only when h=3 and i=3. h=5 only when i=4 and v=5. i=4 only when h=5 and v=5. v==5 only when h=5 and i=4.

From the foregoing, it will be appreciated that pulse widths must be limited to the maximum space between the leading edges of the two closest leading edges when equal pulse spacing is employed. For example, in FIG. 4, the second and third pulses have leading edge spacing of 24. The maximum pulse width for equal width pulses must, therefore, be 24'.

In FIG. 6, the leading edge of the maximum positive pulse is only 12 from the leading edge of the first negative pulse. Thus, for equal pulse widths in the waveform of FIG. 6, all pulses must have a width equal to or less than 12.

When two groups of pulses are employed in one set of eight pulses, one set may have a different spacing than the other set. See FIG. 10. Thus, as before, the pulse spacing may be jTl30, H130, and jT/ [30, respectively, where, as before, j is one of the

numbers

3 and 5 and k is one of the

numbers

2 and 4, j being 3 only when k is 2 and vice versa, j being 5 only when k is 4 and vice versa.

Notwithstanding the fact that certain specific structures or combinations thereof have been illustrated and described in order to demonstrate how the present invention may be practiced, these structures may be changed entirely. For example, any number of higher harmonics may be eliminated completely without the use of any delays. Note will be taken that any means to produce the waveforms in which the undesired harmonics are absent will fall within the scope thereof. It is thus only the waveforms which are important, and not the structural arrangements or the details thereof which produce the waveforms.

If desired, all the delay devices disclosed herein may be omitted. Delay devices 25, shown in FIGS. 2 and 5, may be omitted, if desired. The same is true of delay device 53, shown in FIG. 10. Further, all of the delay devices and buffers shown in FIG. 7, 8 and 9 may be omitted, and other structures substituted therefor in box 49 or in any other portions of the circuits 41 and 44. Circuits 41 and 44 may also be changed completely.

To make perfectly clear the content of

circuits

56 and 57, shown in FIG. 10, neither of these

circuits

56 and 57 incorporate any clock pulse generator, delay device, multivibrator, or circuit 39, shown in FIG. 2. Further,

circuits

56 and 57 do not incorporate switching circuit 40.

Control circuit 57 in FIG. 10 has no reset gate or equivalent to gate 26. For synchronization, the reset gate in control circuit 56 is employed to reset both the counter in circuit 56 and the counter in circuit 57.

Further, in FIG. 10, output circuit 59 has no flip-flop Z or any output leads therefrom, as shown in FIG. 2. Further, output circuit 59 has no structure shown in circuit 39 to the left of flip-flop Z. Output circuit 59 thus does not receive any reset gate input. Instead, the 1 output of the Z flip-flop equivalent in circuit 58 is connected to the input of the gate 32 equivalent in circuit 59, and the 0 output of the Z flip-flop equivalent in circuit 58 is connected to the input of the gate 33 equivalent in circuit 59.

It is an advantage of the present invention that multiple 2, 3 and 5 harmonics are all absent from the output of terminals 14 and 16 of the embodiment shown in FIG. 1, and also absent from the output of switching circuit 40 shown in FIG. 5. However, it has not been discussed how this affects the lower harmonics. Since the second, fourth and sixth harmonics are all multiple 2 harmonics, these harmonics are all absent. Similarly, the third and fifth are missing. Thus, in the case of the embodiment of FIGS. 1 and 2, and in the case of the embodiment of FIG. 5, the lowest harmonic present in the output is the seventh harmonic.

It is an outstanding feature of the invention that the embodiment of FIGS. 1, 2 and 5 may be entirely and easily incorporated in an integrated circuit.

When one occurrence is described as being spaced" from another occurrence, the word "spaced is hereby defined for use throughout this entire specification and the claims to mean spaced center to center," where the word center" refers to the time at the middle of the duration of each corresponding occurrence.

What is claimed is:

1. An inverter comprising: first and second input leads; first and second output leads; selectively operable first switch means actuable to connect either one of said output leads to said first input lead; selectively operable second switch means actuable to connect either one of said output leads to said second input lead; and control means actuable to actuate both of said switch means synchronously in a manner such that neither of said input leads are connected to both output leads at the same time, said first and second input leads being repeatedly connected to said first and second output leads, respectively, during first and second intervals of time, said first and second intervals having first overlapping portions, at least in part, said first and second input leads being repeatedly connected to said second and first output leads, respectively, during third and fourth intervals of time, said third and fourth intervals having second overlapping portions, at least in part, all of said first portions occurring at different times than all of said second portions in a manner such that none of said portions overlap in time, all of said portions being mutually exclusive, said first portions occurring repeatedly in sets of R where n, is any positive integer larger than unity, each first portion being repeated at a substantial constant frequency, f such that the first first portion of each two immediately succeeding sets are spaced in time by a period, T, given by T1 I If the second first portion of each two immediately succeeding sets also being spaced in time by a period, T, and so forth, the first second portion of each two successive sets also being spaced in time by period, T, and so forth, the time between the first and second first portions in each set thereof being equal to the time between the first and second second portions in each set thereof, the time between the second and third portions in each set thereof being equal to the time between the second and third second portions in each set thereof, and so forth, said control means being adapted to actuate said switch means in a manner to produce at least four first portions in each said set thereof and to produce at least four second portions in each set thereof, the time between the first and second of said four first portions being equal to aT/30, where a is one of the numbers3 and 5 the time between the second and third portions of said four first portions being bT/30, where b is one of the numbers 2 and 4, a being 3 only when 12 is 2, a being 5 only when I: is 4, the time between the third and fourth portions of said four first portions being aT/30.

2. The invention as defined in claim 1, including a DC source of potential having a positive terminal connected to said first input lead, and a negative terminal connected to said second input lead.

3. The invention as defined in claim 2, wherein said control means actuate said switch means in a manner such that all of said first'and second portions are produced for equal lengths of time.

4. The invention as defined in claim 3, including a filter connected from said output leads to attenuate some harmonics of the frequency, f, and having a pass band with an upper cutoff frequency larger than f and lower than f,,=Nf, where Nis a prime number having an order number N where

prime numbers

1, 2, 3, 5, 7, etc., have

order numbers

1, 2, 3, 4,5, etc., N, being defined by 5. The invention as defined in claim 4, wherein said control means includes means to adjust the time widths of all of said portions simultaneously.

6. The invention as defined in claim 1, wherein said control means includes means to adjust the time widths of all of said portions simultaneously.

7. The invention as defined in claim 1, wherein said control means actuate said switch means in a manner such that all of said first and second portions are produced for equal lengths of time.

8. An inverter comprising: first and second input leads; first and second output leads; a first switch connected from said first input lead to said first output lead; a second switch connected from said first input lead to said second output lead; a third switch connected from said second input lead to said first output lead; a fourth switch connected from said second input lead to said second output lead; first means actuable to close said first and fourth switches periodically for overlapping periods of time while both of said second and third switches are open; second means actuable to close said second and third switches periodically for overlapping periods of time while both of said first and fourth switches are open; a clock pulse generator; a pulse counter connected from said clock pulse generator; a plurality of AND gates connected from said counter to produce outputs at different corresponding counts of said counter; third means responsive to the output of said counter to reset said counter each time it arrives at the same first-predetermined count; fourth means including a bistable device and responsive to the output of said counter for changing states each time said counter arrives at the same second predetermined count; an OR gate connected from the outputs Of a plurality of said AND @5565; to said first and second means, said first and second means both being responsive to the output of said device and actuable thereby to supply actuating voltage pulses to corresponding pairs of said switches at times corresponding the different actuating outputs of said OR gate, said device deactuat'ing said first means and actuating said second means during alternate periods of time, and actuating said first means and deactuating said second means during the remaining periods of time all of said periods of time being equal in length, the end of each period being coincident with the beginning of the next.

9. The invention as defined in claim 8, wherein said first and second predetermined counts are each equal to 15, four of said AND gates being adapted to produce an output for counts d, e, f and g, respectively, where de=h, ef=i,fg=v, h is one of the

numbers

3 and 5, h=3 only when i=2 and v=3, i=2 only when h=3 and v=3, and v=3 only when h=3 and i=3, Ir =5 only when i==4 and v=5, i=4 only when h=5 and v=5, and v=5 only when h=5 and i=4.

10. An inverter comprising: first and second input leads; first and second output leads; a first switch connected from said first input lead to said first output lead; a second switch connected from said first input lead to said second output lead; a third switch connected from said secondinput lead to said first output'lead; a fourth switch connected from said second input lead to said second output lead; aclock pulse generator; a delay device connected from said clock pulse generator; a digital counter adapted to count the output pulses of said delay device; first, second, third and fourth AND gates connected from said counter to produce outputs on the counts of 0, 3, 5, and 8, respectively; a fifth AND gate to reset said counter at the end of the [5th count, said fifth AND gate also being connected from the output of said delay device; an OR gate connected from the outputs of said first, second, third and fourth AND gates; a sixth AND gate connected from the outputs of said delay device and said OR gate; a first flip-flop having a set l input, a set 0 input, a 1 output, and a 0 output; seventh and eighth AND gates connected, respectively, to the set 1 and set 0 inputs of said first flipJlop, the output of said fifth AND gate being connected to the input of each of said seventh and eighth AND gates, the 1 output of said first flipflop being connected to the input of said eighth AND gate, the 0 output of said first flip-flop being connected to the input of said seventh AND gate second and third flip-flops each having a 1 output, the 1 output of said second flip-flop being connected to said first and fourth switches, the 1 output of said third flip-flop being connected to said second and third switches, said second flip-flop having a set I and set 0 inputs, said third flip-flop having set 1 and set 0 inputs; ninth and 10th AND gates connected to the set 1 inputs of said third and fourth flip-flops, respectively, the output of said sixth AND gate being connected to the input of each of said ninth and 10th AND gates, the 1 output of said first flip-flop being connected to the input of said ninth AND gate, the 0 output of said first flip-flop being connected to the input of said 10th AND gate; and an adjustable monostable multivibrator connected from the output of said clock pulse generator, said multivibrator having a 0 output connected to the set 0 input of each of said second and third flip-flops.

11. An inverter comprising: supply means actuable to produce repeatedly positive and negative sets of pulses, none of said pulses being overlapping, the first pulse in each positive set being spaced from the first negative pulse by a period of time equal to T/ 2, the first pulse of each positive set being spaced from the first pulse in the next succeeding positive set by a period of time equal to T, the position of the second, third, etc., pulses in any one negative set relative to the first pulse in the same said one negative set being substantially identical to the positions of the respective corresponding second, third, etc., pulses in any one positive set relative to the first pulse in the same said one positive set, each of said sets having the same number of pulses, where n, is any positive integer larger than unity, each set including at least one group of four pulses, the first pulse of said one group being the first pulse of that particular set which includes said one group, the second pulse in said one group being spaced from said first pulse in said one group a time aT/ 30, where a is one of the numbers 3 and 5, the third pulse in said one group being spaced from said second pulse therein a time bT/ 30, where b is one of the numbers 2 and 4, the fourth pulse in said one group being spaced from said third pulse therein a time aT/ 30, a being equal to 3 only when b is equal to 2 and vice versa, a being equal to 5 only when b is equal to 4 and vice versa.

12. The invention as defined in claim ll, wherein said supply means includes means to adjust the time widths of all of said pulses substantially simultaneously.

13. The invention as defined in claim 12, wherein all of said pulses have substantially the same amplitudes and substantially the same time widths.

14. The invention as defined in claim 13, wherein each said set has only said one group of pulses.

15. The invention as defined in claim 11, wherein each said set has only two groups of pulses, the positions of the second, third and fourth pulses of said other group relative to the posi- 'tion of the first pulse of said other group being the same as the respective corresponding positions of the second, third and fourth pulses of said one group relative to the first pulse of said one group, the first pulse of said other group being spaced from the first pulse of said one group a time mT/ 14 where m is any positive odd integer not 7 or a multiple thereof.

16. The invention as defined in claim 15, wherein all of said pulses have the same amplitudes and have the same pulse widths.

17. The invention as defined in claim 16, wherein m equals unity.

18. The invention as defined in claim 11, wherein each said set has only said one group and one other group of pulses, the positions of the second, third and fourth pulses in said other group relative to the first pulse also being jT/ 30, kT/ 30 and jT/ 30, respectively, where j is one of the

numbers

3 and 5, and k is one of the

numbers

19. The invention as defined in claim 18, wherein the first pulse of said one group is the first pulse of the set including said one group, a being equal to 3, b being equal to 2,j being equal to 5, and k being equal to 4, the first pulse of said other group in the selfsame set lagging the first pulse in said one group by a time T/(3 .+l0p), where p is any positive integer, the amplitudes and pulse widths of the pulses in said one group all being the same, the amplitudes and pulse widths of all the pulses in said other group aIlbeingthe same, the amplitudes and pulse widths of all of said pulses being such that the following expression is equal to unity E is the amplitude of said one group of pulses,

E is the amplitude of said other group of pulses,

P is the pulse width of said one group of pulses, and

P, is the pulse width of said other group of pulses.

20. The invention as defined in claim 18, wherein the first pulse of said one group is the first pulse of the set including said one group, a being equal to 5, b being equal to 4,j being equal to 3, k being equal to 2, the first pulse of said other group in the self same set lagging the first pulse in said one group by a time T/70(7+l0q), where q is any positive integer, the amplitudes and pulse widths of the pulses in said one group all being the same, the amplitudes and pulse widths of all the pulses in said other group all being the same, the amplitudes and pulse widths of all of said pulses being such that the following expression is equal to unity where,

E is the amplitude of said one group of pulses, E is the amplitude of said other group of pulses, D, is the pulse width of said one group of pulses, and D is the pulse width of said other group of pulses.

Egg? UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 605, 005 Dated September 14, 1971 flswi isiit- It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 3, line 12, change "0 -24" to read 0-24 degrees-.' Column 3, line 35, that portion of the equation reading "T/T should read -t/T. Column 4,

lines

6 and 7, equation (8) should read as follows:

Column 4, line 9, that portion of equation (9) reading 'YuV)" should read -(u v)-. Column 4, line 72, the equation should read as follows:

sing (15 /1)= 0 Column 5, lines 35-40, equation (21) should read as follows:

sin I lfor odd harmonics 3A 71k i2 sin cos cos 3k (21) Column 5, line 50, equation (23) should read as follows:

sin 2y 2 sinycos y j; 2 sin cos isin 31 1 I (23) Cblumn 5, lines 65-75, equations (25 and (26) should read as fol-lows:

sin 5 -I l for odd harmonics UNITED STATES PATENT OFFICE 5 5g CERTIFICATE OF CORRECTION Patent No. 3,605, 005 Dated September 14, 1971 Inventofls) A, D. Stolzy It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

X Sin SSkrr 5k?) k 51 sin( 6 2 155m 5k (T Z cos 3 516 sin (25) krr 51 kn 51:2 s1n( 10 2 sin (ISk 2 Column 6, between lines 20 and 25, that portion of equation (30) reading "-cos 516 should read cos( 5k)--. Column 6, line 31, equation (31) should read as follows:

I 2 sin cos I sin 51? (31) Column 9, line 75, delete ill" and insert will-.

Column 11, line 22, delete "2 0" and insert -2 Column 11, atter line 35, insert the following and the spacing between the third and fourth pulses is always Column 11, 1ine ete "jTlSO" and insert Column 11, line 69, delete "kT" and insert UNITED STATES PATENT OFFICE CERTIFEQATE 0F 0RRECTION patent 3,605,095 Dated September 14, 1971 Albert Donald Stolzy PAGE 3 Inventor(s) It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 13, line 2 in Claim 1, delete "2 0" and insert --2 Column 13, line 7 in Claim 1, that portion of the equation reading "TT" should read --T-. Column 13, line 39 in Claim 4, that portion of the equation reading "f should read -f Column 14, line 16 in Claim 9, after "5" insert the following -i is one of the

numbers

2 and 4, v is one of the

numbers

3 and 5, Column 14, line 74 in Claim 11, delete "20" and insert -2 Signed and sealed this 11th day of April 1972.

(SEAL) Attest:

ROBERT GOTTSCHALK EDWARD iLFLE'I'CHmRJR.

Commissioner of Patents Attesting Officer

Claims

1. An inverter comprising: first and second input leads; first and second output leads; selectively operable first switch means actuable to connect either one of said output leads to said first input lead; selectively operable second switch means actuable to connect either one of said output leads to said second input lead; and control means acTuable to actuate both of said switch means synchronously in a manner such that neither of said input leads are connected to both output leads at the same time, said first and second input leads being repeatedly connected to said first and second output leads, respectively, during first and second intervals of time, said first and second intervals having first overlapping portions, at least in part, said first and second input leads being repeatedly connected to said second and first output leads, respectively, during third and fourth intervals of time, said third and fourth intervals having second overlapping portions, at least in part, all of said first portions occurring at different times than all of said second portions in a manner such that none of said portions overlap in time, all of said portions being mutually exclusive, said first portions occurring repeatedly in sets of 2n where no is any positive integer larger than unity, each first portion being repeated at a substantial constant frequency, f such that the first first portion of each two immediately succeeding sets are spaced in time by a period, T, given by TT 1/f the second first portion of each two immediately succeeding sets also being spaced in time by a period, T, and so forth, the first second portion of each two successive sets also being spaced in time by period, T, and so forth, the time between the first and second first portions in each set thereof being equal to the time between the first and second second portions in each set thereof, the time between the second and third portions in each set thereof being equal to the time between the second and third second portions in each set thereof, and so forth, said control means being adapted to actuate said switch means in a manner to produce at least four first portions in each said set thereof and to produce at least four second portions in each set thereof, the time between the first and second of said four first portions being equal to aT/30, where a is one of the numbers 3 and 5 the time between the second and third portions of said four first portions being bT/30, where b is one of the numbers 2 and 4, a being 3 only when b is 2, a being 5 only when b is 4, the time between the third and fourth portions of said four first portions being aT/30.

3. The invention as defined in claim 2, wherein said control means actuate said switch means in a manner such that all of said first and second portions are produced for equal lengths of time.

4. The invention as defined in claim 3, including a filter connected from said output leads to attenuate some harmonics of the frequency, f, and having a pass band with an upper cutoff frequency larger than f and lower than f0 Nf, where N is a prime number having an order number N0, where prime numbers 1, 2, 3, 5, 7, etc., have order numbers 1, 2, 3, 4, 5, etc., No being defined by N0 no+ 3

5. The invention as defined in claim 4, wherein said control means includes means to adjust the time widths of all of said portions simultaneously.

8. An inverter comprising: first and second input leads; first and second output leads; a first switch connected from said first input lead to said first output lead; a second switch connected from said first input lead to said second output lead; a third switch connected from said second input lead to said first output lead; a fourth switch connected from said second input lead to said second output lead; first means actuable to close said first and fourth switches periodically for overlapping periods of time while both of said second and third switches are open; second means actuable to close said second and third switches periodically for overlapping periods of time while both of said first and fourth switches are open; a clock pulse generator; a pulse counter connected from said clock pulse generator; a plurality of AND gates connected from said counter to produce outputs at different corresponding counts of said counter; third means responsive to the output of said counter to reset said counter each time it arrives at the same first predetermined count; fourth means including a bistable device and responsive to the output of said counter for changing states each time said counter arrives at the same second predetermined count; an OR gate connected from the outputs of a plurality of said AND gates to said first and second means, said first and second means both being responsive to the output of said device and actuable thereby to supply actuating voltage pulses to corresponding pairs of said switches at times corresponding the different actuating outputs of said OR gate, said device deactuating said first means and actuating said second means during alternate periods of time, and actuating said first means and deactuating said second means during the remaining periods of time all of said periods of time being equal in length, the end of each period being coincident with the beginning of the next.

9. The invention as defined in claim 8, wherein said first and second predetermined counts are each equal to 15, four of said AND gates being adapted to produce an output for counts d, e, f and g, respectively, where d- e h, e- f i, f- g v, h is one of the numbers 3 and 5, h 3 only when i 2 and v 3, i 2 only when h 3 and v 3, and v 3 only when h 3 and i 3, h 5 only when i 4 and v 5, i 4 only when h 5 and v 5, and v 5 only when h 5 and i 4.

10. An inverter comprising: first and second input leads; first and second output leads; a first switch connected from said first input lead to said first output lead; a second switch connected from said first input lead to said second output lead; a third switch connected from said second input lead to said first output lead; a fourth switch connected from said second input lead to said second output lead; a clock pulse generator; a delay device connected from said clock pulse generator; a digital counter adapted to count the output pulses of said delay device; first, second, third and fourth AND gates connected from said counter to produce outputs on the counts of 0, 3, 5, and 8, respectively; a fifth AND gate to reset said counter at the end of the 15th count, said fifth AND gate also being connected from the output of said delay device; an OR gate connected from the outputs of said first, second, third and fourth AND gates; a sixth AND gate connected from the outputs of said delay device and said OR gate; a first flip-flop having a set 1 input, a set 0 input, a 1 output, and a 0 output; seventh and eighth AND gates connected, respectively, to the set 1 and set 0 inputs of said first flip-flop, the output of said fifth AND gate being connected to The input of each of said seventh and eighth AND gates, the 1 output of said first flip-flop being connected to the input of said eighth AND gate, the 0 output of said first flip-flop being connected to the input of said seventh AND gate second and third flip-flops each having a 1 output, the 1 output of said second flip-flop being connected to said first and fourth switches, the 1 output of said third flip-flop being connected to said second and third switches, said second flip-flop having a set 1 and set 0 inputs, said third flip-flop having set 1 and set 0 inputs; ninth and 10th AND gates connected to the set 1 inputs of said third and fourth flip-flops, respectively, the output of said sixth AND gate being connected to the input of each of said ninth and 10th AND gates, the 1 output of said first flip-flop being connected to the input of said ninth AND gate, the 0 output of said first flip-flop being connected to the input of said 10th AND gate; and an adjustable monostable multivibrator connected from the output of said clock pulse generator, said multivibrator having a 0 output connected to the set 0 input of each of said second and third flip-flops.

11. An inverter comprising: supply means actuable to produce repeatedly positive and negative sets of pulses, none of said pulses being overlapping, the first pulse in each positive set being spaced from the first negative pulse by a period of time equal to T/ 2, the first pulse of each positive set being spaced from the first pulse in the next succeeding positive set by a period of time equal to T, the position of the second, third, etc., pulses in any one negative set relative to the first pulse in the same said one negative set being substantially identical to the positions of the respective corresponding second, third, etc., pulses in any one positive set relative to the first pulse in the same said one positive set, each of said sets having the same number of pulses, 2n , where no is any positive integer larger than unity, each set including at least one group of four pulses, the first pulse of said one group being the first pulse of that particular set which includes said one group, the second pulse in said one group being spaced from said first pulse in said one group a time aT/ 30, where a is one of the numbers 3 and 5, the third pulse in said one group being spaced from said second pulse therein a time bT/ 30, where b is one of the numbers 2 and 4, the fourth pulse in said one group being spaced from said third pulse therein a time aT/ 30, a being equal to 3 only when b is equal to 2 and vice versa, a being equal to 5 only when b is equal to 4 and vice versa.

12. The invention as defined in claim 11, wherein said supply means includes means to adjust the time widths of all of said pulses substantially simultaneously.

15. The invention as defined in claim 11, wherein each said set has only two groups of pulses, the positions of the second, third and fourth pulses of said other group relative to the position of the first pulse of said other group being the same as the respective corresponding positions of the second, third and fourth pulses of said one group relative to the first pulse of said one group, the first pulse of said other group being spaced from the first pulse of said one group a time mT/ 14 where m is any positive odd integer not 7 or a multiple thereof.

17. The invention as defined in claim 16, wherein m equals unity.

18. The invention as defined in claim 11, wherein each said set has only said one group and one other group of pulses, the positions of the second, third and fourth pulses in said other group relative to the first pulse also being jT/ 30, kT/ 30 and jT/ 30, respectively, where j is one of the numbers 3 and 5, and k is one of the numbers 2 and 4, j being 3 only when k is 2 and vice versa, j being 5 only when k is 4 and vice versa.

19. The invention as defined in claim 18, wherein the first pulse of said one group is the first pulse of the set including said one group, a being equal to 3, b being equal to 2, j being equal to 5, and k being equal to 4, the first pulse of said other group in the selfsame set lagging the first pulse in said one group by a time T/70(3 + 10p), where p is any positive integer, the amplitudes and pulse widths of the pulses in said one group all being the same, the amplitudes and pulse widths of all the pulses in said other group all being the same, the amplitudes and pulse widths of all of said pulses being such that the following expression is equal to unity where, E2 is the amplitude of said one group of pulses, E1 is the amplitude of said other group of pulses, 2 is the pulse width of said one group of pulses, and 1 is the pulse width of said other group of pulses.

20. The invention as defined in claim 18, wherein the first pulse of said one group is the first pulse of the set including said one group, a being equal to 5, b being equal to 4, j being equal to 3, k being equal to 2, the first pulse of said other group in the self same set lagging the first pulse in said one group by a time T/70(7+ 10q), where q is any positive integer, the amplitudes and pulse widths of the pulses in said one group all being the same, the amplitudes and pulse widths of all the pulses in said other group all being the same, the amplitudes and pulse widths of all of said pulses being such that the following expression is equal to unity where, E1 is the amplitude of said one group of pulses, E2 is the amplitude of said other group of pulses, 1 is the pulse width of said one group of pulses, and 2 is the pulse width of said other group of pulses.