US3603967A - Character generator - Google Patents
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- US3603967A US3603967A US820118A US3603967DA US3603967A US 3603967 A US3603967 A US 3603967A US 820118 A US820118 A US 820118A US 3603967D A US3603967D A US 3603967DA US 3603967 A US3603967 A US 3603967A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
- G09G1/08—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system
- G09G1/10—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system the deflection signals being produced by essentially digital means, e.g. incrementally
Definitions
- CHARACTER GENERATOR ABSTRACT A character generator IS described for produc- 36 Claim, 25 D aw g "3 s mg deflection of a beam in a cathode-ray tube to generate [52] Us. CL 340/324 A, selected characters on i screen Deflection information 315/18 315/30 representing the selected character is generated by a set of [SI] llll. CL i G06! 3/14 wires (one set for each character) wsmnd on a series of [50] 340/3241, netic cores and is read out by sequential cncrgization f the 324 A cores. The signals produced by the set are utilized to control charging circuits which produce constant current output [56!
- R'lem CM signals of appropriate sign representing increments of beam UNITED STATES PATENTS deflection to generate the selected character.
- 340/324 X signals are accumulated by a pair of storage means which are 2,931,022 3/1960 Triest 340/324 respectively adapted for connection to the horizontal and vet- 3,222,667 12/1965 Woroncow et 340/324 tical deflection means ofthe cathode-ray tube.
- FIGJB X DEFLEGTION VOLTAGE Y DEFLECTION VOLTAGE 3 n 1 5
- PATENTEUSEP 'HQTI 3 03,957
- This invention relates to character generators for use with cathoderay tubes having deflection plates or deflection coils. More particularly, the invention relates to a character generator which generates deflection voltages for cursively writing characters. rather than deflection voltages representative of a raster scan or other type of fixed pattern scan.
- Cathode-ray tubes are frequently utilized in connection with electronic computers for providing a display of information representative of the output of the computer. Synthesis of characters by providing appropriate deflection voltages to suitable deflection devices in a cathode-ray tube may be accomplished by several different techniques. One such technique involves causing the cathode-ray tube to be deflected through a raster scan or other type of fixed pattern scan which is the same for all characters. The cathode-ray tube beam is allowed to impinge upon the tube screen only at certain times during the scan, such as by appropriate variations of grid voltage, depending upon the particular character being generated. This character generation technique has the disadvantage that a fixed and relatively long period of time is required for each character, irrespective of the complexity or simplicity of the character being generated. Thus a considerable amount of time is wasted due to the necessity of completing the full scan for each character.
- Such generators also incorporate logic circuitry utilizing analytic techniques for producing the required deflection voltages from the information in the storage devices.
- Such character generators require a relatively large number of devices or a complex wiring pattern and as the number of characters or the complexity of the charucters increases, a corresponding increase in the complexity of the character generator results.
- such types of character generators sometimes suffer from poor character registration, uneven intensities and discontinuities between various parts of characters, and are typically limited in the available character styles which may be produced.
- many known information storage and readout systems for character generators are subject to undesired interference from signals representative of unselected characters.
- Another orject oi" the in ention is to provide a character generator in whicn the required number of components per character is reduced over heretofore known devices of corresponding capability.
- a further object of the invention is to provide a character generator which u ilizes a simple and low cost means ofinformation storage.
- Still another object of the invention is to provide a character generator in which character selection is accomplished with minimal interference from unselecctl charac ers.
- FIG. 1 is a block diagram of a character generator constructed in accordance with the invention and illustrating, schematically, a cathode-ray tube used in connection therewith;
- FIG. 2 is an illustration of the character G as formed by utilizing the character generator illustrated in FIG. I as a dottype generator;
- FIG. 3 is a series of graphs illustrating the operation of the character generator of FIG. I in producing the character 6 as illustrated in FIG. 2;
- FIG. 4 is an illustration of a dot sequence of tin: character V produced by the character generator of FIG. 1 utilized as a dot-type generator as it would appear on the cathode-ray tube screen (a) without the proportioning circuit, and (h) with the proportioning circuit;
- FIG. 5 is a circuit diagram of part of the apparatus as FIG I in a configuration for dot-type character generation
- FIG. 6 is a circuit diagram illustrating a stage in one type of pulse generator which may be utilized in the character genera tor of FIG. 1;
- FIG. 7 is a circuit diagram of an intensity circuit as used in the character generator of FIG. I for dottype character generation
- FIG. 8 is a circuit diagram of an enlarging circuit as may be used in the character generator of FIG. 1;
- FIG. 9 is a circuit diagram of a diminishing circuit which may be used in the character generator of FIG. 1;
- FIG. I0 is a circuit diagram of a clamp circuit which may he used in the character generator of FIG. I;
- FIG. 11 is a diagram illustrating the available strokes when the character generator of FIG. I is utilized as a strnlw ype character generator;
- FIG. 12 is an illustration of the letter L as fo med by ut
- FIG. I3 is a series of graphs illustrating the operation of the character generator of FIG. I as a stroke-ty e generator to produce the letter C as illustrated in FIG. I2;
- FIG. 14 is a circuit diagram of a portion of an cttcmfilly timed sequential pulse generator which may used in the character generator of FIG. 1;
- FIG. 15 is a circuit diagram of a portion ofa charging circuit which may be utilized in the character generator of FIG. I for producing characters by the stroke type generation illttsli'alrri in FIGS. 12 and 13;
- FIG. 16 is a circuit diagram of an intensity circuit as may be utilized in the character generator of FIG. 1 for stroke-type character generation of characters as illustrated in FIGS 12 and 13;
- FIG. 17 is a block diagram of another embodiment oi" the in vention.
- FIG. I8 is a block diagram of a further embod ment of the invention.
- FIG. 19 is a diagram illustrating the available s rokes in the embodiment of FIG. I8;
- FIG. 20 is a circuit diagram of a charging current generator which may be utilized in the embodiment of FIG. 18.
- FIG. 21 is a circuit diagram of a brightness compensating circuit which may be utilized in the embodiment o FIG. 18;
- FIG. 22 is a block diagram of a code converter suitable for use in the character generator of FIG. IS;
- FIG. 23 is a block diagram of a gated clock generator which may be employed to drive any of the cha acter generators described herein;
- FIG. 24 is a circuit diagram of a buffer amplifier which may be used to drive electromagnetic deflection yokes if the latter are used in place of electrostatic deflection plates to produce deflection fields;
- PK ⁇ . 25 is a circuit diagram of a deflection yoke driver for use with the circuit of FIG. 24.
- the character generator of the invention comprises a plurality of magnetic cores 11 and means 12 for sequentially energizing such cores. (See HO. 1.)
- a set of wires 13 is provided for producing information to generate a predetermined character. Respective wires in each set are wound on selected cores to produce. upon energization of the cores, pulses representative of incremental changes in beam deflection.
- Charging means 14 are provided for receiving the pulses produced in the wires upon energization of the cores. The charging means produce constant current output signals each of a predetermined duration corresponding to an increment of X' or Y-axis deflection.
- Storage means 16 and 17 are connected to the charging means to receive and accumulate the output signals supplied thereto from the charging means, thereby producing deflection voltages corresponding to the sum of the X- and Y-axis deflection increments. respectively.
- the storage means 16 and 17 are adapted for connection to the X-axis and Y-axis deflection means, 18 and 19, respectively, of a cathode-ray tube 21, to apply X-axis and Y-axis deflec tion voltages to the deflection plates.
- Information for each character is generated in a respective one of a plurality of sets of wires 13.
- wires 13 there are three wires in each set, only one set being illustrated.
- One wire generates X-axis deflection voltage information in accordance with the manner in which it is wound or not wound on each of a series of magnetic cores 1]. When the cores are closed rings, threading the wire through selected cores is sufficient to generate deflection information.
- a second wire generates the Y-axis deflection voltage information in the same manner.
- a third wire is utilized for some characters for which it is necessary to generate information indicating when the electron beam of the cathode-ray tube 21 is to be blanked during part of the character generating period; e.g. to prevent tracing the same segment of the character twice.
- Pulses representative of incremental changes in beam deflection, and blanking or unblanking of the electron beam, are produced by sequentially energizing the cores ll. lf a wire is wound on a particular core, when the core is energized a pulse is produced in that wire, the polarity of the pulse depending upon the direction with which the wire is wound.
- the sequential pulse generator 12 is utilized to energize the cores 11 sequentially.
- the circuitry for the sequential pulse generator may be of any suitable type, and specific types of circuits which may be utilized are shown in FIG. 6 and are described in detail subsequently.
- the sequential pulse generator may comprise a plurality of blocking oscillators, each connected to provide an output pulse for energizing one of the cores and for triggering the next succeeding blocking oscillator.
- Each magnetic core 11 may comprise the core of the blocking oscillator transformer, thus providing a substantial saving in the number of parts required.
- the sequential pulse generator may be timed with a suitable external clock oscillator, not illustrated in FIG. 1.
- the number of magnetic cores utilized determines the total number of available dots or stokes, and this may be varied to suit requirements. It has been found that a series of 18 to 20 cores provides a satisfactory number of dots or strokes, plus pulses indicative of starting and stopping each character as described below.
- the particular set of wires for the production of the desired character which it represents is selected by character selection logic 22 which is coupled to one end of each set of wires.
- the character selection logic receives information on the character to be selected from a computer, not shown.
- the end of each set of wires opposite the character selection logic is connected to gates 23, 24 and 26 for the X-axis deflection, Y- axis deflection and beam intensity functions, respectively.
- the gates 23, 24 and 26, as will be explained below, comprise OR gates which pass the outputs of a selected set of wires in response to appropriate operation of the character selection logic.
- the energizing pulses applied to each core by the sequential pulse generator 12 are so shaped as to result in the production of a single trigger pulse in each wire wound on that core for each core energization.
- the polarity of the trigger pulses depends upon the direction in which the wire is would on the core.
- the outputs of the X-axis deflection gate 23 and the Y-axis deflection gate 24 are applied to the charging means 14.
- the charging means operate in response to such trigger pulses to produce constant current output signals representative of increments of horizontal and vertical deflection.
- the charging means 14 include an X-axis pulse detector 27, a Y-axis pulse detector 28, a positive X-axis charging circuit 29, a negative X-axis charging circuit 31, a positive Y-axis charging circuit 32, and a negative Y-axis charging circuit 33.
- the X-axis pulse detector 27 separates trigger pulses applied to it from the gate 23 (such pulses being produced in the uppermost of the wires 13 and being representative of increments of X-axis deflection) and applies the positive pulses to the positive X-axis charging circuit 29 and applies the negative pulses to the negative X-axis charging circuit 31.
- the Y-axis pulse detector 28 applies positive pulses to the positive Y-axis charging circuit 32 and negative pulses to the negative Y-axis charging circuit 33, depend ing upon the polarity of trigger pulses applied to the pulse detector 28 from the gate 24, such pulses being produced in the middle one of the wires 13.
- a circuit which may be employed for the charging means is shown in FIG. 5 and is described in detail hereinafter.
- the output signals of the charging means 14 which represent increments of X-axis deflection, namely, the outputs of the positive X-axis charging circuit 29 and the negative X- axis charging circuit 31, are accumulated in a storage capacitor 16. Each incremental signal is a constant current pulse ofa predetermined duration; i.e. an increment of charge.
- the output of the charging means 14 representing increments of Y-axis deflection namely the outputs of the positive Y-axis charging circuit 32 and the negative Y-axis charging circuit 33, are applied to a storage capacitor 17.
- a clamp circuit 35 operates at the end of the generation of each character to clamp the voltage on each storage capacitor 16, 17 to a starting or reference level before beginning the generation of the next character.
- the charge accumulated in each of the respective storage capacitors l6 and 17 is equal to the sum of the increments of charge applied thereto from the charging means.
- the voltage across each capacitor is proportional to the charge stored therein, and the capacitor voltages are applied across the X-axis and Y-axis deflection plates 18 and 19, respectively, in the cathode-ray tube 21.
- the cathode-ray tube 21 is also provided with a beam position deflection yoke 34 for positioning the traced characters at a desired region of the cathode-ray tube screen 36.
- the electron beam is produced by a cathode 37, and is directed to the screen 36 by suitable accelerating elements, not shown.
- a grid 38 is provided for controlling the intensity of the beam, and suitable changes in bias may be produced on the grid to blank or unblank the electron beam as desired.
- Such changes in grid bias are produced by an intensity circuit 39, coupled to the grid 38, As previously mentioned, the intensity circuit is controlled for blanking and unblanking the beam for those characters which so require it by means of a third wire in the set of wires l3, Trigger pulses produced in the third wire are applied through a gate 26 to the intensity circuit 39 to control operation thereof.
- the character generator is operated as a dot-type generator. eam position is changed very quickly while blanked, and the beam is then unblariked while stationary to produce a dot on the screen 36 at a desired position.
- the characters are thus formed by a plurality of closely spaced dots.
- the intensity circuit 39 provides periodic unblaiilt signals to the cathode-ray tube grid 38, which are spaced and which are of a length such that the beam is unblanked at the successive positions to which the beam is deflected.
- the pulses produced in the third wire are utilized in the intensity circuit to prevent an unblanking output from being applied to the grid 38, thus leaving the beam blanked in those positions. Details of circuitry for accomplishing the foregoing functions are shown in FIG. 7 and art; described below.
- the intensity circuit 39 provides a con tinuous bias n the grid 38 to maintain the beam unblanked at all times except during the times that blank sections are required; cg. to prevent tracing the same stroke twice.
- the output signals for stroke-type generation from the charging means i4 are igiinstant currents which continue for the full period of each stroke, The accumulation of charges in the storage capacitors during each period results in ramp-type voltage signals which thereby cause the characters to be generated by a series of lines or strokes produced on the screen 36 iii the cathode-ray tube 21.
- the appropriate pulses produced in the third wire of the set are applied through the gate 26 and are utilized by the intensity circuit to change the bias or the grid 33 to blank the cathode-ray tube beam. Details oi tt rllultl'y for accomplishing the foregoing functions are shown in FIG 16 and are described below.
- Some cl'iaracters when properly proportioned, require larger or iil liill ii' rements in one axis than in the other axis, or a larger or am i r dimension in width or height than other characters, i nosicAlI'ilClCfS requiring a change in proportion from the standard tililf'ii ll tr size are affected by the proportioning circuit M which is energized by the character selec tion logic circuit :it th same time the character is selected.
- the proportioning circuit is so constructed to enlarge or diminish the dimension of the character being generated along the X-aizts or the Y .i iris, depending upon which is appropriate, by the subtraction or addition of a suitable amount of capacitance iii the storage provided by the capacitor 16 or 17.
- the proportioning circuit is also connected to the intensity circuit 39 lor reasons explained below. Details of circuitry which may hi. used as the proportioning circuit are shown in FIG. 8 and FIG. 9 and are described below,
- Graph A. of H6. 3 indicates the available pulse times and Graphs B and C indicate the possible pulses utilized, and the polarity of pulses utilized, in the X-axis and Y-axis wires, :espcctiveiy As previously mentioned, the generation ofa pulse and its polarity is determined by the winding of the wires on the cores.
- the dots I through 5 in FIG. 2 are formed by varying the Y- axis deflection voltage while holding the X-axis deflection voltage constant. This may be seen by comparison of Graphs D and E in FIG. 3.
- the step voltage characteristic is achieved by suitable short duration constant current output signals such as may be produced in a blocking oscillator. and by feeding such signals to the storage capacitors l6 and 17.
- the constant current output signals are fed to the storage capacitors for a fixed, predetermined time which is much shorter than the intervals between steps.
- the time is established by the blocking oscillator period and may, for example, be about 0.2 microsecond. Thus, the time required to move the beam from one dot position to the next is about 02 microsecond.
- the period for sequential energizations of the cores may bit set at about 0.7 microsecond, and thus the beam may be left on for the remaining 0.5 microsecond to define a bright dot on the target screen. This is indicated by the Graph F. showing the production of successive intensity signals.
- Xaxis deflection begins to direct the beam to the positions 6, 7, 8 and 9.
- no change in Y-axis deflection voltage occurs, as may be oh served from the graphs.
- positions 9 and 11 no change in X-axis deflection occurs, while the Y-axis deflection voltage decreases in stepwise manner through the application of negative constant current signals to the storage capacitor.
- the production of dots l0 and 11 is prevented by the genera tion of a blanking pulse in the third wire indicated in the Graph G of FIG. 3.
- circuitry which may be employed in the character generator of the invention for operating it as a dot-type character generator. Only circuitry for the generation of the X-axis deflection voltage is illustrated, however, it is to understood that the circuitry for generation of the Y-axis deflection voltage is similar.
- the character seicction logic 22 includes a plurality of selection circuits, each comprising a pair of resistors 42 and a capacitor 43 connected to a common junction 45, to which one end of each wire in an associated set is also connected. The capacitor 43 is grounded and the resistors are connected to individual input points 44., to which the remaining portion, not illustrated, of the character selection logic 22 is connected.
- the remaining unillustrated portion of the character selec tion logic 22 may be any suitable circuit which will bring both input points 44 to a positive potential (for exam le, +5 volts each) when that particular character is selected, and which will maintain either a zero voltage on both of th input points, or a positive voltage on one and a zero voltage on the other, when that particular character is not to be selected,
- One particular satisfactory form of character selection logic may provide a character repertory of 64 characters, selected by six binary coded signals (six bits in parallel). As is known in the art, the six bits can be combined to produce 64 possible signals (2). Combining may be done in two stages, a first stage dividing the six bits into two groups of three each.
- Each group of three can be combined into eight possible combinations in the first combining stage.
- the 16 signals may be then combined to produce 64 unique signals, in the second combining stage, by means of 64 selection circuits, each consisting of a pair of resistors and a capacitor as described in connection with the resistors 42 and the capacitor 43.
- 64 selection circuits each consisting of a pair of resistors and a capacitor as described in connection with the resistors 42 and the capacitor 43.
- the opposite ends of the wires in each set are connected to the gates 23, 24 and 26, respectively.
- the gate 23 consists of a plurality of diodes 46 (64 diodes for 64 characters are used with character selection logic of the type described in the example, above), the outputs of the diodes being tied together and coupled to the X-axis pulse detector 27.
- the X-axis pulse detector 27 includes a transistor 47 having a collector connected through a resistor 48 to a source of potential. The collector is also connected through a capacitor 49 to ground. When a character is selected, its selection junction 45 rises to a positive potential; e.g. volts.
- the particular one of the diodes 46 connected to the wire of the selected character is forward biased by the character selection logic 22 and causes the base of the transistor 47 to rise nearly to the positive potential of the selection circuitjunction 45 to which it is connected.
- the transistor under such conditions, is biased well into conduction.
- All of the other selection circuits are placed, by the character selection logic 22, in a condition such that the voltage at the particular selection junction is at either 0 or one-half that at the junction in the selected selection circuit; e.g. at 0 volt or volts.
- the other diodes in the gate 23 are back biased; e.g. each diode has its cathode at nearly +5 volts and its anode at either 0 volt or +2.5 volts.
- pulses produced in the coding wire are passed by the associated diode. Such pulses may be positive or negative with respect to the bias level, depending upon the way the wire is wound on the cores.
- a pulse on a selected wire which occurs when a given core ll is energized is positive if the wire is wound on that core in one sense, and negative if wound in the other sense.
- the pulses on the selected wire cause the transistor to produce pulses of corresponding polarity superimposed on its steady output resulting from the bias voltage.
- the emitter of the transistor 47 is connected through a resistor 52 and parallel capacitor 51 to a winding 53 which surrounds a portion of a magnetic core 54.
- the magnetic core 54 has a pair of output windings 56 and 57 which produce output pulses in response to pulses in the winding 53.
- a satisfactory series of pulse configurations may be achieved by designing the sequential pulse generator 12 to produce square wave pulses of, for example, 0.6-microsecond duration. At the end of the 0.6-microsecond period, a sharp 0.2-microsecond overshoot pulse is utilized to trigger the next succeeding stage in the sequential pulse generator. A circuit for accomplishing this is illustrated in FIG. 6 and is described in detail subsequently in this specification.
- the resulting form of trigger pulses produced in the wires wound on the energized cores, such pulses being amplified by the transistor 47, are indicated adjacent the resistor 52in Fit]. 5.
- either the upper pulse or lower complementary pulse is produced upon the energizing of that core.
- the winding 56 is connected across the base and emitter of a PNP transistor 58 through a capacitor 59.
- the transistor 58 is a pulse amplifier for driving the positive X-axis charging circuit 29.
- a biasing network comprised of resistors 61, 62 and 63 is provided, coupled to a suitable source 60 of positive potential, and is designed to bias the transistor 58 near cutoff.
- the winding 57 is connected to a pulse amplifier including a transistor 58a for driving the negative X-axis charging circuit 31, which is identical with that of the positive X-axis charging circuit 31. Since both pulse amplifiers are PNP transistors, they trigger only on negative pulses applied to their bases.
- each time the core 54 is pulsed only one of the two output pulses in the respective windings 56 and 57 will be of a polarity to trigger the associated pulse amplifier transistor.
- the particular transistor which is triggered thereby depends on the polarity of the pulse in the winding 53.
- the collector of the transistor 58 is grounded through a resistor 64, and provides an output pulse to the positive X-axis charging circuit 29, when a positive pulse is received by the gate 23 from a wire 13.
- the collector of the transistor 58a provides an output pulse to the charging circuit 31 when a negative pulse is received by the gate 23, in a similar manner.
- the pulse from the transistor 58 is coupled through a capacitor 66 to the base of an NPN transistor 67.
- the base of the transistor 67 is grounded through a resistor 68 and a parallel connected diode 69.
- the transistor 67 is connected as a blocking oscillator, having a collector winding 71 with a parallel resistor 72 and having an emitter winding 73.
- a pair of resistors 74 and 76 connect a source 70 of positive potential to ground and the coil 73 is connected to the juncture between such resistorsv
- the coil 7] is connected to a further source 75 of positive potential, and the coils 71 and 73 have a common core.
- the blocking oscillator is emitter coupled and provides a constant voltage output pulse in the secondary winding 77.
- the secondary winding 77 is connected to provide a potential difference to the base-emitter circuit of a constant current NPN transistor 78.
- the transistor 78 has its base connected to one end of the winding 77, and its emitter connected through an emitter resistor 79 to the other end of the winding 77.
- the constant current output of the transistor 78 is coupled to the storage capacitor 16.
- the collector of the transistor 78 is connected to a source 80 of positive potential which is higher than the maximum deflection voltage to be produced across the X- axis deflection plates of the cathode-ray tube.
- the first stage of the negative X-axis charging circuit 31 is identical with the first stage of the positive X-axis charging circuit 29 and similar parts are indicated with the same reference numeral and the subscript a.”
- the blocking oscillator of the negative X-axis charging circuit 31 operates to provide a constant voltage output signal by producing a signal of appropriate duration in the output winding 81 of the blocking oscillator.
- the output stage of the negative X-axis charging circuit includes a constant current transistor 82 having a current-determining emitter resistance consisting of a fixed resistor 83 and a variable resistor 84 connected to ground, and having its collector coupled to the storage capacitor 16.
- both the positive and negative incremental changes in the X- axis deflection voltage are determined by means of constant positive or negative currents fed to the capacitor for a fixed time predetermined by the time period of the blocking oscillator in the charging circuits.
- stage which may be incorporated in the sequential pulse generator 12 is illustrated.
- Such a pulse generator stage is capable of producing the square-wave-with-overshoot pulses previously described. It is to be understood, however, that the invention is not limited to the use of such a type of pulse generator or pulse configuration. Only one stage is shown in FIG. 6 and will be described, since it is to be understood that all stages are identical.
- a positive going signal from the next preceding stage or from a suitable start pulse circuit, not shown, is applied at the terminal 86.
- the terminal 86 is connected through a differentiating circuit including a capacitor 87 and a resistor 91.
- a diode 88 couples the differentiated signal to the base of an NPN transistor 89, the emitter of which is coupled through a resistor 92 to ground.
- the base of the transistor 89 is also coupled to ground through one winding 93, a feedback winding of a blocking oscillator transformer.
- the other winding 94 of the transformer is connected to the collector of the transistor and to a suitable source of positive potential 95.
- the winding 94 is also connected across a further winding 96 through a resistor 97 and a diode 98.
- the further winding 96 is wound on the associated core 11, upon which are also wound the wires 13.
- the collector of the transistor 89 is also connected to the next succeeding stage.
- the foregoing circuitry thereby operates as a base coupled blocking oscillator, providing output pulses to energize the associated core 11, and to also trigger the next succeeding stage.
- the base then returns toward potential, which causes the collector current to be reduced, which drives the base further negative, so that collector current is rapidly cut off by a regenerative "off" action.
- the sudden interruption ofcollector current causes a positive going voltage step at the collector. Since the energy stored in the core of the transformer during the 011" interval of the blocking oscillator must be dissipated, the voltage at the collector overshoots, or wings to a potential more positive than the terminal 95, and current is forced to flow through the diode 98, the winding 96 and the resistor 97. Part of the energy stored in the blocking oscillator transformer core thus is transferred to the core 11, magnetizing it and producing the desired information pulses in the wires I3, while another part is dissipated in the resistor 97.
- the time constant of the overshoot interval of the period is made small, by choosing a low value for resistor 97, so the pulses generated in wires l3 are short, e.g. about 0.] psec.
- a signal is generated across resistor 92, which is proportional to emitter current.
- This signal is a ramp voltage superimposed on a pedestal, and is coupled to terminal 99,
- the signals at terminal 99 in the first and last blocking oscillators of the sequential pulse generator 2 are used in the intensity circuit 39, as will be explained h reafter, while the terminals 99 in the intervening stages are not used.
- the positive going step in the collector voltage at the end of the on interval of the transistor 89 is coupled to the input trigger terminal 86 ofthe next stage, to initiate its action.
- FIG. 7 An intensity circuit, which may be utilized in the character generator of HG I when the character generator is operated as a dot-type character generator, is illustrated in FIG. 7.
- the circuit includes a flip-flop comprised of a pair of NPN transistors l0! and HI? connected in appropriate fashion by a plurality of resistors, capacitors and diodes.
- the emitters of transistors 101, 102 are connected to a source of positive potential +V1, while the collectors are coupled to a more positive potential +V2. Ground potential can then be coupled to the bases through suitable bias resistors.
- An initiating signal from the emitter circuit (terminal 99) of the first stage in the sequential pulse generator 12 (FIG. 1) is applied to the unblank terminal 103 of the intensity circuit (FIG. 7).
- the initiating signal is applied to the base of one transistor 102 of the flip-flop through a capacitor 104 and a steering diode 106.
- the first sequential pulse generator stage pulses, its emitter output signal sets the flip-flop to provide an output signal through a series resistor 107 to a buffer amplifier in cluding an NPN transistor 108.
- the output signal provided through a resistor I09 from the transistor 108 is a s uare wave having substantial length, rather than a short pulse, and serves to enable or disable an unblank blocking oscillator which provides intermittent signals for unblanking the cathode-ray tube beam at appropriate times.
- the blocking oscillator is emitter coupled and includes an NPN transistor 11] having an emitter winding 112 and a collector winding 113.
- the emitter winding is connected to the resistor 109, and also to a source of positive potential through a resistor 110.
- the collector winding 113 is connected to a source 105a of positive potential which is higher than the source 105.
- a series connected diode 115 and damping resistor 1I4 are connected in parallel with the winding 113.
- output signals from the charging cir cuits are connected through an OR gate consisting of four diodes 116.
- the output signals are obtained from the emitter circuits of the charging circuit blocking oscillators; e.g trr minals 75, 85 in FIG. 5.
- the diodes 116 are slightly back biased by a source 117 of positive potential connected to their cathodes through the parallel combination of a resistor H8 and a capacitor 119. At each timing interval (see Graph A, FIG.
- a pulse will be passed by the OR gate diodes 1 I6, since a pulse sufficient to overcome the hack bias is present in at least one of the four charging circuit outputs.
- This pulse is applied to the base of the transistor 11] through a resistor 121 and parallel capacitor 122.
- the pulse applied to the base of the transistor is a positive going pulse and triggers the blocking oscillator (providing it is in the enabled condition). A pulse is therefore produced in the output winding 124 of the blocking oscillator.
- the pulse produced in the output winding E24 is coupled across the emitter and base of a PNP Quip-.1! transistor I26 through a resistor [27.
- the output of the transistor I26 is developed, from a source 125 of positive potential tied to the emitter, across a load resistor 128 in the collector circuit and applied to the cathoderay tube grid.
- the circuitry may be designed such that the blocking oscillator produces a negative going rectangular pulse nominally about 0.3 microsecond in width and 9 volts in magnitude at the collector of the transistor 111, with a positive overshoot lasting about 0.3 #sec.
- a wave of the same shape, but inverted and about one-quarter of the magnitude appears at the upper end of the output winding and couples to the base of the output transistor [26.
- the output transistor is normally off (at t) bias) and is turned farther off by the positive rectangular pulse (dur ing the transition time between spot positional.
- the output transistor 126 clips and amplifies and inverts the negative overshoot, producing a short positive unblank pulse at its collector. This pulse is applied to the grid of the cathode-ray tube for unblanking the beam.
- the circuit of FIG. 7 represents a simple embodiment of the intensity circuit 39 which can be used in the character generator of FIG. 1.
- the delay period and unblank period can be controlled independently.
- the delay period to allow for transition of the spot can be reduced to 0.2 used, or any other desired interval by proper design and adjustment of the first blocking oscillator.
- the unblank interval can be increased to 0.5 sec, or any other desired interval, by proper design and adjustment of the second blocking oscillator, as is well known in the art.
- the flip-flop 101-102 is placed in the reset or disabling condition, as described below, when certain dots are not to appear on the cathode-ray tube screen.
- the reset condition corresponds to conduction of transistor 101.
- the buffer amplifier transistor 108 conducts heavily from the positive voltage source at its collector through the resistor 109 and the further resistor 110 to the lower potential source 105 to which the resistor 110 is connected.
- the current through the resistor 110 causes the blocking oscillator transistor 11] emitter to rise to a substantially more positive potential than its base. Hence, triggering of the blocking oscil lator by pulses from the diodes 116 is prevented.
- the flip-flop 101,102 is controlled by blank and unblank pulses produced in the third line or wire. Such pulses are applied through the OR gate 26 to a twostage amplifier.
- the two-stage amplifier is comprised of a pair of NPN transistors 131 and 132 connected by suitable biasing tesistors and capacitors respectively in an emitter follower configuration and a grounded emitter configuration.
- Such pulses are applied to the flip-flop comprising the transistors 101 and 102 through a capacitor 133, and also through a capacitor 136.
- the first pulse (see FIG. 3 G) operates the flip-flop to the reset or disabling condition, causing the buffer amplifier to disable the blocking oscillator.
- the second pulse sets the flipflop again to a condition wherein the buffer-amplifier enables the blocking oscillator.
- an unblank inhibit pulse is applied to a terminal 138 by the last stage of the sequential pulse generator 12 (FIG. 1). This pulse is applied to the flipflop through a capacitor 139 and operates the flip-flop to the reset or disabling condition when the generation of a character is completed.
- the cathode-ray tube beam is blanked until such time as generation of a new character begins and a pulse is applied to the terminal 103.
- the flip-flop consisting of the transistors 101 and 102, it is possible to generate many types of characters without the necessity of a third wire being threaded through the cores 11. Thus, if no portions of a character are to be blanked or retraced, it is unnecessary to inhibit the output of the blocking oscillator. If the character shape requires a blanked portion or a retraced portion, the third wire need only be threaded through two cores for each blanked segment, rather than threaded to provide blanking pulses for each beam position. Thus, the first pulse produced in the third wire resets the flip-flop (which is initially set upon the production of a pulse in the first core 11) and the second pulse produced sets the flip-fiop once again to a condition for enabling the blocking oscillator.
- the unblank pulse applied by the first sequential pulse generator to terminal 103 and unblank inhibit pulse applied by the last sequential pulse generator to terminal 138 are not both required for operation of the character generator. If the inhibit pulse at terminal 138 is omitted, it is necessary to thread the third wire 13 to generate an additional pulse to blank the cathode-ray tube beam after the last desired dot is produced. Conversely, the unblank pulse to tenninal 103 can be omitted if the third wire 13 is threaded to generate an additional pulse before the first desired dot is produced.
- the third wire 13 may be threaded to produce positive pulses when it is desired to unblank the beam and negative pulses when it is desired to blank the beam.
- the intensity circuit in that event is accordingly modified to include a pulse detector and separator like transistor 47 and core 54 (FIG. with its windings 53, S6, 57. The separated pulses from the two output windings of the core are then used respectively to set and reset the intensity flip-flop via separate steering diodes.
- the intensity circuit 39 may be modified to operate without the flip-flop and without the OR gate comprised of the diodes 116.
- the third wire for each character is threaded through a core for each dot to be brightened.
- the pulses produced in the third wire are then coupled, by suitable amplification, directly to the input of the blocking oscillator.
- FIGS. 8 and 9 illustrate enlarging and diminishing circuits, respectively, which may be utilized as the proportioning circuit 41 in FIG. 1.
- a diode 141 (FIG. 8) is used for each character to be enlarged, and is connected to the input resistor junction 45 for that particular character in the character selection logic 22.
- the plurality of diodes 141 are arranged to form an OR gate and function in a manner similar to the OR gates for the charging means and for the intensity circuit.
- a signal (e.g. +5 v.) is passed by the associated one of the diodes 141 to the base of a first of a pair of NPN transistors 142 and 143 having a common emitter resistor 144 connected to ground.
- the base of the first transistor 142 is also connected to ground through a resistor 146, and the base of the second transistor 143 is connected to ground through a resistor 147.
- the base of the second transistor 143 is also connected through a resistor 148 to a source of positive potential.
- the resistors 147, 148 form a voltage divider which bias the base of the second transistor 143 to a suitable positive potential; e.g. +2.5 volts.
- the collector of the first transistor 142 is also connected to a source of positive potential. Without any positive signal being passed by any of the diodes 141, the first transistor 142 is biased off and the second transistor 143 is biased on.
- a capacitor 149 is connected between the collector of the second transistor 143 and the storage capacitor 16 or 17 for the axis to be enlarged.
- the capacitor 149 is normally (Le. when the second transistor 143 is biased on) in the system and effectively in parallel with one of the capacitors 16, 17; however, when a sufficiently positive signal; e.g. +5 v., is passed by one of the diodes 141, the first transistor 142 is rendered conductive, cutting off the second transistor 143 and, in effect, removing the capacitor 149 from the systemv Accordingly, less storage capacity is present, producing an enlargement of the character.
- an OR gate comprised of a plurality of diodes 151 receives signals from the input resistor junctions 45 for those characters to be diminished, which input junctions are in the character selection logic 22.
- the base of an NPN transistor 152 is connected to the diodes 151 through a resistor 153.
- the base of the transistor 152 is also connected through a resistor 154 to a source of negative potential, and the emitter is grounded. Accordingly, the transistor is normally biased to an off condition. In the presence of a sufficiently positive signal passed by one of the diodes 151, however, the transistor 152 is rendered conductive.
- a capacitor 156 is connected between the collector of the transistor 152 and the storage capacitor 16 or 17 associated with the particular axis to be diminished (normally the X-axis). Accordingly, when the transistor 152 is rendered conductive, the capacitor 156 is added to the system effectively in parallel with one of the capacitors 16, 17, resulting in a diminishing of the character on the associated axis.
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Radar Systems Or Details Thereof (AREA)
- Video Image Reproduction Devices For Color Tv Systems (AREA)
- Details Of Television Scanning (AREA)
Abstract
Description
Claims (35)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US82011869A | 1969-04-29 | 1969-04-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
US3603967A true US3603967A (en) | 1971-09-07 |
Family
ID=25229934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US820118A Expired - Lifetime US3603967A (en) | 1969-04-29 | 1969-04-29 | Character generator |
Country Status (5)
Country | Link |
---|---|
US (1) | US3603967A (en) |
JP (1) | JPS4916206B1 (en) |
DE (1) | DE2020522A1 (en) |
FR (1) | FR2040362A1 (en) |
GB (1) | GB1244949A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4580231A (en) * | 1978-09-15 | 1986-04-01 | Alphatype Corporation | Ultrahigh resolution photocomposition system employing electronic character generation from magnetically stored data |
US4615012A (en) * | 1982-12-09 | 1986-09-30 | Alps Electric Co., Ltd. | Method of generating character patterns |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53116966A (en) * | 1977-03-22 | 1978-10-12 | Takara Thermistor Instr | Reclining lifting seat |
US5924664A (en) | 1997-03-12 | 1999-07-20 | Ergo View Technologies Corp. | Keyboard support mechanism |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2920312A (en) * | 1953-08-13 | 1960-01-05 | Lab For Electronics Inc | Magnetic symbol generator |
US2931022A (en) * | 1954-06-16 | 1960-03-29 | Ibm | Spot sequential character generator |
US3222667A (en) * | 1962-04-24 | 1965-12-07 | Nat Res Dev | Core matrix for control of crt having forward and reverse wound cores |
US3325802A (en) * | 1964-09-04 | 1967-06-13 | Burroughs Corp | Complex pattern generation apparatus |
US3329947A (en) * | 1963-03-07 | 1967-07-04 | Burroughs Corp | Electronic character generator |
US3466612A (en) * | 1966-12-07 | 1969-09-09 | Burroughs Corp | Wired core memory |
-
1969
- 1969-04-29 US US820118A patent/US3603967A/en not_active Expired - Lifetime
-
1970
- 1970-04-07 DE DE19702020522 patent/DE2020522A1/en active Pending
- 1970-04-07 GB GB06323/70A patent/GB1244949A/en not_active Expired
- 1970-04-28 JP JP45036223A patent/JPS4916206B1/ja active Pending
- 1970-04-28 FR FR7015417A patent/FR2040362A1/fr not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2920312A (en) * | 1953-08-13 | 1960-01-05 | Lab For Electronics Inc | Magnetic symbol generator |
US2931022A (en) * | 1954-06-16 | 1960-03-29 | Ibm | Spot sequential character generator |
US3222667A (en) * | 1962-04-24 | 1965-12-07 | Nat Res Dev | Core matrix for control of crt having forward and reverse wound cores |
US3329947A (en) * | 1963-03-07 | 1967-07-04 | Burroughs Corp | Electronic character generator |
US3325802A (en) * | 1964-09-04 | 1967-06-13 | Burroughs Corp | Complex pattern generation apparatus |
US3466612A (en) * | 1966-12-07 | 1969-09-09 | Burroughs Corp | Wired core memory |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4580231A (en) * | 1978-09-15 | 1986-04-01 | Alphatype Corporation | Ultrahigh resolution photocomposition system employing electronic character generation from magnetically stored data |
US4615012A (en) * | 1982-12-09 | 1986-09-30 | Alps Electric Co., Ltd. | Method of generating character patterns |
Also Published As
Publication number | Publication date |
---|---|
JPS4916206B1 (en) | 1974-04-20 |
FR2040362A1 (en) | 1971-01-22 |
DE2020522A1 (en) | 1970-11-12 |
GB1244949A (en) | 1971-09-02 |
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