US3594509A - Delta modulator apparatus - Google Patents

Delta modulator apparatus Download PDF

Info

Publication number
US3594509A
US3594509A US847622A US3594509DA US3594509A US 3594509 A US3594509 A US 3594509A US 847622 A US847622 A US 847622A US 3594509D A US3594509D A US 3594509DA US 3594509 A US3594509 A US 3594509A
Authority
US
United States
Prior art keywords
delta modulator
input
coder
output
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US847622A
Other languages
English (en)
Inventor
Tadao Shimamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Application granted granted Critical
Publication of US3594509A publication Critical patent/US3594509A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/06—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
    • H04B14/062—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation using delta modulation or one-bit differential modulation [1DPCM]

Definitions

  • high-speed delta modulator apparatus wherein a plurality of relatively low speed delta modulator means are arranged so that one of such plurality of low speed delta modulator means adapted to receive an input signal to be modulated while each succeeding one of said plurality of low speed delta modulator means is connected to a preceding one of such plurality of low speed delta modulator means in a manner to receive an error signal therefrom as an input thereto.
  • the plurality of relatively low speed delta modulator means each includes commonly timed coder means whose outputs may be combined in a multiplex manner whereby the resulting modulator apparatus ex- [56] Rderences Cited hibits an equivalent sam lin rate equal to the sam ling rate of P 2 P UNITED STATES PATENTS each of said plurality of relatively low speed delta modulator 2,949,505 8/1960 Kretzmer 179/ 15.55 means multiplied by the number of relatively low speed delta 3,471,648 10/ 1969 Miller 179/ 1 5.55 modulator means present in said plurality.
  • Coder l4 4 Integrator 1 3- b 1 Multiplexing 2 5 15 Means i 3/ r .9 23 Coder Integrator Fig. I.
  • This invention relates to high-speed delta modulation communications systems and more particularly to high-speed delta modulator apparatus therefor.
  • delta modulation communications systems possess a plurality of attractive attributes which render them highly advantageous when compared to other pulse communications systems presently in wide use. For instance, if a delta modulation communications system is compared to the well-known forms of pulse code modulation communications systems which are prevalent today, it will be seen that such delta modulation communications systems possess the marked structural advantage that the modulators and demodulators thereof are substantially simplified as compared to those present in conventional pulse code modulation communications systems.
  • delta modulation communications systems require the use of transmission bands which are wider than those necessitated by other forms of pulse modulation communications systems and that the sampling rate presently required thereby is exceedingly high.
  • the requirements of a wide transmission bandwidth and a high sampling rate are related and result in the uneconomical use of the available transmission band, particularly when the transmission of wide-band signals such as television signals is considered, and complex circuit design criteria, which are often difficult to achieve in conventional modulator apparatus used in conjunction with delta modulation communications systems.
  • conventional communications systems have generally avoided delta modulation techniques so that the more efficient use of the transmission band and the less onerous design criteria of the modulator apparatus used in other forms of modulation communications systems could be employed. Accordingly, despite attractive advantages, delta modulation communications systemshave not played a prominent role in the development of practical, commercial communications systems due to the need for wide transmission bands and high sampling rates which attend their use.
  • modulator apparatus for high-speed delta modulation systems wherein a plurality of relatively low-speed delta modulator means are arranged so that one of such plurality of low-speed delta modulator means is adapted to receive an input signal to be modulated while each succeeding one of said plurality of low-speed delta modulator means is connected to a preceding one of said plurality of low-speed delta modulator means in a manner to receive an error signal therefrom as an input thereto, each of said plurality of relatively low-speed delta modulator means including commonly timed coder means whose outputs may be combined in a multiplex manner whereby the resulting modulator apparatus exhibits an equivalent sampling rate equal to the sampling rate of each of said plurality of relatively low-speed delta modulator means multiplied by the number of relatively low-speed delta modulator means present in said plurality.
  • FIG. I is a block diagram serving to schematically illustrate conventional delta modulator apparatus
  • FIG. 2 is a block diagram schematically showing an embodiment of the delta modulator apparatus according to the present invention.
  • F IG. 3 is a graphical representation illustrating waveforms present at various portions of the block diagram of the embodiment of this invention shown in FIG. 2.
  • the conventional delta modulator apparatus comprises coder means 11, decoder means 12 and subtractor means 13.
  • the coder means 11 may take the form of a conventional l-bit coder circuit which acts in the well-known manner to discriminate between positive and negative values of input signals applied thereto and produce in response to said input signals positive and negative output pulses, respectively, whose amplitudes are constant, at a rate determined by sampling pulses applied to a timing input thereto.
  • the input signals applied to said coder means ll are applied through the conductor 2, which is connected to the output of the subtractor means l3, and the sampling signals are applied thereto from an external source which connects to terminal c through conductor 5.
  • the output of the coder means 11 is applied through the conductor 3 to the output terminal means b of the illustrated delta modulator apparatus and to an input of the decoder means 12 in the manner shown in FlG. l.
  • the decoder means 12 may take, in the simplest case, the form of an integrator circuit which acts in the well-known manner to integrate the bipolar pulse output of the coder means 11 and thus derive therefrom the input waveform to the illustrated delta modulator apparatus.
  • the output of the decoder means 12 is connected through conductor 4 to an input of the subtractor means 13.
  • the subtractor means 13 may take the form of a conventional difference circuit which acts in the well-known manner to provide an output signal representative of the difference between first and second input signals applied thereto.
  • a first input to the subtractor means 13 is applied thereto from input terminal means a which represents the input to the conventional delta modulator apparatus depicted in FIG. 1.
  • the second input of the subtractor means 13 is applied through conductor 4 from the output of the decoder means 12. Accordingly, as the first input signal is the input signal to be modulated and the second input signal represents the decoded output signal of the illustrated delta modulator apparatus, it will be seen that the output signal of the subtractor means, being the difference therebetween, is representative of the error signal of the conventional delta modulator apparatus shown in FIG. 1.
  • input signals to be delta modulated are applied to the input terminal means a and sampling signals, having an appropriate repetition rate, are applied to the input terminal means c.
  • the input signals applied to the input ter minal means a are further applied to the first input of the subtractor means 13 which also receives, as a second input thereto, the output from the decoder means 12.
  • the output of the subtractor means 13 is applied through conductor 2 to the input of the coder means 11 which acts, as aforesaid, on the error signal applied thereto to discriminate such error signals and produce in response thereto positive and negative output pulses of constant amplitudes at a rate determined by the repetition rate of the sampling signals applied to the input terminal means c.
  • the output of the coder means II which takes the form of a bipolar pulse train, is applied through the conductor 3 to the output terminal means b for transmission to the receiving portions of the delta modulation communications system and to the input of the decoder means 12 wherein the same is integrated and applied to the second input of the subtractor means l3 so that an error signal may be derived.
  • the exemplary embodiment of the delta modulator apparatus comprises first and second coder means 14 and 16, first and second integrator means and 17, first and second subtractor means 13 and 23 and multiplexing means 31.
  • the first and second coder means 14 and 16 may each take the form of a conventional one-bit coder circuit of the type described above with reference to -the coder means 11 shown in FIG. 1.
  • the first and second coder means 14 and 16 thus act in the wellknown manner to discriminate between positive and negative values of input signal applied thereto and produce as a result of such discrimination, positive and negative output pulses, respectively, whose amplitudes are constant at rates determined by sampling pulses applied to timing inputs thereto.
  • the timing inputs to each of said first and second coder means 14 and 16 are commonly connected, as shown in FIG. 2, to the input terminal c through the conductor 5'.
  • the input terminal c is here adapted to be connected to an external source of sampling signals which acts to set the sampling rate of each of the first and second coder means 14 and 16.
  • the input signals applied to the first coder means M are applied thereto through the conductor 2 which is connected to the output of the first subtractor means 13 while the input signals applied to the second coder means 16 are coupled thereto through the conductor 9 connected to the output of the second subtractor means 23.
  • the output of the first coder means 14 is connected through the conductor 3 to a first input of the multiplexing means 31 and in addition thereto is connected to the input of the first integrator means 15.
  • the output of the second coder means 16 is connected through the conductor 6 to a second input of the multiplexing means 31 and to the input of the second integrator means 17.
  • the multiplexing means 31 may take the form of a conventional multiplexing circuit which acts in the wellknown manner to multiplex the input pulses applied thereto on a bit by bit basis. As the exemplary embodiment of the delta modulator apparatus shown in FIG.
  • the multiplexing means 31 may be here considered to act upon the input pulses present in the first and second inputs thereto in alternating sequence whereupon such input signals are combined at the output thereof in an alternating sequence.
  • the output of the multiplexing means 31 is connected through the conductor 8 to the terminal means b which here acts as the output means for the delta modulator apparatus illustrated in FIG. 2.
  • the first and second integrator means 15 and 17 may take the form of conventional decoder circuit means which act in the well-known manner to integrate the bipolar pulse output of the first and second coder means 14 and 16, respectively, associated therewith to derive a decoded form of the input waveform applied thereto.
  • the operation of the first and second integrator means 15 and 17 are described in conjunction with the waveforms illustrated in FIG. 3 as if said first and second integrator means 15 and 17 constituted local decoder means of the single integration type.
  • first and second integrator means 15 and 17 act as local decoders of the singleintegration type, to simply integrate the bipolar pulse output of the first and second coder 14 and 16, respectively, associated therewith; it will be appreciated by those of ordinary skill in the art that any well-known form of local decoder circuit may be substituted for the first and second integrator means 15 and 17 and that those forms of decoder circuits acting under dual-integration principles, predicting principles or other conventional principles are specifically contemplated.
  • the output of the first integrator means 15 is connected through conductor 4 to a second input to the first subtractor means 13 in a similar manner to that illustrated in the conventional delta modulator apparatus shown in FIG. 1, while the output of the second integrator means 17 is connected through conductor 7 to a second input of the second subtractor means 23.
  • the first and second subtractor means 13 and 23 may each take the same form and perform the same functions as the subtractor means 13 previously described in conjunction with FIG. 1.
  • a first input to the first subtractor means 13 is applied thereto from the input terminal means a which represents the input to the embodiment of the delta modulator apparatus illustrated in FIG. 2 and hence may receive video signals or any other form of input signal to be modulated prior to transmission.
  • the second input to the first subtractor means 13 is connected to the output of the first integrator means 15 so that said first subtractor means 13 receives first and second input signals representing the signal to be modulated and the decoded output signal of the first coder means 14, respectively, and produces in response thereto an output error signal representative of the difference therebetween.
  • the output of the first subtractor means 13 is connected through the conductor 2 to the input of the first coder means 14 and to a first input of the second subtractor means 23.
  • a second input to the second subtractor means 23 is connected through the conductor 7 to the output of the second integrator means 17.
  • the second subtractor means 23 thus receives at the first and second inputs thereto a first input signal representative of the error signal applied as an input to the first coder means 14 and a second input signal representative of the decoded output of the second coder means 16.
  • the second subtractor means 23, thereby acts in the well-known manner to produce an error output signal representative of the difference between the input to the first coder means 14 and the decoded output of the second coder means 16 and such error output signal is applied, as aforesaid, to the input of the second coder means 16 through the conductor 9.
  • the delta modulator apparatus includes first delta modulator means formed by the first subtractor means 13, the first coder means 14 and first integrator means I5 and second delta modulator means formed by the second subtractor means 23, the second coder means 16 and the second integrator means 17.
  • the first and second delta modulator means thus present in the FIG. 2 embodiment of the present invention are interconnected in such a manner that each of said first and second delta modulator means is commonly timed by sampling signals applied to the input terminal c and the error signals applied to the first coder means 14, present in the first delta modulator means, are applied as input signals to the first input of the second subtractor means 23 of the second delta modulator means.
  • the sampling rate of each of the first and second modulator means may be one-half of that required in the conventional delta modulator apparatus illustrated in FIG. I for the same form of input signals applied and hence the repetition rate of the sampling signals applied to the input terminal c' of the delta modulator apparatus shown in FIG. 2 need only be onehalf that required to be applied to the input terminal c of the conventional delta modulator apparatus shown in FIG. I.
  • the sampling rate of each of the first and second modulator means may be one-half of that required in the conventional delta modulator apparatus illustrated in FIG. I for the same form of input signals applied and hence the repetition rate of the sampling signals applied to the input terminal c' of the delta modulator apparatus shown in FIG. 2 need only be onehalf that required to be applied to the input terminal c of the conventional delta modulator apparatus shown in FIG. I.
  • two interconnected delta modulator means have been shown in the exemplary embodiment of the delta modulator apparatus illustrated in FIG.
  • any number n of delta modula tor means may be present therein and interconnected in the manner shown wherein each such delta modulator means is commonly timed and receives as an input signal thereto the error signal derived from the preceding delta modulator means.
  • the sampling rate of each of the delta modulator means present therein will be l/nth the sampling rate of that necessary for the conventional delta modulator apparatus illustrated in FIG. I while the equivalent sampling rate for such given embodiment of the present invention will be the same as that exhibited by said conventional delta modulator apparatus.
  • FIG. 3 depicts the waveforms present at various portions of the illustrated embodiment of the instant invention during the operation thereof. Accordingly during the explanation of the present invention which follows, the reader will be periodically referred to specific waveforms illustrated in FIG. 3 so that the function of the circuit component being described will be fully appreciated.
  • an input signal which may take the form of a video signal or and other signal to be modulated is applied to the input terminal means a and sampling pulses having an appropriate repetition rate, supplied from an external source not shown herein, are applied to the input terminal 0'.
  • the input signals applied to the input terminal means a may here be considered to take the form of video signals, a portion of whose waveform is illustrated by the waveform l in FIG. 3.
  • the input signals thus applied to the input terminal means a are further applied through the conductor 1 to the first input of the first subtractor means I3 which also receives, as aforesaid, at the second input thereof, the output of the first integrator means 15 applied thereto by the conductor 4.
  • the second input to the first subtractor means 13, applied thereto by the conductor 4, is illustrated in FIG. 3 by the waveform 4'.
  • the first subtractor means 13 acts in the well-known manner on the first and second input signals applied thereto to derive therefrom an error signal representative of the difference thcrebetween.
  • the output of the first subtractor means 13, as shown by the waveform 2' in FIG. 3, is applied through the conductor 2 to the input of the first coder means 14.
  • the first coder means 14, as indicated above, acts on the error signal applied thereto to discriminate such error signal as to positive and negative values and produce in response thereto positive and negative output pulses of a constant magnitude whose rate is determined by the repetition rate of the sampling signals applied to the input terminal 0' and applied to the timing input thereof through the conductor 5'.
  • the first subtractor means 13 receives first and second input signals representative of the input signal to be modulated and the decoded output of the first coder means 14, respectively, and derives therefrom an output error signal representative of the difference therebetween for application to the first coder means 14; it will be appreciated that the operation of the first delta modulator means present in the embodiment of the delta modulator apparatus of this invention as illustrated in FIG. 2 is similar to that of the conventional delta modulator apparatus shown in FIG. 1.
  • the error output signal produced by the first subtractor means I3, as shown by the waveform 2, is additionally applied through the eonductor 2 to the first input of the second subtractor means 23 of the second delta modulator means present in the delta modulator apparatus shown in FIG. 2.
  • the error signal of the first delta modulator means present in the embodiment of the invention illustrated in FIG. 2 serves as the input signal to the second demodulator means present therein. Since the operation of the second delta modu lator means present in the embodiment of the invention illustrated in FIG.
  • the second subtractor means 23 receives error input signals from the output of the first subtractor means 13 as a first input thereto and output signals from the second integrator means 17, through the conductor 7, at the second input thereof wherein the waveform of the second input to the second subtractor means is illustrated by waveform 7' in FIG. 3.
  • the output of the first subtractor means 13 shown in FIG. 2 is illustrated in FIG. 2 as being directly applied to the first input of the second subtractor means 23, it should be understood that the operation of the second delta modulator means present in the embodiment of the invention shown in FIG. 2 may be rendered more stable by applying the error signal from the first delta modulator means to the first input of the second subtractor means 23 through a low-pass filter so that the sampling frequency component of the error signal may be removed thereby.
  • the second subtractor means 23 is thus in receipt of the error signal of the first delta modulator means at the first input thereof and the output of the second integrator means 17 at the second input thereto and thereby acts in the previously described manner to produce a second error output signal representative of the difference therebetween.
  • the output of the second subtractor means 23 is applied through conductor 9 to the input of the second coder means 16.
  • the second coder means 16 acts to discriminate the second error signals applied thereto as to positive and negative values and as a result of such discrimination produces positive and negative output pulses, respectively, having a constant magnitude at a rate determined by the repetition rate of the sampling signals applied to the input terminal 0'.
  • the first and second coder means M and 16 operate at the same sampling rate as determined by the repetition rate of the sampling signals applied to the input terminal 0 which samplingrate is equal to one-half of that exhibited by the coder means 11 illustrated in the con ventional delta modulator apparatus shown in FIG. I
  • the output of the second coder means I 6, illustrated by the bipolar waveform 6 in FIG. 3, is applied through the conductor 6 to the second input of the multiplexing means 31 and to the input of the second integrator means 17.
  • the second integrator means 17 is selected to have the same characteristics as the first integrator means 15 and may therefore be considered to take the form of a decoder circuit of the single-integration variety whose length of step or level interval is increased or decreased in response to a single-code pulse in the same manner as that of the first integrator means 15.
  • the second integrator means 17 thus acts to integrate the bipolar output pulses 6 present at the output of the second coder means 16 and supply such integrated output, as shown by the waveform 7 in FIG. 3, to the second input of the second subtractor means 23 through the conductor 7.
  • the second subtractor means 23 receives the error signal of the first delta modulator means present in the delta modulator apparatus of the instant invention at a first input thereto, receives the integrated output of the second coder means 14 at a second input thereto and produces an output signalequal to the error signal of the second delta modulator means present in the delta modulator apparatus according to the present invention.
  • the error output signal from the second subtractor means 23 is applied only to the input of the second coder means 16'; however, if an embodiment of this invention were illustrated wherein a third delta modulator stage were present, the error output signal from the second subtractor means would additionally be applied to a first input to the subtractor means present in that stage.
  • the outputs of the first and second coder means 14 and 16, illustrated by the wavefomis 3 and 6' in FIG. 3, are applied to the first and second inputs, respectively, of the multiplexing means 31.
  • the multiplexing means 3! acts in the well-known manner to combine the bipolar output pulse trains of the first and second coder means 14 and 16 in a bit by bit time division sequence wherein the pulses applied to the first input thereof by the conductor 3 are allocated first time slots in the output of the multiplexing means 311 and corresponding pulses applied to the second input of said multiplexing means 31 are allocated second time slots.
  • the multiplexing means 31 has been relied upon in the embodiment of this invention illustrated in FIG.
  • the multiplexing means 31 may be omitted and the outputs of each of the n coder means relied upon therein directly transmitted.
  • the coded multiplexed pulse train received may be decoded by integrator means having the same characteristics as the first and second integrator means 15 and 17 illustrated in FIG. 2. Thereafter, the integrated waveform of such transmitted NRZ signals may be applied to a low-pass filter means whereby the fundamental frequency band component of the original signal applied to the input terminal means a may be recovered.
  • the integrated waveform of transmitted NRZ signals is illustrated by the solid portion of waveform 10 in FIG. 3 while the fundamental recovered therefrom by passing said integrated waveform through a lowpass filter means is indicated by the dashed portion of waveform 10'.
  • the multiplexed signal received may be divided into two pulse trains and separately operated upon by individual decoders whose outputs may then be added to again derive the original signal. Furthermore, even when such alternative receiving and decoding operation is utilized, so long as each of the individual decoder means exhibit the same electrical characteristics, no particular synchronizing signal will be required.
  • the delta modulator apparatus exhibits an equivalent sampling frequency which is sufficiently high to allow the transmission of wideband signals while allowing each of the delta modulator means present therein to operate at relatively low frequencies which are readily within the normal capabilities of the circuit components present therein.
  • delta modulator apparatus has been disclosed in conjunction with the exemplary embodiment thereof illustrated in FIG. 2, many modifications and alterations will be obvious to those of ordinary skill in the art.
  • delta modulator apparatus may be formed in accordance with the teachings of the present invention containing any number n of delta modulator means therein and each such delta modulator means thus present will operate at l/nth of the desired sampling frequency while the delta modulator apparatus formed as a whole will exhibit an equivalent sampling frequency equal to that desired.
  • present invention has been disclosed in conjunction with an exemplary embodiment thereof which relies upon decoder means of the single integration variety, it will be apparent that any known form of decoder means may be utilized without any deviation from the teachings of the present invention.
  • Delta modulator apparatus comprising:
  • each of said plurality of delta modulator stages including means for deriving an error signal equal to the difference between said coded pulse train output representative of the input signal received and the actual input signal received and means for coding said error signal to thereby produce said coded pulse train;
  • said means for accepting said coded pulse train output of each of said delta modulator stages includes multiplexing means for converting each of said coded pulse train outputs into a resultant high speed multiplexed pulse train.
  • each of said plurality of delta modulator stages other than said one stage is connected to said immediately preceding delta modulator stage through low-pass filter means, said low-pass filter means acting to remove sampling frequency components present in said error signal.
  • each of said plurality of delta modulator stages comprises subtractor means, coder means and integrator means.
  • delta modulator apparatus exhibits an equivalent sampling rate equal to the sampling rate of each of said plurality of delta modulator stages multiplied by the number of delta modulator stages in said plurality.
  • each of said integrator means exhibits closely matched electrical characteristics.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
US847622A 1968-08-06 1969-08-05 Delta modulator apparatus Expired - Lifetime US3594509A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP43055290A JPS4839505B1 (de) 1968-08-06 1968-08-06

Publications (1)

Publication Number Publication Date
US3594509A true US3594509A (en) 1971-07-20

Family

ID=12994436

Family Applications (1)

Application Number Title Priority Date Filing Date
US847622A Expired - Lifetime US3594509A (en) 1968-08-06 1969-08-05 Delta modulator apparatus

Country Status (3)

Country Link
US (1) US3594509A (de)
JP (1) JPS4839505B1 (de)
GB (1) GB1237820A (de)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3681756A (en) * 1970-04-23 1972-08-01 Industrial Research Prod Inc System for frequency modification of speech and other audio signals
US3750024A (en) * 1971-06-16 1973-07-31 Itt Corp Nutley Narrow band digital speech communication system
US3881099A (en) * 1972-12-15 1975-04-29 Lannionnais Electronique Pseudo-random binary sequence generator
US4229820A (en) * 1976-03-26 1980-10-21 Kakusai Denshin Denwa Kabushiki Kaisha Multistage selective differential pulse code modulation system
US4618952A (en) * 1983-11-04 1986-10-21 Fibronics Ltd. Communication of unipolar pulses
US5150120A (en) * 1991-01-03 1992-09-22 Harris Corp. Multiplexed sigma-delta A/D converter
US6104991A (en) * 1998-02-27 2000-08-15 Lucent Technologies, Inc. Speech encoding and decoding system which modifies encoding and decoding characteristics based on an audio signal

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50123912U (de) * 1974-03-26 1975-10-09
JPS557475U (de) * 1978-06-29 1980-01-18

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2949505A (en) * 1957-08-14 1960-08-16 Bell Telephone Labor Inc Reduced bandwith transmission system
US3471648A (en) * 1966-07-28 1969-10-07 Bell Telephone Labor Inc Vocoder utilizing companding to reduce background noise caused by quantizing errors
US3518548A (en) * 1966-11-22 1970-06-30 Philips Corp Pulse delta modulation transmission system having separately transmitted low-frequency average level signal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2949505A (en) * 1957-08-14 1960-08-16 Bell Telephone Labor Inc Reduced bandwith transmission system
US3471648A (en) * 1966-07-28 1969-10-07 Bell Telephone Labor Inc Vocoder utilizing companding to reduce background noise caused by quantizing errors
US3518548A (en) * 1966-11-22 1970-06-30 Philips Corp Pulse delta modulation transmission system having separately transmitted low-frequency average level signal

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3681756A (en) * 1970-04-23 1972-08-01 Industrial Research Prod Inc System for frequency modification of speech and other audio signals
US3750024A (en) * 1971-06-16 1973-07-31 Itt Corp Nutley Narrow band digital speech communication system
US3881099A (en) * 1972-12-15 1975-04-29 Lannionnais Electronique Pseudo-random binary sequence generator
US4229820A (en) * 1976-03-26 1980-10-21 Kakusai Denshin Denwa Kabushiki Kaisha Multistage selective differential pulse code modulation system
US4618952A (en) * 1983-11-04 1986-10-21 Fibronics Ltd. Communication of unipolar pulses
US5150120A (en) * 1991-01-03 1992-09-22 Harris Corp. Multiplexed sigma-delta A/D converter
US6104991A (en) * 1998-02-27 2000-08-15 Lucent Technologies, Inc. Speech encoding and decoding system which modifies encoding and decoding characteristics based on an audio signal

Also Published As

Publication number Publication date
JPS4839505B1 (de) 1973-11-24
GB1237820A (en) 1971-06-30

Similar Documents

Publication Publication Date Title
US5461379A (en) Digital coding technique which avoids loss of synchronization
US3980825A (en) System for the transmission of split-phase Manchester coded bivalent information signals
US3980824A (en) Modulator demodulator for binary digitally encoded messages
US3594509A (en) Delta modulator apparatus
US4787096A (en) Second-order carrier/symbol sychronizer
US3899429A (en) Pulse-frequency-modulation signal transmission system
US4086587A (en) Apparatus and method for generating a high-accuracy 7-level correlative signal
US3968328A (en) Circuit for automatically correcting the timing of clock pulse in self-clocked pulse signal decoders
US4928318A (en) Optical signal transmission system including pulsed FM modulator/demodulator
US4325053A (en) Method and a circuit for decoding a C.M.I. encoded binary signal
US4075429A (en) Transmultiplexer
US3459892A (en) Digital data transmission system wherein a binary level is represented by a change in the amplitude of the transmitted signal
US3984777A (en) Carrier wave reproducer device for use in the reception of a multi-phase phase-modulated wave
US4153814A (en) Transition coding method for synchronous binary information and encoder and decoder employing the method
US3339142A (en) Adaptive pulse transmission system with modified delta modulation and redundant pulse elimination
US4489421A (en) Digital message transmission system employing pulse stuffing and having two plesiochronic sampling clocks
US3996607A (en) System for digital transmission of color television signals
US4639911A (en) Head-end and receiver for a signal distribution system
US4264973A (en) Circuitry for transmitting clock information with pulse signals and for recovering such clock information
US3394312A (en) System for converting two-level signal to three-bit-coded digital signal
US4550337A (en) Digital video transmission system
US4461011A (en) Method and apparatus for converting binary information into a high density single-sideband signal
US4346367A (en) Circuit for converting binary digital signals into pseudoternary A.C. pulses
US4534037A (en) Method and apparatus for scrambled pulse-code modulation transmission or recording
US3739289A (en) Apparatus for demodulation of phase difference modulated data