US3593164A

US3593164A - Electric linear and square root integrator and multiplier/divider

Info

Publication number: US3593164A
Application number: US709575A
Authority: US
Inventors: William F Newbold
Original assignee: Honeywell Inc
Current assignee: Honeywell Inc
Priority date: 1968-03-01
Filing date: 1968-03-01
Publication date: 1971-07-13
Anticipated expiration: 1988-07-13
Also published as: CA932864A; GB1268649A; FR2003047A1; JPS4843464B1; SE348063B; DE1910102A1; NL6903271A

Abstract

A circuit is provided for performing various arithmetic operations. These arithmetic operations include linear integration, square root extraction, multiplication and division. The circuit includes an integrator having capacitive transfer, sampling and holding circuits. A voltage-to-frequency converter network is interconnected by operational amplifiers.

Description

United States Patent (72] Inventor William F. Newbold 3,049,631 8/1962 Taylor 307/295 Springfield Township, Montgomery 3,192,481 6/1965 Pincus 331/177 County,Pa. 3,376,518 4/1968 Emmer 331/177 [21] Appl. No. 709,575 3,386,039 5/1968 Naive 328/127 [22] Filed Mar. 1, 1968 3,113,274 12/1963 Utt 328/144 {45] Patented July 13,1971 3,256,426 6/1966 Roth et a1. 328/127 [73} Assignee Honeywell inc. 3,327,228 6/1967 Deavenportetal. 307/271 p is, Minn. OTHER REFERENCES Feedback Linearizes Voltage to Frequency Converter" 54 ELECTRIC LINEAR AND SQUARE ROOT by James D: Long page 48 ELECTRONICS September 1,

INTEGRATOR AND MULTlPLIER/DIVIDER (CPY m 331/177) 2 Chums S g 8 Primary Examiner-Donald D. Forrer [s21 U.S.C1 328/144, 45mm" 328,127 307/228, 307/271, 307/295 307/229 Att0meys-Arthur H. Swanson and Lockwood D. Burton [51] lnt.Cl H04b 1/04 [501 Field of Search .1 307/271,

228395329328/127, 144 ABSTRACT: A circuit is provided for performing various arithmetic operations. These arithmetic operations include [561 References cued linear integration, square root extraction, multiplication and UNITED STATES PATENTS division. The circuit includes an integrator having capacitive 2,894,215 7/1959 Toy 307/295 transfer, sampling and holding circuits. A voltage-to-frequen- 3,022,469 2/1962 Bahrs eta1.. 307/295 cy converter network is interconnected by operational am- 3,040,273 6/1962 Boff 328/127 plifiers.

l3 2 VOLTAGE I ,2, To '7 FREQUENCY V CONVERTER TRANSFER TRANSFER R UNIT I UNIT --0 NO. 1 d No.2

S I\ I00- 5 Y CONTROL UNIT OUTPUT PATENTED JUL 1 312m SHEET 1 [IF 3 l l v V F G VOLTAGE L T0 I. I7 FREQUENCY V CONVERTER ::-2l IO TRANSFER TRANSFER ER UNIT um? --o no. I no.2

, FCONTROL uurr OUTPUT F I e. 3

INVENTOR.

WILLIAM F. NEWBOLD ATTORNEY.

PATENTEU JUL] 3 |97| SHEET 2 BF 3 INVI'IN'IUR. WILLIAM F. NEWBOLD ATTORN PATENTEU JUL 1 3 I971 SHEET 3 BF 3 COUNTER FIG. 5

IN VIENTOR.

FLIP FLOP WILLIAM F. NEWBOLD BY 2 ATTORNE ELECTRIC LINEAR AND SQUARE ROOT INTEGRATOR AND MULTIPLIER/DIVIDER Cross reference is made to other applications assigned to the common assignee wherein other arithmetic circuits are described. These arithmetic circuits may be generally categorized as time division multiplier circuits or the like. These applications include one entitled TIME DIVISION MULTIPLIER, by W. H. Crowell bearing Ser. No. 675,596 and filed on Oct. 16, 1967, now U.S. Pat. No. 3,492,471. Another application is entitled TIME-DIVISION MULTIPLI- ER by T. A. Patchell bearing Ser. No. 406,675 and filed on Oct. 27, 1964, now US. Pat. No. 3,383,501. Each of these applications, as noted, relates to arithmetic circuits which can be connected as multipliers or square rootextractors.

The subject application is, generally, an arithmetic circuit. This arithmetic circuit can be connected to produce a square root output signal, or it can be connected to operate as an integrator or a multiplier and divider. The circuit is basically linear in operation.

A voltageto frequency converter is utilized to produce output pulses as a function of an input signal level. The input signal level is supplied via suitable amplification means, if necessary and desirable. That is, an amplifier can reduce the nonlinearity in a voltage to frequency converter. A transfer unit which comprises a switchable storage circuit (for example a capacitor) applies a negative feedback input signal to the voltage to frequency converter. This combination of amplification and negative feedback produces a linear voltage to frequency converter; If the output of the aforesaid network is connected to a suitable pulse motor or impulse counter, an in tegrated or totalized output signal can be produced.

By utilizing a further switchable storage circuit (and suitable amplification means) as the input to the aforesaid circuit, a square root integrating circuit is produced'lf the second mentioned circuit is used as a separate input in conjunction with the first mentioned voltage to frequency network, a multiplier and divider circuit is obtained. The latter connections are especially useful in obtaining solutions to flow equations.

Consequently, one object of this invention is to provide an Another object of this invention is to provide a linear arithmetic circuit which utilizes a nonlinear oscillator.

These'and other objects and advantages of this invention will become readily apparent when the following description is read in conjunction with the attached drawings, in which:

FIG. 1 is a block diagram of the circuit;

FIG. 2 is a schematic diagramof the linear voltage-tofrequency converting circuit;

FIG. 3 is a schematic diagram of the input transfer circuit which can be connected to the .input of the circuit shown in FIG. 2;

FIG. 4'is a schematic diagram of a suitable output control circuit; and

FIG. 5 is a schematic diagram of a second embodiment of the nonlinear voltage to frequency converter circuit.

Referring now to FIG. I, there is shown a block diagram of the subject arithmetic circuit. An input signal vV (which may be a positive signal of [-5 volts, DC) is supplied at terminal 1. Terminal 1 is connected to normally open contacts 19 and to normally closed contacts 20. Resistor 17 is connected between the normally closed contacts 20 and one input of amplifier 11. The output of amplifier. 11 is connected via normally closed contacts 21 to common junction 2 at which the signal 21 is detected. The output of amplifier 11 is connected via feedback path 10a to the input of switching circuit 10 designated as transfer unit 1. The output of switching circuit 10 is connected to an input of amplifier 11. The control input of switching circuit 10 is supplied by control unit 15 which is described hereinafter.

The input of amplifier 13 is connected to normally open contacts 19 and to common junction 2 via resistor 18. The output of amplifier 13 is connected to a voltage to frequency converter circuit (VFC) 14. The'output of VFC 14 is connected to control unit 15. The output of control unit 15 is connected to switching circuit 12 designated as transfer unit 2. The input of switching circuit" is connected to common junction 2 via resistor 18. The input of amplifier 13 is also connected to the input of switching circuit 12. A reference source E2 is connected to a further input of switching'circuit 112. An output device 16 is connected to an output of control unit 15.

While the

contacts

19, 20 and 21 need not be utilized in a typical application of this circuit, the switches are used to suggest a selective interconnection of the circuit to produce either a linear voltage to frequency converter or a square root integrating circuit. Thus, with the contacts in the positions shown, the input signal V is applied via closed contacts 20 and resistor 17 to the input of amplifier l1 and transfer unit 1. The output of amplifier 11 is connected via closed contacts 21 to common junction 2. The signal Z1 detected at common junction 2, is applied via resistor 18 to transfer unit 2 and is, as well, returned to the input of transfer unit 1 via feedback path 10a.

In the alternative, operation of a relay coil (not shown) will cause the closing of contacts 19 and the opening of

contacts

20 and 21. Thus, the output of amplifier 11 is disconnected from the circuit as is the input to amplifier 11 and switching circuit 10. Consequently, the input signal at terminal I is supplied via closed contacts 19 to amplifierl3 and switching circuit 12 whereby a linear voltage to frequency conversion circuit is provided.

In essence, the voltage to frequency conversion network (individually or as a portion of the integrating circuit) operates upon an input signal supplied to amplifier 13. The signal is amplified as desired and applied to the VFC 14 which selectively produces output pulses as a function of the magnitude of the input signal supplied thereto. The signals produced by VFC 14 are supplied to control unit 15. Control unit 15 is operative to provide signals to switching

circuits

10 and 12 to cause the selective operation thereof. That is, switching circuits l0 and I2 selectively operate on the signals supplied thereto as a function of the pulses supplied by control unit 15 in response to signals supplied by VFC I4. Thus, switching circuit 10 operates upon the signal supplied via resistor 17 or via path 10a dependent upon the signal supplied by control unit 15. Similarly, switching circuit 12 operates upon the signal supplied via resistor 18 or a reference signal E according to the condition of control unit 15. More particularly, each of the switching

circuits

10 or 12, selectively samples or stores a signal representative of a predetermined value in response to one signal condition at control unit 15. A different signal condition at control unit 15 causes the

circuits

10 or 12 to apply the sampled 'or stored signal to the input of the associated amplifier. This applied signal affects the signal supplied to the amplifiers by the respective input circuit. The amplifiers are affected by this combination of signals and operate thereon accordingly.

Furthermore, control unit '15 supplies signals to output device 16. Output device 16 may be any suitable counter or the like which counts pulses produced by control unit 15. Output device 16 may operate as a totalizer or an integrator.

Referring to FIG. 2, there is shown a schematic diagram of a linear voltage to frequency converter circuit. The signal 21, which in this case is identical with the input signal V referred to in connection with FIG. 1, is applied to a terminal which corresponds to common junction 2 of FIG. 1 and is at one end of resistor 18. The opposite end of resistor 18 is connected to the inverting input of amplifier l3 and to the emitter electrode of transistor 30. The noninverting input of amplifier 13 is connected via resistor 51 to ground. Resistor 51 is utilized to provide bias current compensation relative to amplifier 13. Amplifier 13 is an operational amplifier and operates to sum the input currents supplied thereto substantially to zerov The opposite end of resistor 18 is also connected to the emitter of transistor 30 at the terminal D The collector electrode of transistor 30 is connected via precision capacitor 34 to ground. In addition, the collector of transistor 30 is connected to the emitter of transistor 31. The collector of transistor 31 is connected via voltage source 35 to ground. Voltage source 35, shown as a battery, provides a suitable reference potential, for example volts. The base of transistor 31 is connected via diode 36 to ground. Diode 36 is poled to provide current flow from ground to the base of transistor 31. The base of transistor 30 is connected via diode 32 to the emitter thereof. Diode 32 is connected for current flow from the emitter to the base of transistor 30. In addition, the emitter of transistor 30 is connected, via capacitor 33, to ground at terminal C1.

The base of transistor 30 is further connected via the series connection of resistor 38, capacitor 40 and resistor 48 to terminal B1 of flip-flop 70. The base of transistor 31 is further connected via the series combination of resistor 37, capacitor 39 and resistor 47 to terminal A1 of flip-flop 70. It is seen that terminals A1, B1 are the complementary outputs of flip-flop 70 wherein either transistor 30 or transistor 31 is rendered conductive, alternatively and exclusively, in accordance with the condition of flip-flop 70.

The junction between capacitor 40 and resistor 48 is connected to one terminal of capacitor 42. Another terminal of capacitor 42 is connected to the junction between resistor 45 and the anode of diode 43. The cathode of diode 43 and the other terminal of resistor 45 are connected to ground. In addition, the junction between capacitor 39 and resistor 47 is connected to one terminal of capacitor 41. The other terminal of capacitor 41 is connected to a common junction of the anode of diode 44 and one terminal of resistor 46. The other terminal of resistor 46 and the cathode of diode 44 are connected to ground.

The output of amplifier 13 is connected via resistor 51 to the base of transistor 53. The emitter of transistor 53 is connected to ground via resistor 52. The collector of transistor 53 is connected to a suitable voltage source, for example +l2 volts via capacitor 64. In addition, the collector of transistor 53 is connected to the collector of transistor 56. The emitter of transistor 56 is connected to ground via resistor 55. The anode of the silicon controlled switch (SCS) 63 is connected to the +12 volt source via resistor 62. The cathode of SCS 63 is connected to the emitter of transistor 56.

A voltage divider

network comprising resistors

57, 58, 59 and 60 is connected between the +1 2 volt source and ground. The variable tap of resistor 59 is connected to the base of transistor 56. The junction between

resistors

58 and 59 is connected to the cathode of diode 54. The anode of diode 54 is connected to the base of transistor 53. The common junction between

resistors

57 and 58 is connected via resistor 72 to the gate electrode of SCS 63.

The emitter of transistor 67 is connected to the +12 volt source. Resistor 66 is connected between the emitter and base electrodes of transistor 67. Capacitor 65 is connected between the anode of SCS 63 and the base of transistor 67. The collector of transistor 67 is connected via resistor 61 to ground. In addition, the collector of transistor 67 is connected as an input to flip-flop 70 to provide the trigger or toggle input thereto such that the signals supplied at output terminals A and B are varied.

An output of flip-flop 70 is connected via capacitor 71 to the collector of transistor 68. The emitter of transistor 68 is connected to ground. The base of transistor 68 is connected to the common junction between one end of resistor 49 and the anode of diode 50. The other end of resistor 49 is connected connected to ground.

In addition, the collector of transistor 68 is connected via resistor 69 to a suitable reference source, for example l2 volts. The collector of transistor 68 is further connected to the output device 16 as described hereinafter.

In operation, amplifier 13 functions as an operational amplifier. Amplifier l3 sums the currents l1, 12 which are applied, via commonjunction D1, to the input of amplifier 13. Current ll is defined by the equation I l=E /Rl where E,- is the signal 21 and R] is the resistance value of resistor 18. Current 12 is calculated from the equation I2=ClF E, where F is the frequency of transfer or operation of

transistors

30 and 31, Cl is the capacitance value of capacitor 34 and E is the value of the reference voltage as applied by source 35.

Amplifier 13 operates upon the input signal supplied thereto and produces a signal at the base of transistor 53 which controls the operation, or the conductivity characteristic, thereof. The operation of transistor 53 controls the charging current flow for capacitor 64 and provides a decreasing ramp-type output voltage. This voltage is applied to the cathode of SCS 63. When the voltage supplied to the cathode of SCS 63 becomes less than the bias voltage supplied to the gate electrode thereof via the voltage divider network, SCS 63 fires. When SCS fires, capacitor 64 is discharged therethrough, the voltage across capacitor is dissipated. When capacitor 64 is fully discharged, SCS 63 is turned off due to the lack of a sustaining voltage. Capacitor 64 is then connected to begin charging again wherein the ramp voltage signal is initiated again as a function of the current which exists through transistor 53. Since the transistor 53 controls the charging current for the capacitor in accordance with the magnitude of the applied DC signal, the repetitive firing rate of the switching transistor 63 is also controlled in accordance with the magnitude of the DC signal applied as input signal to the transistor 53. Therefore the firing rate of the transistor 63 is at a repetitive frequency which is proportional to the magnitude of the input signal.

When SCS 63 is rendered conductive, a relatively large current exists in the circuit therewith such that a relatively large voltage is dropped across resistor 62. Consequently, the potential at the base of transistor 67 is reduced whereupon the transistor is rendered conductive. When transistor 67 is conductive, a relatively high voltage is applied via the collector thereof to the input of flip-flop 70. Inasmuch as capacitor 64 is very rapidly discharged, hereby SCS 63 is rapidly rendered nonconductive, transistor 67 is operative for only a short time. Consequently, the signals supplied to the toggle input of flipflop 70 appear to be in the nature of spike-tyne signals. These signals are supplied via terminals Al and D1 to the bases of

transistors

30 and 31, respectively. When transistor 31 is rendered conductive, the reference signal is supplied across capacitor 34 which is a precision capacitor. When transistor 30 is conductive, capacitor 34 is connected to the input of amplifier 13. When the transistor 30 is conductive, the capacitor 34 is charged to the input potential of amplifier 13. When the transistor 31 is conductive and transistor 30 is nonconductive, the capacitor 34 is discharged to the level of the reference potential of the source 35. This charging and discharging of the capacitor 34 results in the production of a unidirectional current flow which is directly proportional to the frequency of the output pulses from the SCS 63 as hereinbefore noted. The capacitor 33 provides a smoothing or filtering action for the current 12. That current 12 is of opposite polarity with respect to the input current 11 and sums algebraically with 11 at the input of the amplifier 13.

It was previously noted that the amplifier 13 is an operational amplifier. As such a feedback current must be provided to sum toward zero with the input current to stabilize the operation of the amplifier. Therefore, in order to stabilize the operation of the amplifier with the oscillatory output, with respect to the frequency conversion. the frequency of the output signal is used to provide [2 as above noted, to provide the feedback current signal to the input of the amplifier 13, thus closing the loop and stabilizing the voltage-to-frequency conversion of the apparatus. Thus, it is seen that the current I applied to amplifier 13 is a function of the frequency of the output signal supplied at the collector of transistor 67.

The output of flip-flop 70 is connected via capacitor 71 to the output device I6. Output device 16 which may include a suitable counter, or the like, counts the signals supplied by flip-flop 70 and produces a suitable display thereof. Thus, since the voltage to frequency conversion is linear, the inclusion of means to count the pulses renders the system a linear integrator. If the output is taken at the collector of transistor 67 a linear voltage to frequency converter is provided. In an exemplary apparatus, constructed in accordance with the present invention, the output frequency, taken at the collector of the transistor 67, as on the order of 80 pulses per second for a maximum input signal of5 volts.

Transistor 56 is connected to capacitor 64 to provide a low limit bias current thereto. That is, if the frequency F of the signals supplied to flip-flop 70 is sufficiently small wherein the operation rate of transistors and 31 is extremely slow, amplifier 13 produces a relatively negative output signal. A negative signal from amplifier 13 renders transistor 53 relatively nonconductive. Transistor 56 is, then, relatively conductive and supplies a current to capacitor 64 to provide a low limit signal. When amplifier 13 produces a negative signal at or below the minimum signal designated, transistor 68 is rendered conductive thereby clamping the output of flip-flop 70 to ground. This has the effect of terminating the operation of the output device 16 when the frequency of operation is below the cutoff value.

It should be noted that

transistors

30 and 31 operate as switches and, therefore, can be replaced by other switching devices. For example, it is contemplated that other semiconductor device (such as field effect transistors) can be used. Alternatively, relays can be used. Reed relays or the like would be preferable in some cases. If relays are used, the outputs of flip-flop 70 would be connected to relay coils to effect control over the switching operation.

In a further modification, not necessarily related to the above embodiment, transistor 67 and the components related thereto, may be eliminated. In this configuration, the input of flip-flop 70 would be connected to the junction of the collector of transistor 53 and capacitor 64. Moreover, a resistor (not shown) is connected between the collector of transistor 53 and the cathode of SCS 63 to effect suitable isolation.

Referring no to FIG. 3, there is shown an input circuit which can be associated with the circuit shown in FIG. 2 to produce a square root integrator circuit. Input signal Z2 is equivalent to the signal V shown in FIG. 1. This signal is supplied via resistor 17 to one input of amplifier 11. The other input of amplifier I1 is connected via resistor 93 to ground. Resistor 93 is used to provide bias current compensation for amplifier 11. The output of amplifier 11 is supplied to the base of transistor 95 which is an isolating circuit. The collector of transistor 95 is connected to a suitable reference potential, for example l2 volts. The emitter of transistor 95 is connected via resistor 94 to ground and directly to terminal Z1 which is related to one terminal of resistor 18, shown in FIG. 3.

The emitter of transistor 95 is further connected to the collector of transistor 75. The emitter of transistor 75 is connected to the collector of transistor 76. The emitter of transistor 76 is connected to the junction between resistor 17 and the input of amplifier 11. The emitter of transistor 76 is further connected to ground via capacitor 78. The common junction between the emitter of transistor 75 and the collector of transistor 76 is connected to ground via the precision capacitor 79. The base of transistor 76 is connected to the anode of diode 77 which has the cathode thereof connected to the emitter of transistor 76. The baseof transistor 75 is con nected to the anode of diode 80 which has the cathode thereof connected to ground.

The base of transistor 75 is further connected via the series connection of resistor 81, capacitor 83 and resistor to terminal A2. The base of transistor 76 is further connected via the series combination of resistor 82, capacitor 84 and resistor 86 which is connected to terminal B2. Terminals A2 and B2 are connected to flip-flop 70 along with terminals A1 and B1. The common junction between capacitor 83 and resistor 85 is connected to one terminal of capacitor 88.Another terminal of capacitor 88 is connected to one terminal of resistor 92 and the cathode of diode 91. The anode of diode 91 and another terminal of resistor 92 are connected to ground.

The common junction between capacitor 84 and resistor 86 is connected to one side of capacitor 87. The other side of capacitor 87 is connected to one terminal of resistor 89 and to the cathode of diode 90. The other terminal of resistor 89 and the anode of diode 90 are connected to ground.

The operation of switching unit 10 (shown in FIG. 3) is similar to the operation of switching unit 12 (shown in FIG. 2). That is, in accordance with the condition of the flip-flop 70, the signals supplied to terminals A2 and B2 are determinative of the alternative operation of

transistors

75 and 76. Thus, hen transistor 75 is conductive, capacitor 79 is discharged to the level of the output signal at the emitter of the transistor and, when transistor 76 is conductive, capacitor 79 is being charged to the level of the input terminal D2 of the amplifier 11. Here, too, the repetitive charging and discharging of the capacitor 79 produces a negative feedback unidirectional current signal which is proportional to the switching frequency; the capacitor 78 providing the smoothing of the feedback signal.

Amplifier 11 thus operates as an operational amplifier which sums the currents supplied through resistor 17 and transistor 76.

Thus, the amplifier and transfer or switching circuit shown in FIG. 3 provides a circuit wherein the output signal is a function of the input signal, the frequency of operation of the first transfer switching circuit, the input resistance value and the capacitance of the precision capacitor. Thus, in FIG. 3, the current equation is Z /C R F =Z where F is the frequency of transfer, R is the resistance of resistor 17 and C is the value of capacitor 79.

By connecting output terminal Z of FIG. 3 to input terminal Z of FIG. 2, a square root circuit is provided. That is, the circuit equation may be written as follows; Z =E E R C R F Z is defined as the input signal, E is the signal supplied by source 35 and the other parameters represent the capacitance or resistance of the respective components indicated by the subscript.

Lumping terms together, it may be shown that Z =KF. Thus, the input signal is proportional to the square of the frequency. By operating on both sides of the equation, the equation can be rewritten as F x Z By supplying this signal to the integrating portion of the network, the output counter will read EF /y/Z] dt or the total flow if the flow equation Q=K {K}? is utilized.

Moreover, from the preceding equations, it will be seen that output signal Z is a square-root-extracted voltage signal.

If now the circuits shown in FIGS. 2 and 3 are arranged to utilize three separate and independent inputs Z Z and E a multiplier/divider circuit is obtained. The output of the oscillator is applied to flip-flop 70 to control the operation of the respective transistors in the switching circuits, as noted supra. Using the equations noted supra, the circuit operation may be defined by equations Z,/R, =E C F. In addition, Z /R =2 {C 1 Rearranging the second equation and substituting into the first equation provides Since input Z is reversible in sign, this circuit is a twoquadrant multiplier.

Thus, it can be seen that the circuits shown hereinabove provide a linear voltage to frequency oscillator or converter. By supplying a suitable output device, the voltage to frequency converter can be utilized as a linear integrator. By supplying a suitable input circuit, in the nature of a transfer circuit similar to that shown in the linear VFC, a square root integrator may be provided. An intermediate signal may be used to produce a square root extractor voltage signal. By using the same circuits with independent input signals (but controlled by the same oscillator) a multiplier/divider circuit is obtained. Therefore, the circuit shown hereinabove provides a highly useful arithmetic circuit which may be utilized in many electronic devices.

Referring now to FIG. 4, there is shown a schematic diagram for a typical output control circuit. This circuit is useful with the circuits shown in FIG. 2 and similar components bear similar reference numerals. Transistor 68 is the transistor which has the base thereof connected via resistor 49 to the output of amplifier 13. Likewise, capacitor 71 is connected between the collector of transistor 68 and an output terminal of flip-flop 70. The emitter of transistor 68 is connected to ground. The collector of transistor 68 is further connected to a 1 2 volt source via resistor 69. It should be noted that capacitor 71 may be connected directly to the output of the oscillator circuit 14 to eliminate a division-by-two of the output' signal by flip-flop 70. Moreover, flip-flop 70', which has the toggle input thereof connected to the collector of transistor 68, may be eliminated if division of the pulses is undesirable. On the contrary, additional flip-flops may be included if frequency division is required.

In the configuration shown, a voltage

divider comprising resistors

103 and 104 is connected between one output of flipflop 70 and ground, The common junction of

resistors

103 and 104 is connected to the base of transistor 105.

Resistors

102 and 113 also form a voltage divider between another output of flip-flop 70' and ground. The base of transistor 106 is connected to the junction of

resistors

102 and 113. The collectors of

transistors

105 and 106 are connected to opposite ends of drive coil 109 which is associated with pulse motor 110, Counter 111 is connected to the shaft of pulse motor 110 via the mechanical coupling indicated by a dashed line. The anodes of

overload protection diodes

107 and 108 are connected together while the cathodes thereof are connected, respectively, to the collectors of

transistors

105 and 106. The common junction of the diode anodes is connected to center tap 114 of coil 109 and to the cathode of voltage regulating tube 112. This common junction is also connected to the l2 volt source. The anode of VR tube 112 is connected to a common junction of emitters of

transistors

105 and 106 which junction is further connected to ground,

In operation, transistor 68 is initially assumed to be nonconductive. The application of spike type signals to flip-flop 70 via capacitor 71 causes flip-flop 70 to produce alternating, square wave signals of opposite sense at the respective outputs. The signals supplied by the flip-flops 70 are applied to the bases of

transistors

105 and 106, respectively. Assuming initially a positive output signal being applied to the base of transistor 105, this transistor is nonconductive. Conversely, a relatively negative signal will then be applied to the base of transistor 106 via resistor 102 whereby transistor 106 is conductive. When transistor 106 is conductive, current exists in at least one portion of coil 109 whereby pulse motor 110 is driven and counter 111 records one increment or unit.

A further or subsequent pulse at capacitor 71 causes flipflop 70 to change states herein the signal supplied to the base of transistor 105 via resistor 103 is a relatively negative signal rendering transistor 105 conductive. A positive signal is applied to the base of transistor 106 via resistor 102 herein transistor 106 is nonconductive. Current now exists in the other portion of coil 109 wherein pulse motor 110 is, again, driven and counter 111 records another increment of operation. Obviously, the output frequency of the oscillator determines the frequency of alternation of flip-flop 70' and the application of signals to motor 110 and, thus, operation of counter 111. This indication by counter 111 produces an integration of signals supplied by the oscillator.

A calibration circuit comprising a series combination of capacitor 101 and resistor is connected between one terminal of flip-flop 70' and the l2 volt source. The calibration terminals are connected at the "12 volt source and the junction between resistor 100 and capacitor 101. Of course, this calibration circuit may be modified or eliminated as desired.

Referring no to FIG. 5, there is shown a schematic diagram of another embodiment of an oscillator. The oscillator is designated generally by reference numeral 14 and may be utilized to replace the oscillator 14 shown in FIG. 2.

The oscillator shown in FIG. 5 has the base of transistor 201 connected to an input terminal 200. The collector of transistor 201 is connected to ground. The emitter of transistor 201 is connected directly to the base of transistor 202 and, via resistor 203, to a +12 volt source is connected via capacitor 204 to the collector of transistor 202. The emitter of transistor 202 is connected via resistor 219 to ground. The collector of transistor 202 is further connected to the collector of transistor 205 which has the emitter thereof connected to the +12 volt source. The base of transistor 205 is connected to the anode of diode 207 while the cathode of diode 207 is connected to the +12 volt source.

The junction between the base of transistor 205 and diode 207 is connected to a positive source represented by terminal 209. In addition, this junction is connected via resistor 215 to the collector of transistor 218. The emitter of transistor 218 is connected to ground. The base of transistor 218 is connected to the collector of transistor 211. The base of transistor 211 is connected via resistor 206 to the collector of transistor 202. In addition, the base of transistor 211 is connected via series combination of resistor 216 and capacitor 217 to the collector of transistor 218. Diode 208 has the anode thereof connected to the base of transistor 211 and the cathode connected to the +12 volt source. Transistor 212 has the collector thereof connected to ground. The emitters of

transistors

211 and 212 are connected together and to one terminal of resistor 210 which has the other terminal thereof connected to the +12 volt source. The voltage divider

network comprising resistors

213 and 214 is connected between the +12 volt source and ground. The common junction of

resistors

213 and 214 is connected to the base of transistor 212.

This embodiment of the oscillator has been simplified by the omission of low limit cutouts and the like. Of course, such limit cutouts and other control circuits similar to those shown in the embodiment of FIG. 2 may be incorporated into the circuit shown in FIG. 5.

In operation, the circuit of FIG. 5 is quite similar to the circuit of FIG. 2. However, the SCS 63 has been eliminated and the capacitor discharge path comprises conventional transistor 205. In this circuit,

transistors

201 and 202 are connected to form a complementary Darlington current generator. The Darlington circuit is used to charge capacitor 204.

Transistors

211 and 212 are connected together as a differential comparator to detect the ramp voltage on capacitor 204. When the signal supplied to the base of transistor 211 is of proper magnitude, transistor 211 is rendered conductive. When transistor 211 is rendered conductive, a signal is supplied to the base of transistor 218 to produce regenerative action. Operation of transistor 218 turns on transistor 205 very rapidly and provides a very rapid discharge of capacitor 204. When capacitor 204 is discharged, the circuit returns to the initial conditions with

transistors

211, 218 and 205 turned off. The output signal can be supplied from the collector of transistor 218 to the flip-flop 70 of FIG. 2.

Thus, there has been described a circuit for producing arithmetic functions. The circuit, depending upon the connection thereof, will operate as a multiplier/divider, an integrator, a square root extractor and a linear voltage to frequency cona feedback circuit means connected between the output of said voltage controlled oscillator and said input terminal of said operational amplifier;

said feedback circuit means including conversion means responsive to the output of said oscillator for producing a direct current signal proportional to the frequency of the output signals from said oscillator;

an output means connected to the output of said oscillator;

said conversion means in said feedback circuit means comprising a reference signal means,

a storage capacitor,

switch means connected to be actuated at a frequency determined by the output signal from said oscillator,

said switch means being operatively connected to said storage capacitor to alternately connect said capacitor to be charged to the level of said input signal and discharged to the level of said reference signal,

a smoothing capacitor connected between said input terminal and ground,

said storage capacitor having one side connected to ground and the other side alternately connected by said switch means to said reference means and to said input terminal said input means including a second operational amplifier having an input terminal and an output terminal,

a feedback circuit means connected between the output of said voltage-controlled oscillator and said input terminal of said second amplifier,

said feedback circuit including conversion means responsive to the output of said oscillator for producing a direct current signal which is a function of the frequency of said output signals from said oscillator and of the signal at said output terminals of said second amplifier,

said conversion means in said feedback circuit means of said second amplifier including means connected to said output terminal of said second amplifier for establishing a second reference signal means,

a second storage capacitor having one side connected to ground,

second switch means connected to be actuated at the same frequency as said first mentioned switch means,

said second switch means being operatively connected to said second storage capacitor to connect the other side of said second capacitor alternately to said second reference means and to said input terminal of said second amplifier,

a smoothing capacitor connected between said input terminal of said second amplifier and ground, and

means connecting said output terminal of said second amplifier to the input terminal of said first mentioned amplifier.

2. The invention as set forth in claim 1 wherein said output means comprises a counter for integrating the output of said oscillator as a square root function of said input signal.

Claims

1. In combination, input means to which an input direct current signal may be applied; a voltage-to-frequency converter comprising an operational amplifier having an input terminal connected to said input means; a voltage-controlled oscillator connected to and controlled by the output of said operational amplifier; a feedback circuit means connected between the output of said voltage controlled oscillator and said input terminal of said operational amplifier; said feedback circuit means including conversion means responsive to the output of said oscillator for producing a direct current signal proportional to the frequency of the output signals from said oscillator; an output means connected to the output of said oscillator; said conversion means in said feedback circuit means comprising a reference signal means, a storage capacitor, switch means connected to be actuated at a frequency determined by the output signal from said oscillator, said switch means being operatively connected to said storage capacitor to alternately connect said capacitor to be charged to the level of said input signal and discharged to the level of said reference signal, a smoothing capacitor connected between said input terminal and ground, said storage capacitor having one side connected to ground and the other side alternately connected by said switch means to said reference means and to said input terminal said input means including a second operational amplifier having an input terminal and an output terminal, a feedback circuit means connected between the output of said voltage-controlled oscillator and said input terminal of said second amplifier, said feedback circuit including conversion means responsive to the output of said oscillator for producing a direct current signal which is a function of the frequency of said output signals from said oscillator and of the signal at said output terminals of said second amplifier, said conversion means in said feedback circuit means of said second amplifier including means connected to said output terminal of said second amplifier for establishing a second reference signal means, a second storage capacitor having one side connected to ground, second switch means connected to be actuated at the same frequency as said first mentioned switch means, said second switch means being operatively connected to said second storage capacitor to connect the other side of said second capacitor alternately to said second reference means and to said input terminal of said second amplifier, a smoothing capacitor connected between said input terminal of said second amplifier and ground, and means connecting said output terminal of said second amplifier to the input terminal of said first mentioned amplifier.