US3590224A

US3590224A - Device for generating a series f j of binary numbers

Info

Publication number: US3590224A
Application number: US762592A
Authority: US
Inventors: Bengt Roland Forsberg
Original assignee: US Philips Corp
Current assignee: US Philips Corp
Priority date: 1967-09-29
Filing date: 1968-09-25
Publication date: 1971-06-29
Anticipated expiration: 1988-06-29
Also published as: CH498460A; DE1774881A1; SE327435B

Abstract

A generating device for generating a series of binary numbers in predetermined sequence and employing a counter for counting a number of positions relative to a reference position on the carrier, a gating device controlled by the counter for opening the gating device at a particular counter position such that the particular position will be transmitted to a memory, the memory providing a plurality of stored positions, scanning of the carrier being affected with a speed such that at least one complete scan of the carrier is affected for each memory cycle readout, the memory then providing a control signal to the counter such that the counting means will produce a gating pulse to the gate at the pulsing of the next following position in the displacement cycle.

Description

United States Patent [54] DEVICE FOR GENERATING A SERIES F .1 OF

BINARY NUMBERS 6 Claims, 1 Drawing Fig.

[52] U.S. Cl 235/92, 340/ l 74.1 [51] Int. Cl 606m 3/02 [50] Field of Search 235/92, 25,

Primary Examiner-Maynard R. Wilbur Assistant Examiner-Joseph M. Thesz Attorney-Frank R. Trifari ABSTRACT: A generating device for generating a series of binary numbers in predetermined sequence and employing a counter for counting a number of positions relative to a reference position on the carrier, a gating device controlled by the counter for. opening the gating device at a particular counter position such that the particular position will be transmitted to a memory, the memory providing a plurality of stored positions, scanning of the carrier being affected with a speed such that at least one complete scan of the carrier is affected for each memory cycle readout, the memory then providing a control signal to the counter such that the counting means will produce a gating pulse to the gate at the pulsing ofthe next following position in the displacement cycle.

PATENTEDJUNZS I97! INVENTOR. B ENGT R. FORSBERG DEVICE FOR GENERATING A SERIES F J OF BINARY NUMBERS The invention relates to a device for successive generation of binary numbers in a predetermined series having a very extended repetition period by deriving (reading) binary sign elements from a carrier having sign elements arranged in lines under stepwise cyclic displacement of the reading position in each line for each reading preferably with displacement cycles with numbers of steps having no common factors, the binary numbers to be generated being composed by a sign element from each line on the carrier, which is scanned by mutual motion between the carrier and for each sign element line individual sensing means.

Previously, it has been proposed to generate binary series of different lines on the card by means of mutually and individually movable sensing means which are stepped forward synchronously relative to the stillstanding carrier, for example back and forth in the respective line. Resulting from the fact that the lines have different lengths the sensing means will for each operation cycle assume a different mutual position whereby a long interval is obtained before a certain mutual position of the sensing means reappears. Another previously known apparatus for generating such an extended series of binary numbers uses stillstanding sensing means and has the primary information arranged on individually and mutually movable subcarriers such as pinwheels of different periphery lengths which are stepped forward synchronously past the stillstanding sensing means.

The object of the invention is to achieve a generator for an extended series of binary numbers in which mutually unmovable for example stillstanding sensing means are combined with a carrier for the primary binary information of punchcard type in which thus also the primary binary elements assume a mutually fixed position.

The generating device according to the invention is characterized in that means are associated with each line for counting the number of passed positions of the sensing means relative to a reference position on the carrier, and gating means arranged between the respective sensing means and an associated memory means, which gating means are controlled by the counting means for instantaneous opening of the gating means at the passing of a position on the carrier determined by the counting means so that the sign element in this position will be transmitted to the associated memory means, means being furthermore arranged for taking-out the sign elements stored in the memory means, the scanning of the carrier being effected with so high speed that at least one complete scanning of the carrier is effected for each taking-out from the memory means and means being furthermore arranged to change the setting of the counting means after delivery from the memory means such that the counting means thereafter will produce opening pulse to the gating means at the passing ofa following position in the displacement cycle.

The invention is illustrated in the accompanying drawing, which shows a schematic view of a binary number generator according to the invention adapted to produce binary num bers of n-order and included in a ciphering machine.

In the drawing reference numeral designates a rotating drum of transparent material, for example plastic material, upon the outer surface of which a replaceable punchcard 11 is fastened. The drum rotates with relatively high speed, for example 2,400 rpm. whereby the reading period will 25 ms. Within the drum is situated an illumination device comprising a light source (not shown) and a reflector 12 which illuminates the inside of the drum along a line extending in axial direction. Opposite the light line outside the card there are a number of phototransistors each associated with its line on the card, which transistors sense presence of absence of hole in the different positions in the respective line. Illuminated phototransistors due to hole in a sensed position on the card results in a voltage pulse from the transistor, which in a way known per se can represent binary sign 1.

n phototransistors designated T,-T,, are arranged opposite those lines on the card, which comprises the basic information from which the series of binary numbers having a long repetition period is derived. For achieving the extended repetition period, these lines on the card comprise different numbers of positions, as will be more closely described in the following. Furthermore, there is a transistor T arranged opposite a line, which has a hole in each position. The pulses produced by T, are called clock pulses. The line of clock pulses on the card may have a hole only in each second position and the intermediate clock pulses produced by means of a time delay circuit, for example a monostable flip-flop with a predetermined return time. In the shown example there is a further phototransistor T, for producing a pulse, s 0 reference pulse, which appears in the interval between the reading periods, i.e., immediately before the reading transistors have reached a position opposite the first position in the lines. The reference pulses will thus appear once per revolution of the drum l0 and indicate that a new parallel reading of the lines on the card is to begin. The phototransistor T, can if desired be replaced by a device connected to T which is sensitive for the interval in the clock pulse series appearing between two reading periods.

The pulses from the transistors T --T,, are amplified in amplifiers A -A,, and then led to an input of an associated AND gate C -G The clock pulses are after a corresponding amplification in A led to the input of the binary counters C,-C, each associated with its line on the card. The counters C,C,, are set before reading of the card by means of setting counters, S,S,,, the individual stages of which are connected to the corresponding stage in the counters C,C, through AND gates G G, G,,,G,, (it has then been assumed that the counters have six stages). On a second input AND gates G G, -G,,,G,, receive the reference pulses from the transistor T, through an AND gate G The gate G has a second input connected to the treating unit of the ciphering machine, which input receives voltage for opening the gate at deliver of the previously produced binary number in the series of binary numbers. When voltage appears on this input the next following reference pulse will via the gates G G, G,,,G,, cause transferring of the setting of the counters 8 -8,, to the counters C,C,,.

The initial position of the counters S,S,, is determined by manually actuatable switches, which are schematically shown at 0 -0 The function of the switches O,O,, is to write into each counter a binary number which corresponds to the order number of the set position in an associated switch upon activation of a manually actuatable switch 0, The switches O O,, may for example consist of a number of movable contacts corresponding to the number of stages of the associated counter, which contacts for each position receive voltages which in binary shape represent the set position. Instead of the shown parallel setting of the counters S,---S, it is also possible according to another alternative to set the counters by a series method in that they are fed with a number of pulses corresponding to the set position.

The counters S,S, are during operation stepped forward in parallel by means of pulses from the treating unit of the ciphering machine, which pulses are applied to a terminal 13. As step-forward pulses those pulses may for example be used, which have for its purpose to release a pressed pushbutton in the ciphering machine, and which pulses indicated that the treatment of the sign selected by pressing the button has been terminated. It is assumed for the present that each such release pulse corresponds to one single pulse on terminal 13, whereby the counters S,S, are each time stepped forward one position.

The counters C,-C,, which are driven with the clock pulses from the phototransistors T,. are adapted to count backwards against zero from the wet initial position. A detector D -D senses when the respective counter has reached the position zero and delivers in this moment on opening voltage to the associated gate G -G and switch memory elements M,, M in a binary register R,.

The position in the respective line which is sensed by the reading transistors T,'l", and the binary sign of which is used for setting the memory elements in the binary register R is determined by the number stored in the respective counter C C, at the beginning of the reading procedure. As these counters are adapted to count backwards and reading is effected at zero position of thecounters, that position will be read, the order number of which corresponds to the initially stored number in the counters C,C,,. But this number is according to the foregoing determined by the setting of the counters S,S,,. The counters S,-S, are in the given example stepped forward one position for each new binary number and the positions in which reading is effected thus will be displaced for each new number one position in each line.

The series of binary numbers to be generated in derived from the memory elements M -M,,, in the register R At the same time as a number is derived for use in the treating unit of the ciphering machine emptying of the register is effected by means of a pulse on a terminal 14, which resets all memory elements to zero. The device is after emptying of R, ready for storing a new binary number in the register R, which is effected first by a pulse on terminal 13 so that the counters S,- S, are stepped forward, and thereafter pulse to the gate 0,, so that the next following reference pulse from T, will cause transmission of the new number in the counters S -S, to the counters C,C,,. During the following scanning of the card then a new number is written into the register R, by use of the binary signs in the positions on the card selected by the counters S S,,. The produced series of binary numbers will be determined on the one hand by the information on the card (inner key) and on the other hand by the initial position of the counters 8 -8,, which in turn is determined by the switches -0, (outer key).

' The counters S S, are of modulo M-type, where M indicates the length of the operation cycle of the counters. The modulo number M for each counter is selected equal to the number of positions in the associated line on the card. For achieving an extended repetition period of the produced series the modulo numbers for the different counters are further selected such that they have no common factors. The counters S,-S, have in a practical example six stages and the modulo number can thus amount to maximum 64.

It is common at the treatment of the generated binary numbers for producing superposition numbers that it is required to have simultaneously available two adjacent numbers in the series. This can be arranged in a simple way by connecting a second detector D,,D,,, to the backward operating clockpulse counter C,-C,,as shown by dotted lines in the drawing-which second detector produces opening pulse to gates G,G,, at the position 1 of the associated counter. The gates G,G, are like the gates G G,,,, supplied with the pulses from the reading transistor T -T, and a further input with the clock pulses. The pulses from the reading transistors passed by the gates G,--G, are used to switch memory elements M M in a second register R It is evident that the number stored in the register R will represent the foregoing number in the series of binary number. In order to prevent that double reading is made in this case two pulses are applied to the terminal 13 each time, so that the counters S,-S,, are stepped forward two positions In principle it is possible to have any ic scanning of the card can also be used. The counting means for counting the scanned position and activation of readingout of the binary sign in predetermined position can also be shaped in several ways. The counters controlled by the clock pulses canthus in the given example instead be adapted to count forward and readin initiated at coincidence between the setting of the clock pu se counter and the associated comparison counter. in principle it is also possible to have one single counter for each line, which counts the clock pulses and which can be set to produce an activation pulse for readingout from the card at certain setting positions of the counter which positions are varied from time to time.

What I claim is:

A generator for generating binary numbers in an extended series comprising, an information carrier having lines of binary elements of different lengths, a plurality of mutually nonmovable individual sensing means for each of said lines on said carrier, said carrier and said sensing means having mutual movement, gating means connected to each of said sensing means, memory means associated with each of said lines, counting means coupled to said sensing means and counting the number of positions passed by said sensing means relative to a reference position on a carrier, said gating means coupled to said counting means and responsive to a predetermined position of said counting means for instantaneously opening said gating means and thereby passing a sensed binary position to said memory means, means for reading the stored binary number out of said memory and means responsive to the readout of said memory for automatically changing the setting of said counter for producing a gating pulse to said gating means at the passing of a following position on said carrier.

2 A device as claimed in claim 1 wherein said counting means comprises a pulse counter associated with each of said lines, said pulse counter driven by means of clock pulses derived from said carrier.

3. A device as claimed in claim 2 further including means for presetting said counters on a position at he beginning of the scan, said means for presetting determining the position to be read.

4. The combination of claim 3 wherein said means for presetting said clock pulse counter comprises a further counter connected to said clock pulse counter such that at the beginning of said scan, the number stored in the position counter is transmitted to the respective clock pulse counter.

5. A combination of claim 4 wherein each of said counters are of a modulo M-type where M equals the number of positions in the associated line on the carrier.

6 A combination of claim 5 wherein said memory means is formed of two or more registers for simultaneously storing two or more numbers of said series, the means for setting said counters being adapted to stepped forward as many steps as the number of registers.

Patent No.

Dated June 29, 1971 Inventor() BENGT ROLAND FORSBERG It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

in the title,

Column 2,

Column 3,

line 62,

line 70,

line 74,

line 15,

line 60,

cancel "F J II "indicated" should be -indicate "wet" should be set- After insert which gates as previously mentioned on a first input receives the pulses from the reading transistors T T In order to center the reading moments selected by the AND- gates G -G to the middle of each position the clock pulses from T are further led to a third input of the gates G G At reception of voltage from the detectors D D i.e. in the moment when the number of the respective counter is zero, thus pulses if any from the reading transistors P -T will pass through the respective gate G G "in" should be -is After "positions" insert mg? UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 590,224 Dated June 29. 1971 Inventorfii) BENGT ROLAND FORSBERG PAGE 2 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 4, line l2, canthus" should be --can thus-- Column 4, line2l, before "A" insert l-- Claim -3, line 2, "he" should be the Signed and sealed this 11 th day of July 1972.

( SEAL) Attest:

EDHARD I-I.FLETCHER, JR. ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents

Claims

3. A device as claimed in claim 2 further including means for presetting said counters on a position at he beginning of the scan, said means for presetting determining the position to be read.
4. The combination of claim 3 wherein said means for presetting said clock pulse counter comprises a further counter connected to said clock pulse counter such that at the beginning of said scan, the number stored in the position counter is transmitted to the respective clock pulse counter.
5. A combination of claim 4 wherein each of said counters are of a modulo M-type where M equals the number of positions in the associated line on the carrier. 6 A combination of claim 5 wherein said memory means is formed of two or more registers for simultaneously storing two or more numbers of said series, the means for setting said counters being adapted to stepped forward as many steps as the number of registers.