US3588364A

US3588364A - Adaptive encoder and decoder

Info

Publication number: US3588364A
Application number: US725431A
Authority: US
Inventors: Errol E Wallingford; Ronald Bruce Morris
Original assignee: NAT DEFENSE CANADA
Current assignee: NAT DEFENSE CANADA; NATIONAL DEFENSE CANADA
Priority date: 1967-06-19
Filing date: 1968-04-30
Publication date: 1971-06-28
Anticipated expiration: 1988-06-28

Abstract

A TIME-MULTIPLEXED ENCODING AND DECODING SYSTEM FOR INCREASING AVERAGE INFORMATION ENCODED. ANALOG INFORMATION FROM PLURAL CHANNELS IS CONVERTED INTO DIGITAL FORM AND UNDER "NORMAL" CONDITIONS WHERE THE INFORMATION IS CONTINUALLY CHANGING THE CHANNEL ARE TRANSMITTED IN A PREDETERMINED SEQUENCE. UNDER "ADAPTIVE" CONDITIONS WHERE THE INFORMATION DOES NOT CHANGE OR CHANGES ONLY PARTIALLY BETWEEN SUCCESSIVE CHANNELS, SIGNALS FROM THE NORMALLY SCHEDULED CHANNEL ARE DELETED AND OTHER SIGNALS SUBSTITUTED THEREFOR.

Description

United States Patent inventors Errol E. Wallingford:

Ronald Bruce Morris, Kingston, Ontario, Canada Appl. No. 725,431

Filed Apr. 30, 1968 Patented June 28, 1971 Assignee Her Majesty the Queen in right of Canada as represented by the Minister of National Defense Priority June 19, 1967 Canada 993315 ADAPTIVE ENCODER AND DECODER 23 Claims, 9 Drawing Figs.

Int. Cl H04j 3/16 Field at Search 179/15 (A),

15 (AFC), 15 (Sig), 15, 55, 15 (ASYNC), l5 (BWR 325/38.1;332/l 1(D) ANALOG INPUT ANALOG INPUT SEQUENTIAL MULTIPLIXER COUNTER MASTER CLOCK [56] References Cited UNITED STATES PATENTS 3,372,237 3/1968 Hackett 179/15 3,478,266 11/1969 Gardenhire 325/38 Primary Examiner Kathleen H. Claffy Assistant ExaminerTom D. D'Amico Attorneys-R. S. Sciascia and A. L. Branning ABSTRACT: A time-multiplexed encoding and decoding system for increasing average information encoded. Analog information from plural channels is converted into digital form and under normal conditions where the information is continually changing the channel are transmitted in a predetermined sequence. Under adaptive conditions where the information does not change or changes only partially between successive channels, signals from the normally scheduled channel are deleted and other signals substituted therefor. I

JAN TRANSFER BUFFER REGISTER DI GI TA L COMPARATOR ADAPTIVE DETERMMINER 8 IDENTIFIER ADAPTIVE GATING SHIFT REGISTER NORMAL GATING PATENIEDJU-28|QH 3 5 354 SHEET 2 m 6 FIG. 2a

I N VE N TORS ERROL E. WALL INGFORD R. BRUCE MORRIS PATENTEnJunzsmn 3588.364

SHEET 3 UF 6 ADAPTIVE REGISTER NORMAL I NVE N TURS ERROL E. WALL/A/GFO/FD R BRUCE MORRIS BY M AGENT ATTORNEY PATENIED .JUN28 I871 SHEET 5 OF 6 llllllllllllll .Ill'llll .llllllllllllllulllnllll HBLSIOHH INVENTOKS ERROL E. WAL L lA/GFORD R BRUCE MORRIS BY K WAGENT ATTORNEY PMENIEnJumm-m BBBBQM SHEET 8 BF 6 FROM REG. 3 A

GROUP 0 GROUP B GROUP A A A A FROM REG. 3

GROUP A GROUP A GROUP 8 GROUP A IN VENTORS ERROL E. WALLINGFOHD R BRUCE MORRIS BY LA AGENT ATTORNEY ADAPTIVE ENCOlDlEI't AND lDlEtCODlEllt The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION This invention relates to time-multiplexed encoding systems and has for its object an encoding entropy increase, i.e. an increase in the average information encoded.

In a time-multiplexed system, a significant redundancy reduction can be obtained when the signal sources have a high probability of being inactive for long time intervals. By what is known as Shannons measure of average information content, i.e. entropy, these are low entropy signals and the advantage to be obtained is not an increase in information, as given by the present invention, but a saving in channel capacity over that required to send the redundant data directly.

Some prior systems claiming significant redundancy reduction rely on sources having a high probability ofbeing inactive for long time intervals. The present system takes advantage of short as well as long term redundancies due to either deterministic or random causes. The system is most advantageous with information sources having moderate to high information content requiring continuous monitoring but it may be used with low information sources as well.

The present system is ideally suited for telemetry applica tions where more information about the signal sources may be obtained under adaptive" conditions but where all possible available information need not necessarily be retained. The adaptive mode adds an extra sample of the changing data mid way between normal sampling intervals.

SUMMARY OF THE INVENTION According to one aspect of the present invention, a time multiplexed encoding system comprises a multiplexer ar' ranged to sample repeatedly in turn each of N channels, arranged to present the values of these samples in digital form as groups of digits, comparison means arranged to compare the groups of digits arising from one sampling with the group of digits arising from a subsequent sampling, to ascertain whether any change has taken place between these samplings, control means arranged to determine whether the output from the encoder shall consist, during each time cycle or word, of information on one sample only or alternatively information on two samples; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on any two groups of bits on one sampling is the same as the corresponding two groups of bits on the subsequent sampling, redundant information as to the unchanged samples is replaced with useful information derived from a third sample.

According to another aspect of the present invention, a time-multiplex encoding system comprising a multiplexer arranged to sample in turn each ofN channels (where N is odd) and arranged in each time cycle or word to sample a first channel, say channel (i), a first time and after a delay to sample a different second channel, say channel (i+1), and after a delay to sample a different third channel, say channel ([+2), and to present the value of the sample coded as three groups of bits; comparison means by which the data content in the first sampling is compared with the data content in the third sampling to ascertain whether any change has talten place in the data between the first and third sampling; control means arranged to determine whether the output from the encoder shall consist, during each time cycle or word, of information on one channel only or alternatively information on two channels; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on two groups of bits on the first channel (channel (1')) is the same as the corresponding two groups of bits on the third channel (channel (i+2)), the output from the encoder shall consist of the data on the remaining changed groups of bits of the third channel (channel (i+2)) and the most significant groups of bits of the second channel (channel (i+l and when the data on all three compared groups of bits is unchanged between the first sampling and the third sampling then the two most significant groups of bits of the second channel (channel (i+l are sent, while otherwise the output from the encoder consists of the data of the third channel (channel (i+2)).

According to still another aspect of the present invention, a time-multiplex encoding system comprises a multiplexer arranged to sample in turn each of N channels (where N is odd) and arranged in each time cycle or word to sample a channel a first time and after a delay to sample that channel a second time and after a further delay to sample that channel a third time and arranged to present the value of each sample coded as three groups of bits; comparison means by which the data content in the first sampling is compared with the data content in the third sampling to ascertain whether any change has taken place in the data between the first and third sampling; control means arranged to determine whether the output from the encoder shall consist during each time cycle or word of information relating to one of these samples only or alternatively consist of information on two of the samples; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on two groups of bits on the first sampling is the same as the corresponding two groups of bits on the third sampling, the output from the encoder shall consist of the data on the remaining changed group of bits ofthe third sampling and the most significant group of bits of the data on the second sampling, and when the data on all three compared groups of bits is unchanged between the first sampling and the third sampling then the two most significant groups of bits of the second sampling are sent, while otherwise the output from the encoder consists of the data ofthe third sample.

An object of the present invention is the provision of an information transmission system with an encoding entropy increase.

Another object is to provide an increase in the average information encoded by substituting other data for redundant data.

A further object of the invention is the provision of a timemultiplexed encoding system wherein redundant data is deleted and other data is inserted therefore.

BRIEF DESCRIPTION OF THE DRAWING Other objects and features of the invention will become apparent to those skilled in the art as the disclosure is made in the following description of preferred embodiments of the in vention as illustrated in the accompanying drawing in which:

FIG. I is a combined block and timing diagram of an adaptive encoder according to the present invention;

FIGS. 2a and 2b show details of portions of the encoder of FIG. I;

FIG. 3 is a combined block and timing diagram ofa decoder which can be used with the encoder of the present invention;

FIG. 4 shows details of portions of the decoder of FIG. 3;

FIG. 5 shows an alternative version of a register ofthe encoder shown in FIG. 2a.

FIG. 6 is a diagrammatic representation of one possible form of the repetitive time cycle or word on the output lead of the encoder of FIG. I during periods when the encoder is operating in a Normal mode;

FIG. 7 is a diagrammatic representation of one possible form ofthe repetitive time cycle or word on the output lead of the encoder during periods when the encoder is operating in an Adaptive mode; and

FIG. 8 is a diagrammatic representation of another alternative possible form of the word during operation in the Adaptive mode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, the adaptive encoder shown has N input terminals to which are fed N analog input signals from

sources

1, 2, ...N where N is any odd number. The function of the encoder shown is to provide on output lead 5 an electrical signal in the form of a sequence of 7-bit words. Under normal conditions each word conveys information regarding one of the N input channels while under "adaptive" conditions a 7-bit word may convey information regarding two of the N input channels.

In the embodiment shown in FIG. 1 the output on line 5, under normal" conditions, carries information on every other channel and, since there is an odd number of channels, all of the channels are covered before the sequence is repeated. Thus, for example, if there are 11 channels the order in which the channels are reported on line 5 would be I, 3, 5, 7, 9, ll, 2, 4, 6, 8, 10, 1,3, 5, etc. Under adaptive" conditions, i.e. conditions where the information on normally consecutive channels does not change or changes only partially, the information in a 7-bit word on line 5 may refer to a channel different from the one normally scheduled.

The N channel inputs are connected to a sequential multiplexer 7 which sequentially samples the N inputs and places these samples in order on line 6. The sequential multiplexer is stepped by signals received on line 8 from ring counter 11. This ring counter in turn may be stepped by pulses from master clock 9.

The output from multiplexer 7 is applied to analog-to-digital converter 13 and is immediately converted into a 6-bit digital format by a known successive approximation analog-to-digital technique. As soon as the conversion is complete, the digital output signals are applied to jam transfer buffer register 15 which actually comprises three separate registers, Reg. 1, Reg. 2 and Reg. 3 as shown in FIG. 2a.

Digital samples of successive inputs or channels are first stored in Register 3 ofjam transfer buffer register 15 and then shifted to the right into Register 2 and then Register 1. The six digits in each of the three registers are divided into three pairs or groups A, B and C'and the digits in Register 3 are compared with the digits in Register 1. The logic gating of comparator 19 is such that if two or more of the groups A, B, and C have changed between Register 3 and Register 1, the output on lead 23 from adaptive determiner and identifier 21 puts a one in the first position of the serial output shift register 31. This one is a code for a normal word to follow in the next 6bit positions. The logic gating of comparator 19 is also such that when only one or none of the three groups A, B and C is different in Reg. 3 and Reg. 1, the output on lead 23 from adaptive determiner and identifier 21 places a zero in the first position of serial output shift register 31. This zero bit is a code for an adaptive word to follow in the next 6-bit positions. Two types of adaptive words are possible one for cases where only one of groups A, B and C is different, and the other for cases where none of groups is different. These types of adaptive words will be described with reference to FIGS. 7 and 8.

FIGS. 6, 7 and 8 show various types of word patterns which could occur in output shift register 31. A normal word pattern is shown in FIG. 6 with a one in the first position (reading from the right) followed by six data bits from Reg. 3. The most significant bit of the six bits follows immediately after the first bit with the next most significant bits following in order. Two possible adaptive words are shown in FIGS. 7 and 8. The right hand bit is zero in both of these figures meaning that an adap- In FIG. 7 the first bit (starting from the right) is a zero meaning that an adaptive word is to follow. The next two bits are zero and one meaning that a change has occurred in group A. The following two bits are taken from Reg. 2 and are the two most significant bits in that register. The last two bits are the group A bits from Reg. 3.

In FIG. 8 the first bit (again starting from the right) indicates an adaptive word follows, the next two bits indicate no change from Reg. 1 to Reg. 3, and the final four bits are the four most significant bits from Reg. 2.

The timing of the system shown in FIG. 1 is controlled through a 14 stage ring counter 11. Multiplexer 7 advances two positions or channels for each cycle of 14 clock pulses from master clock 9 and the clock frequency is chosen to ensure that data on each channel is sampled at least at its Nyquist rate. The bit rate of the output signal on lead 5 is equal to one-half of the frequency of master clock 9. Two successive channels or signal sources on the N input terminals are sampled once each during each l4 pulse cycle by switching in multiplexer 7 during the first and eighth time periods of ring counter 11. It is noted that during normal" operation only one of these samples is used, the other being discarded. A delay unit 12 (whose delay is a small fraction of the master clock period) is incorporated to ensure that the multiplexer switching does not occur simultaneously with analog-to-digital conversion.

tive rather than a normal word is to follow. The next two bits identify which group (if any) is different between Reg. 1 and Reg. 3 and these two bits are chosen according to the following code: (I zero followed by one means that group A is different, (2) one followed by zero means group B is different, (3) one followed by one means group C is different and (4) zero followed by zero means no group is different. From this code, it can be seen that FIG. 7 represents a situation where only group A has changed and FIG. 8 represents a situation where Register 3 and Register 1 agree completely.

The representation of the ring counter 11 in FIG. 1 illustrates how the 14 time periods [I to I14 of each cycle are utilized in the encoder operation.

Referring first to FIG. 1, the time periods :1 to I14 are utilized as follows:

t1: The A/D converter 13 reads an analog input source or channel i, converts this to digital format and stores in jam transfer-buffer register 15 in register Reg. 3. When conversion is complete, after a short delay the sequential multiplexer moves to the i+l channel input position. The contents of serial output register 31 shift one position.

12: Idle :3: The last digitally stored data in the adaptive identifier 21 is cleared. The contents of serial output register 31 shift one position.

t4: Idle :5: The comparator 19 compares the contents of register Reg. 1 with the contents of register Reg. 3. The contents of serial output register 31 shift one position.

t6: Idle :7: Enables Adaptive gating 29 or Normal gating 27 to read in data form registers Reg. 2 and Reg. 3. Also reads in normal or adaptive word identity into first output position of output serial register and code for adaptive group in next two positions if adaptive. After a short delay (short compared to a clock period) to allow for read-in, the contents of serial output register 31 are shifted one position.

:8: The A to D converter 13 reads analog input source or channel i+l, converts to digital format and stores in jam transfer buffer register 15 in register Reg. 3 while channel i data moves to register Reg 2 when conversion is complete.

!9: Contents of the serial output register 3] shift one position.

: Idle :11: Contents of the serial output register 31 shift one position.

:12: Idle 113: Contents of the serial output register 31 shift one position.

114: Idle It is to be noted that although twochannels are sampled in each frame of the ring counter, 11, only one channel data is normally transmitted through lead 5,. Thus normally the lead 5 carries information in consecutive frames on

inputs

1, 3, 5, 7-- -

N

3, 5, 7N, 2, 4, 6,--(Nl Table I below shows typical jam transfer buffer register channel allotments during successive output frames for the version of the adaptive encoder shown in FIG. 1 with N=l, 3,

7 or II channels. Larger numbers of channels would follow the same pattern.

TABLE 1 Reg. 3 Reg. 2 Reg. 1 Reg. 3 Reg. 2 Reg. 1

Ch. 2 Ch. 1 Ch. 1 Ch. 3 Ch. 3 Ch. 2 Ch. 2 Ch. 1 etc. etc.

Reg.3 Reg 2 Reg. 1 Reg 3 Reg 2 Reg 1 .3 Ch. 2 Ch. 1 Ch. 4 Ch. 3 .7 Ch. 6 Ch. 5 H Ch. 8 011.7 .11 Ch. Ch. 9 2 Ch. 1 Ch. 11 .4 Ch. 3 Ch. 2 6 Ch. 5 Ch. 4 .8 Ch. 7 Ch. 6 .10 Ch. 9 Ch. 8

1 Ch. 11 011.10 3 011.2 Ch. 1

etc etc Referring to Table l, the first column for each value of N shows the information channel present in Register 3 of jam transfer buffer register 15, i.e. the normal readout channel. The second column is Register 2 or the Possible adaptive channel. The third column is Register ll, i.e. the channel data sent in the previous word which has been stored for comparison purposes. Choosing N=7 for descriptive purposes, successive cycle output channel words of data which are sent during normal operation are given to the first column, i.e. 3, 5, 7, 2, A, 6 and 1. Whenever an adaptive mode of operation is indicated, as determined by comparator I9 and adaptive determiner 211, information as to this normal channel is still conveyed but information as to

channels

2, 4t, 6, ll, 3, 5 and 7 is interspersed adaptively.

FIGS. 2a and 2b show portions of FIG. l in more detail. The logic circuitry shown is merely exemplary and other combinations could be easily designed by one skilled in the art to carry out the operations described above with reference to FIG. 1. Jam transfer buffer register 15 is shown to contain three registers Reg. 3, Reg. 2 and Reg. l. The data first enters Register 3 and then is shifted to Register 2, and then Register ll. Corresponding bits in the three registers may be arranged like 3- bit shift registers under the control of shift signals on line 14]. A signal on this line occurs after the analog-to-digital conversion has been completed. The new data is shifted into Reg. 3 while the earlier data shifts to Register 2 and Register ll.

Comparator 1'9 functions to compare the individual bits in Register 3 with the bits in Register it. This comparison may be carried out by using Exclusive-or gates 2M206 which receive corresponding bits from the two registers and produce outputs only if the compared bits differ. The comparison is done at time r3 under the control of an enabling signal on line 20. In order to divide these six bits into the three groups A, B and C, the outputs from the Exclusive-or gates are applied in pairsto OR gates 211 ll--21l3 so that outputs occur on

lines

283, 234 and 235 only if groups A, B, and C, respectively, are different in Reg. 3 and Reg. E. The signals on lines 233-285 are used to control storage units, 2211, 222 and 223 in FIG. 2b so that if, for example, line 285 indicates that group A has changed from Reg. l to Reg. 3, the bits of group A from Reg. 3

are stored in storage unit 223. If group A is the only group which has changed, the new group A bits are gated at time :7 over

lines

71 and 72 to the trailing two positions in shift register 31. The outputs on lines 233233 are also inspected to determine if more than one group has changed. This is done by AND gates 23l-233 which will produce at least one output if signals occur on two or more of lines 233-283. The outputs from AND gates 2311-233 are fed to OR gate 234 so that an output occurs on line 23 only if changes have occurred in at least two of groups A, b and C. In such a case a normal word is to be transmitted, so line 23 enables normal gating unit 27 to allow six bits from Reg. 3 to be placed in shift register 31 and a one to be placed in the first position of this shift register. Normal gating unit 27 allows these signals to pass to shift register 31 at time 17 when gate control signals are present on both line 213 and line 23. The signal on line 23 also serves to inhibit adaptive gating unit 29 which is adapted to pass adaptive signals only if no signal is present on line 23.

The signals on lines 233, 23 i and 235 may be used to produce the group identifying code for the adaptive mode. OR gates 233 and 236 are sufficient to accomplish this. As explained above, in the adaptive mode the second and third bits in each output word identify which group (if any) is different between Reg. I and Reg. 3. These two bits are controlled by lines 73 and MI, and it can be seen from FIG. 2a that if only group A has changed a one will occur on line 73 and a zero will occur on line 74. If only group B has changed a one will occur on line 74 and a zero will occur on line 73. If only group C has changed a one will occur on both lines 73 and 7 1. If more than one group has changed, a one occurs on line 23 which inhibits adaptive gating unit 29' and prevents the signals on

lines

73 and 74 from reaching shift. register 31. If no change has occurred from Reg. I to Reg. 3 a. zero will appear on line 237 which is inverted to a one by inverter 233 and is applied to storage unit 22d. This enables storage unit 224 to receive the group B digits from. Reg. 2 so that in an adaptive mode of the type illustrated in FIG. 8 four bits from Reg. 2 are transferred to shift register 31. A signal on line 290 at time I3 is used to clear the data stored in storage units 2211-224.

Operation of the decoder to be used in the system may best be understood by reference to FIG. 3. The decoder accepts the incoming PCM serial bit stream from lead 5 into a seven stage serial shift register 30. Once frame sync has been achieved the seven bits of the input serial shift register 30 are read in parallel to a buffer register 32 and an adaptive identifier 35 looking at the first bit signifies a normal or adaptive word. If adaptive, it looks at the code signal on the next two "bits and enables the appropriate adaptive gating for read out on t7 of a ring counter 37. The last six bits of data from buffer register 32, if normal, are shifted in parallel to a buffer register 39 at time [7 prior to being read out at time :14 to their proper channel through the sequential demultiplexer 3-11 or, if adaptive, are gated according to the adaptive identifier code to their proper bit-pair positions through the sequential demultiplexer dl to their correct output channel buffer registers 43, 44, 45, etc. and simultaneously, the unaffected least significant bit positions are loaded with zeros. The detailed timing of the decoder operation is best described by successive shifts of the ring counter 37.

Decoder Timing tll Serial shift register 30 shifts one bit.

12 Idle.

t3 Serial shift register 30 shifts one bit.

Ml Idle.

t5 Serial shift register 30 shifts one bit.

to Idle.

t7 Serial shift register 30 shifts one bit. Channel demultiplexer 41 shifts one position. IfAdaptive, reads in changed pair to register 39 and reads in 2 or 4 M88 through demultiplexer 4'1 to appropriate channel.

t3 Idle. [9 Serial shift register 30 shifts one bit. (It) Idle.

till Serial shift register 30 shifts one bit.

I12 Idle.

113 Serial shift register 30 shifts one bit.

:14 Parallel shift from serial register 30 to buffer register 32; Parallel shift from buffer register 39 through demultiplexer 41 to proper output channel.

Channel demultiplexer 41 shifts one position.

A possible detailed embodiment of portions of FIG 3 is shown in FIG 4. Of course, there are many combinations of logical gating circuitry which could accomplish the decoding objectives described above, but FIG. 4 shows one exemplary arrangement. Adaptive identifier 35 is arranged to receive the three leading bits in each 7-bit word and determine whether the word is normal or adaptive. If the word is found to be adaptive, adaptive identifier 35 further determines what type of adaptive word is involved and the identity of the other ele- 101 (equivalent to Reg. 1 of FIG 2a). The contents of register Reg. 101 and Reg. 103 are compared and as before the two values of group A will be compared, the two values ofgroup B will be compared, and the two values of group C will be compared. If two or more of the groups A, B and C have changed between registers Reg. 103 and Reg. 101, then a normal frame containing all the six digits is sent. On the other hand, if only one, or none, of the three groups A, b and C is different between registers Reg. 103 and Reg. 101, the output in lead 23 places a zero in the first position ofthe serial output register on read-in command t7 from the ring counter 11. It will be seen that this operation is the same as that described with reference to FIG. 1.

Table II below is similar to Table l but relates to an arrangement in which there are (N+l) stages in the buffer register.

TABLE II Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg.103 102-1 102-2 101 103 102-1 102-2 102-3 102-4 102-5 102-6 101 1 3 1 1 7 6 5 4 3 2 1 3 2 3 3 2 1 7 6 5 4 3 2 1 3 2 5 4 3 2 1 7 6 5 1 3 2 1 7 6 5 4 3 2 1 7 2 1 7 6 5 4 3 2 4 3 2 1 7 6 5 4 6 5 4 3 2 1 7 6 1 7 6 5 4 3 2 1 ments in the adaptive word. AND gate 401 includes inhibit inputs connected to the first two bits of the received word and two ordinary inputs connected to the third bit and to the seventh stage of ring counter 37. It can be seen that gate 401 will emit a signal at time :7 only ifa one occurs in the third bit of the received word and zeros occur in the first two bits. This condition occurs only if the adaptive word indicates that only group A has changed and in such a case the new group A bits are located in the last two bits of the received word as illustrated in FIG. 7. The output of gate 401 enables gates 411 so that these last two bits are passed to their proper positions in buffer register 39. AND

gates

402 and 403 perform functions similar to gate 401 but in respect to changes in group B and Group C, respectively. An exemplary code word for the situation where only group A has changed is shown in FIG. 7. In such a case the fourth and fifth code bits (counting from the right in FIG. 7) represent group A from Register 2 and these two bits are passed by gate 415 at time :7 to demultiplexer 41 to be read into the appropriate channel. Gate 415 is not enabled by gate 405 unless a zero occurs in the first bit of the received word. In situations where no group A, B, or C has changed, zeros occur in all of the first three bits of the received word (as shown in FIG. 8) and

gates

404 and 405 emit signals at time :7 to open

gates

414 and 415 and pass four bits from the adaptive word to demultiplexer 41.

If a normal word is received, a one occurs in the first bit so that AND gate 407 emits a signal at time :7. This signal opens gates 416 so that the last six bits in register 32 are shifted to register 39. Later at time r14 the information in register 39 is supplied to demultiplexer 41.

As can be seen from FIG. 3, demultiplexer 41 distributes the b-bit words to

appropriate registers

43, 44, 45, etc. from which they are converted by digital-to-analog converters 53, 54, 55, etc. into analog signals.

Referring now to FIG. 5, this illustrates a modification to the arrangement of FIG. 2a for use where the redundancies are likely to occur in the same channel rather than between different channels. The difference lies in the jam transfer buffer register designated 15 in FIG. Zaand designated 115 in FIG. 5. In order to compare consecutive samplings of the same channel, it is necessary to have N+I stages in the buffer register 115. Then the input from channel say (i'+3) will be fed into register Reg. 103 (equivalent to register Reg. 3 of FIG. 2a) and will move two stages every complete time frame ofthe ring counter 11 of FIG. 1. When channel (i'+3) is again read, the first sample will have progressed to the last register, Reg.

The additional information to be sent during adaptive frames is determined by the buffer stage which is selected to act as stage Reg. 102. If it is desired to provide during Adaptive operation additional information on the changing channel, then by the use of (ZN-+1) buffer stages the middle buffer stage will contain intermediate information on the channel being sampled. In this manner, when the variable applied through one channel is varying at a rapid rate in which two of the groups A, B and C change between first and third samplings, normal operation provides information as to the first and third samplings only, but if the variation is slower, so that only one of these groups of digits changes between the first and third samplings, then information as to the value of this changing group is provided from the second (intermediate) sampling.

Table III shows typical successive channel allotments for N=5 channels, as in Table II, but using 2N+I buffer stages. This table makes it clear that there is a complete choice of which channel is to be sampled when working in the Adaptive mode. The central stage has been indicated as Reg. 102 to show how an intermediate value of the two values compared from stages Reg. 103 and Reg. 101 can be used.

TABLE III (N=5) Reg.

When the modification shown in FIG. 5 is used, it is necessary to incorporate N-l additional buffer storages in the decoder of FIG. 3, these buffer storages being arranged subsequent to register 39 with the last stage cycled back to the first stage.

The multiplexed adaptive encoder/decoder system which has been described above is basically a conventional PCM system with a self-adaptive feature which improves the average information (entropy) encoded by going into an adaptive mode whenever two or three pairs of bits on two compared channels remain unchanged for two successive normal sampling intervals. In the adaptive mode two or four additional data bits from another channel are sent along with any changing data from the compared channels.

It will be seen that the system which has been described does not compact the output signal by omitting redundant information, i.e. in this case by omitting information that a measured quantity has remained unchanged since the previous sampling operation. The system does not compact the output signal, but instead, when conditions are suitable, conveys more information than an orthodox system about another signal source. The described system can give an important gain in efficiency when the signals to be multiplexed are suitable. For example, when all three compared pairs of bits are dormant, the system is percent efficient and four additional most significant data bits are transmitted about another channel.

When only one out of three compared pairs of bits is experiencing a change, then the comparator senses a system which is only 33.3 percent efficient when operating in the normal mode. ny the present invention, the comparator and adaptive determiner can cause the system to operate in the Adaptive mode and two additional most significant data bits are transmitted about another channel. This represents a 100 percent increase in efficiency during the time the system is adaptive. This improvement normally occurs only a fraction of the total time, dependent on the amplitude and frequency characteristics of the source channels, hence the average in formation gain will normally be considerably less.

Should only one pair of compared bits be inactive, then the normal system is 66.6 percent efficient and no further gain can be realized.

The adaptive system design is intended to improve the efficiency of information transfer by increasing data transfer. The object is to achieve as much increase as possible while requiring a minimum increase in hardware for both encoder and decoder. The design further requires that no feedback chan nel, from decoder to encoder, is necessary. The system described satisfies the criteria of adaptive operation, namely that it monitors its own performance, learns about changing conditions, and adapts its operation to these new conditions.

The system described is a 6-bit N channel system which makes use of short duration redundancies in multiplexed data, eliminating these and simultaneously substituting data into the vacancies. The optimum number of channels has been found to be any odd number, and the optimum number of bits per channel has been found to be six. The optimum word length has been found to be seven hits total, made up of ii information bits, three pairs of two bits each, plus an at ptive identifier bit. The added adaptive identifier bit is neces y and serves to indicate to the receiving apparatus whether the following six bits are from an adaptive word or from a normal word.

Additional entropy comes from allowing the sources to have a maximum frequency component of 2 Wit-l2. instead of as in a conventional system, and sampling these sources at a l Wl'lz. Nyquist rate rather than at the more conventional 2 WI-lz. rate (where W is the bandwith of the communication channel in question), The extra samples from each channel are temporarily stored in the buffer register, and whenever this additional information can be added to the fixed word length transmission channel this is done. Otherwise the additional information is automatically destroyed as it is shifted out of the jam transfer buffer register.

The system described above is well suited to telemetry applications where more information about the signal sources can be obtained under adaptive conditions but where all possible available information need not necessarily be retained. it is not suited to systems whose sources are optimally encoded as the extra data bit required over a conventional system would decrease the coding efficiency. But for many real signal sources moderate to considerable gains are possible dependent on the nature of the redundancies. The adaptive encoder according to FIG. 5 is best suited when redundancies occur on ill the same channel, and that of FIG. l for redundancies between channels.

Qbviously many modifications and variations ofthe present invention are possible in the light of the above teachings. it is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

We claim:

T. An encoding system comprising:

store means, including at least three multidigit registers each of which contains a plurality of groups of plural digit storage means, to temporarily store a succession of multidigit signals;

compare means to compare a first of said multidigit signals with a later one of said multidigit signals and connected to said store means to compare said groups of signals in a first and a third of said multidigit registers;

logic means connected to said compare means to determine if a majority of said groups differs between said first and said third registers; first gating means to selectively transmit said later signal dependent upon the results of said determination and second gating means to selectively substitute a multidigit signal other than said first and said later signals for transmission in place of at least some of the digits ofsaid later signal.

2. The system of claim 1 wherein said logic means is connected to said first gating means to allow transmission of said later signal when a majority of said groups differs between said first and said third registers.

3. The system of claim ll wherein said logic means is connected to said second gating means to substitute a multidigit signal other than said first and said later signal for transmission in place of at least some of the digits of said later signal when less than a majority of said groups differ between said first and said third registers.

d. An encoding system comprising:

at least three multidigit signal registers for storing a plurality of successively received multidigit signals,

means to shift the multidigit signals from a first of said registers to a second of said registers;

means to shift the multidigit signals from said second register to a third of said registers;

means to compare the multidigit signal stored in said first register with the multidigit signal stored in said third register;

first gating means to selectively transmit the multidigit signal stored in said first register dependent upon the results ofsaid comparison;

second gating means to selectively substitute portions of the multidigit signal stored in said second register for transmission in place of some of the: digits of the multidigit signal stored in said first register.

5. The system of claim 4 wherein said means to shift the multidigit signals from a first of said registers to a second of said registers comprises at least one additional multidigit signal register.

ii. The system of claim 5 wherein said means to shift the multidigit signals from said second of said registers to a third of said registers comprises at least one additional multidigit signal register.

7. The system ofclaim l wherein each of said registers comprises at least three groups of plural digit storage means,

8. The system of claim 7 wherein said means to compare comprises at least three group comparators for comparing groups of signals from the three groups of storage means in said first multidigit storage register and said third multidigit storage register.

it. The system of claim b further including logic means for evaluating the outputs of said group comparators to determine if changes have occurred in a majority of said groups.

ill. The system of claim 9 wherein said logic means controls said first gating means to transmit the multidigit signal stored in said first register when a majority of said groups in said third register differs from corresponding groups in said first register.

11. The system of claim 9 wherein said logic means controls said second gating means to substitute at least one group of the multidigit signal stored in said second register for transmission in place ofa group of digits from said first register.

12. A time-multiplexed encoding system comprising a multiplexer arranged to sample repeatedly in turn each ofN channels, arranged to present the values of these samples in digital form as groups of digits, comparison means arranged to compare the groups of digits arising from one sampling with the group of digits arising from a subsequent sampling, to ascertain whether any change has taken place between these samplings, control means arranged to determine whether the output from the encoder shall consist during each time cycle or word of information on one sample only or alternatively information on two samples; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on any two groups of bits on one sampling is the same as the corresponding two groups ofbits on the subsequent sampling, redundant information as to the unchanged samples is replaced with useful information derived from a third sample.

13. An encoding system as claimed in claim 12 wherein the output from the multiplexer is applied to an analog-to-digital converter the digital output from which is stored in a register until the comparison means are activated.

14. An encoding system as claimed in claim 12 wherein an analog-to-digital converter converts the analog input into a digital output having six bits and the bits are used as three groups of two bits.

15. An encoding system as claimed in claim 12 wherein an analog-to-digital converter converts the analog input into a digital output, a buffer register stores each digital output until it has been used for comparison purposes, and the control means control the reading out of the buffer register in parallel to a serial output shift register providing the useful output from the encoding system.

16. A time-multiplexed encoding system comprising a multiplexer arranged to sample in turn each ofN channels (where N is odd) and arranged in each time cycle or word to sample a first channel say channel (i) a first time and after a delay to sample a different second channel say channel (i+l) and after a delay to sample a different third channel say channel (i+2) and to present the value of the sample coded as three groups of bits; comparison means by which the data content in the first sampling is compared with the data content in the third sampling to ascertain whether any change has taken place in -the data between the first and third sampling; control means arranged to determine whether the output from the encoder shall consist during each time cycle or word of information on one channel only or alternatively information on two channels; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on two groups of bits on the first channel (channel (1')) is the same as the corresponding two groups of bits on the third channel (channel (i+2)), the output from the encoder shall consist of the data on the remaining changed group of bits of the third channel (channel (i+2)) and the most significant group of bits of the second channel (channel (i-H and when the data on all three compared groups of bits is unchanged between the first sampling and the third sampling then the two most significant groups of bits of the second channel (channel (i+1)) are sent, while otherwise the output from the encoder consists of the data of the third channel (channel (i+2)).

17. An encoding system as claimed in claim 16, wherein the output from the multiplexer is applied to an analog-to-digital converter the digital output from which is stored in a register until the comparison means are activated.

18. An encoding system as claimed in claim 16, wherein an analog-to-digital converter converts the analog input into a digital output having six bits and the bits are used as three groups each of two bits.

19. An encoding system as claimed in claim 16, wherein an analog-to-digital converter converts the analog input into a digital output, a buffer register stores each digital output until it has been used for comparison purposes, and the control means control the reading out of the buffer register in parallel to a serial output shift register providing the useful output from the encoding system.

20. A time-multiplexed encoding system comprising a multiplexer arranged to sample in turn each ofN channels (where N is odd) and arranged in each time cycle or word to sample a channel a first time and after a delay to sample that channel a second time and after a further delay to sample that channel a third time and arranged to present the value of each sample coded as three groups of bits; comparison means by which the data content in the first sampling is compared with the data content in the third sampling to ascertain whether any change has taken place in the data between the first and third sampling; control means arranged to determine whether the output from the encoder shall consist during each time cycle or word ofinformation relating to one of these samples only or alternatively consist of information on two of the samples; and adaptive means activated by the comparison means and effective to control the control means in such a manner that, when the data on two groups of bits on the first sampling is the same as the corresponding two groups of bits on the third sampling, the output from the encoder shall consist of the data on the remaining changed group of bits of the third sampling and the most significant group of bits of the data on the second sampling, and when the data on all three compared groups of bits is unchanged between the first sampling and the third sampling then the two most significant groups of bits of the second sampling are sent, while otherwise the output from the encoder consists of the data of the third sample.

21. An encoding system as claimed in Claim 20, wherein the output from the multiplexer is applied to an analog-to-digital converter the digital output from which is stored in a register until the comparison means are activated.

22. An encoding system as claimed in Claim 20, wherein an analog-to-digital converter converts the analog input into a digital output having six bits and the bits are used as three groups each of two bits.

23. An encoding system as claimed in Claim 20, wherein an analog-to-digital converter converts the analog input into a digital output, a buffer register stores each digital output until it has been used for comparison purposes, and the control means control the reading out of the buffer register in parallel to a serial output shift register providing the useful output from the encoding system.