US3587065A - Circuit arrangement for generating steep flanked pulses to a magnetic memory - Google Patents

Circuit arrangement for generating steep flanked pulses to a magnetic memory Download PDF

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Publication number
US3587065A
US3587065A US710180A US3587065DA US3587065A US 3587065 A US3587065 A US 3587065A US 710180 A US710180 A US 710180A US 3587065D A US3587065D A US 3587065DA US 3587065 A US3587065 A US 3587065A
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United States
Prior art keywords
voltage
source
load
circuit
circuit arrangement
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Expired - Lifetime
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US710180A
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English (en)
Inventor
Rudolf Kuntze
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Siemens AG
Siemens Corp
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Siemens Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/64—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors having inductive loads
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/12—Shaping pulses by steepening leading or trailing edges

Definitions

  • SHEET 2 OF 2 .aY ATTYSJ CIRCUIT ARRANGEMENT FOR GENERATING STEEP FLANKED PULSES TO A MAGNETIC MEMORY BACKGROUND OF THE INVENTION The invention is directed to a circuit arrangement for generating current impulses with very steep flanks. Circuits of this type are employed, for example, in magnetic core storage matrices in connection with the production of writing and reading impulses therefor.
  • Circuit arrangements have been designed in the past in which a constant current source is alternately connected and disconnected with a point of load (a current impulse source) and a source of voltage necessary to supply the required voltage to the current impulse source.
  • a current impulse source a point of load
  • the voltage source is so timecontrolled that upon operative connection of the constant current source it delivers during the brief period of the buildup processes a high voltage and following the buildup condition is makes available considerably lower voltage.
  • This form of operation greatly reduces the circuit losses as a high operating voltage is required only during the rise of the current impulse to overcome inductive resistances, while a lower operating voltage of the constant current is sufficient to thereafter cover the circuit losses.
  • a particular disadvantage of circuit arrangement such as above described resides in the fact that a remote-controlled switch is necessary for actuation of the time-dependent voltage source.
  • an additional circuit is required which performs the function of controlling the current impulse source in accordance with the switching frequency to provide a control impulse for the time-dependent voltage source.
  • Such an additional circuit is avoided in a circuit according to the invention by an arrangement in which the portion of the time-dependent voltage source which, during the buildup processes, applies the full operating voltage to the current impulse source, comprises a capacitor and a switch controlled directly by the current impulses at the point of load.
  • the circuit arrangement according to the invention thus has the special advantages that, in addition to simple design and low cost of the components, in particular in the fact that automatic operation of the circuit is achieved, eliminating the necessity of a control impulse for governing the time-dependent voltage source.
  • the invention contemplates the utilization of the charge of a capacitor to provide an initial high voltage for the buildup operation taking place at the load point upon initiation of a current impulse, following which a lower voltage is applied.
  • a transistor is utilized as a switch to control the charging of the capacitor with the switch, i.e. the controlling element of the transistor, being operatively connected to the load point and thus controlled by the conditions thereat.
  • the transistor will permit a charging while the pulse source is disconnected from the load point and upon connection of such current source discharge of the capacitor will take place with the transistor being switched to a condition during which no charging action takes place, such transistor remaining in such state while the load point remains at the lower operating voltage until the current source is again disconnected following which the transistor will be switched to permit charging of the capacitor.
  • FIG. 1 is a circuit diagram illustrating an embodiment of the invention, represented in simplified form
  • FIG. 2 is a chart illustrating the voltage course at the load point
  • FIG. 3 illustrates a practical application of the circuit of FIG. I.
  • FIG. 4 illustrates another application of the circuit arrangement ofFlG. l.
  • the reference numeral 1 indicates generally a constant current source which is adapted to be operatively connected to the load point of 3, by means of a switch 2.
  • a time-dependent controlled source indicated generally by the numeral 5, which is enclosed by broken lines.
  • the time-dependent voltage source 5 comprises the relatively low operating voltage source 6, having a voltage U1, which is likewise connected to the point 4 over a diode 7, as is the so-called charge circuit A, likewise enclosed by broken lines.
  • the charge circuit A comprises a transistor 8 having its base connected over ohmic resistance 9 and its collector over another ohmic resistance 10 to the relatively high operating voltage source 11, having a voltage U2. Bridging the voltage source 11 and the emitter of the transistor 8 is a capacitor 12, with the emitter of the transistor being connected to the point 4 over a diode 13 while the base of the transistor is connected directly to the point 4.
  • the transistor 8 will be blocked by the drop in potential taking place across diode l3 and even when the voltage at point 4 has reached the lower voltage U1, current from the source 6 flowing over the diode 7, the transistor 8 will not become conductive. However, if the switch 2 is now opened, the bias on the base of the transistor 8 again reaches a value reestablishing conduction of the transistor 8 and recharging of the capacitor 12.
  • FIG. 2 illustrates the source of the voltage of the time-dependent voltage source 5 at the point 4 of FIG. 1 with the voltage remaining at U] until the switch 2 is opened, at which time the voltage increases from UI to U2 during the time interval 20, commensurate with the charge of the capacitor.
  • the switch 2 is closed, the voltage of the time-dependent voltage source initially drops to the lower operating voltage U1 at which level it remains during the remainder of the time interval 21.
  • FIG. 3 illustrates an application of a circuit arrangement in accordance with FIG. I to a magnetic core matrix for a matrix-like control of the line or column conductors thereby.
  • both ends of a line or a column conductor 30 are independently connected for reading or writing in series with a diode matrix 31 and respective address switches 32 whereby one of the time-dependent voltage sources 33 is connected at one end of the series circuit for writing or reading purposes, while the other end a single constant current source 34 is provided for cooperation with the two time-dependent voltage sources.
  • FIG. 3 presents a slight variation in the time-dependent voltage source as compared with FIG. 1 in that the capacitor and the ohmic resistances are not at the same voltage.
  • the operation of the circuit of FIG. 3 compares substantially to that of FIG. I with respect to operation, the respective address switches being so actuated that in one operational state, as for example writing, a series circuit will be formed from the right hand time-dependent voltage source 33 over the corresponding address switch 32 and diode matrix 31 to the conductor 30, over the same to the lower left hand diode matrix 31 and address switch 32 to the constant current source 34.
  • the left hand time-dependent voltage source 33 may be connected over the corresponding address switch 32 and diode matrix 31, the conductor 30 (reverse flow), lower right diode matrix 31 and lower right address switch 32 to the constant current source 34.
  • FIG. 4 illustrates another application of the circuit arrangement corresponding to the arrangement of FIG. 1 involving linear control of the line or column conductors of a magnetic core matrix.
  • one end of the line or column conductor 40 is connected to a reference potential, while the other end may be connected by respective address switches 41 or 42 to respective time-dependent voltage sources and constant current sources 43 or 44 respectively, each constant current source being connected in series with the associated ti medependent voltage source.
  • an additional diode is disposed in parallel across each capacitor which is so poled that it will become conductive when the capacitor has been discharged to the lower operating voltage.
  • a circuit arrangement for generating current impulses with very steep flanks to a load comprising: arelatively low voltage source coupled to the load, an electronic switching means, a relatively high voltage source, a charging circuit, said relatively high voltage source being coupled to said charging circuit to produce a build up of voltage therein, said charging circuit and said relatively high voltage source being normally uncoupled from'said load by said electronic switching means,
  • bias means capable of being coupled to the load for causing said electronic switching means to conduct to discharge the build up of voltage therein through said load, whereby a relatively high operating voltage'is initially coupled to said load and a much lower voltage is coupled to the load subsequent thereto to cover circuit losses.
  • a circuit arrangement according to claim 1 in combination with a magnetic core matrix, a diode matrix, with which the line or column conductors of the magnetic core matrix are connected in series, and address switches operatively connected therewith, one time-dependent voltage source being provided at one end of each series circuit, and a single current impulse source, provided for two time-dependent voltage sources, disposed at the opposite ends of the corresponding series circuits.
  • a circuit arrangement according to claim 1 in combination with a magnetic core matrix in which one end of the respective line or column conductors is connected to reference potential, a first time-dependent voltage source and a first constant current source connected in series therewith and an address switch operatively connecting said first voltage and current sources to the opposite end of such line or column conductor, a second time-dependent voltage source and a second constant current source connected in series therewith, and a second address switch operatively connecting said second voltage and current sources to said opposite end of such line or column conductor.
  • a circuit arrangement in accordance with claim 1 wherein said bias means causing said switching means to conduct comprises a constant current source, switching means being provided to couple said constant current source to said load to turn on said electronic switch and initiate discharge of said charging circuit therethrough.
  • said charging circuit includes a transistor, a capacitor and a biasing arrangement therefor which turns on the transistor to build up a voltage in the charging circuit and which turns off the transistor when said buildup of voltage is being discharged through said load.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)
  • Static Random-Access Memory (AREA)
US710180A 1967-03-10 1968-03-04 Circuit arrangement for generating steep flanked pulses to a magnetic memory Expired - Lifetime US3587065A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0108744 1967-03-10

Publications (1)

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US3587065A true US3587065A (en) 1971-06-22

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US710180A Expired - Lifetime US3587065A (en) 1967-03-10 1968-03-04 Circuit arrangement for generating steep flanked pulses to a magnetic memory

Country Status (4)

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US (1) US3587065A (enrdf_load_stackoverflow)
BE (1) BE711915A (enrdf_load_stackoverflow)
GB (1) GB1197696A (enrdf_load_stackoverflow)
NL (1) NL6803260A (enrdf_load_stackoverflow)

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Publication number Publication date
BE711915A (enrdf_load_stackoverflow) 1968-09-09
GB1197696A (en) 1970-07-08
NL6803260A (enrdf_load_stackoverflow) 1968-09-11

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