US3582903A - For transferring information between a central unit and peripheral elements - Google Patents

For transferring information between a central unit and peripheral elements Download PDF

Info

Publication number
US3582903A
US3582903A US772781A US3582903DA US3582903A US 3582903 A US3582903 A US 3582903A US 772781 A US772781 A US 772781A US 3582903D A US3582903D A US 3582903DA US 3582903 A US3582903 A US 3582903A
Authority
US
United States
Prior art keywords
transfer
peripheral
register
control unit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US772781A
Inventor
Henri Louis Verdier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull General Electric NV
Original Assignee
Bull General Electric NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR128535A external-priority patent/FR1566177A/fr
Application filed by Bull General Electric NV filed Critical Bull General Electric NV
Application granted granted Critical
Publication of US3582903A publication Critical patent/US3582903A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Definitions

  • the invention concerns a data processing ELEMENTS system comprising a central unit and peripheral unlts of dif- 22 mm ferent types connected to the said central unit through two 11.8. CI. 340/1725 transfer channels, and wherein each peripheral element is pro- Int. Cl G06!
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Document Processing Apparatus (AREA)

Abstract

THE INVENTION CONCERNS A DATA PROCESSING SYSTEM COMPRISING A CENTRAL UNIT AND PERIPHERAL UNITS OF DIFFERENT TYPES CONNECTED TO THE SAID CENTRAL UNIT THROUGH TWO TRANSFER CHANNELS, AND WHEREIN EACH PERIPHERAL ELEMENT IS PROVIDED WITH A FUNCTIONAL CONNECTING SYSTEM WHICH ENABLES IT TO BE CONNECTED TO THE CENTRAL UNIT WITHOUT ANY NECESSITY TO MODIFY THE CIRCUITS OF THE CENTRAL UNIT IN ORDER TO ADAPT IT TO THE OPERATION OF THIS ELEMENT.

Description

United States Patent Inventor App]. No.
Filed Patented Assignee Priority Henri Loni Verdler Paris, France Nov. 1, 1968 June 1, 197 l Societe lndustrl'elle Bull-General Electric (Soeiete Anonylne) Perk, France Nov. 16, 1967,.Iln. 24, 1968 France 128,535 and 137,206
DEVICES FOR TRANSFERRING INFORMATION BETWEEN A CENTRAL UNIT AND PERIPHERAL [56] References Cited UNITED STATES PATENTS 3,029,414 4/1962 Schrirnpf 340/l 72.5 3,181,121 4/1965 Losch et a1. 340/1715 3,215,987 1 1/1965 Terzian 340/1725 3,243,781 3/1966 Ehnnan et a1. 340/1725 3,434,118 3/1969 Svoboda et a1. 340/ 172.5
Primary Bxaminer-Gareth Dr Shaw i me ms i ig e/ e is P- Binge-Em! Neuhauser, Joseph B. Forrnan and Oscar B. wfidii ABSTRACT: The invention concerns a data processing ELEMENTS system comprising a central unit and peripheral unlts of dif- 22 mm ferent types connected to the said central unit through two 11.8. CI. 340/1725 transfer channels, and wherein each peripheral element is pro- Int. Cl G06! 3/00, vided with a functional connecting system which enables it to G061 3/04 be connected to the central unit without any necessity to Fieldolsareli 340/1725; modify the circuits of the central unit in order to adapt it to 235/15 7 the operation of this element.
(GMTRQA. SELECrION flit-ems 0 Meme? y 17 '81! Q) 12 raj-Li "1 2275222" nco .snwoav 21 EVDO RVCQ 00 Try r RIG/S TEX L1 MUJ FWD 1 PER/P1152161. EL E MEN? BLF.4
UTA
INPU EEG/5 TEE OIITPUT EEG SYER PATENTED JUN nan 3,582,903
SHEET 03m 19 REG/S T'EK SELEcrI 0N CON "r201.
MEM 0825 DA TH MEMO? Y ION REG/S TIR ADDfiESS REOUCIP A 002555 ADVANCE PAD MAD REA REGISTER DECODER BET I SIGNHLL 1N6 DEVICE PATENTEU JUN 1 l97l SHEET us or 19 A UX/L 142 y CONTBQL,
PATENTED JUN 1 l97| SHEET 03 [JF 19 oscoosz 256157512 PATENTEDJUH nan 3,5 2 903 sum near 19 PATENIED JUN I I97! SHEET 10 0F FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG.
FIG. 30
FIG.
FIG.
FIG.
FIG.
FIG.3
PATEN TED JUN 7 I97! SHEET 11 or 19 EVCQ 2555252,?
i-H XREPJ sac 35 I R105 h-I PATENTED JUN 1 I97! sum 13 or 19 BER DR.
F0. rppgg 7.01: TR
DEODEE PATENTEDJUN Hen 3.582.903
SHEET 1'; [1F 19 REGISTER VDQ DKR pECaOE R X X BRP PATENTED JUN 1 l97| sum 15 or 1 PUL s E GE/VRATcR PATENTEDJUN Hen 3582.903
SHEET 17UF 19 PULSE GENEEA roe 1.1
FIG. 3C

Claims (14)

  1. 2. A data processing system according to claim 1, wherein each peripheral element and the instruction register of the associated connecting system are connected to the first channel through an input register, having a capacity of one character, and in which the central control unit comprises in addition a permanent data register which is connected to the first channel and which permanently contains a special character representing a signal indicating the availability of the central unit, the control means of the central control unit being designed to bring about, in response to the reception in the code-order register of a code order sent by a functional connecting system, the transfer of the said special character to the input register of the said connecting system, the local control unit of the said connecting system comprising a decoder connected to the said input register and designed to generate a control signal when the latter register contains the said special character, and a switching assembly connected to the said decoder and to the associated peripheral element to initiate the operation of the said element, in response to the reception of a control signal.
  2. 3. A data processing system according to claim 2, wherein each peripheral element and the order memory of the associated connecting system are connected to the second channel through an output register which has a capacity of one character, the input register being connected to the first channel through a first gate, the said output register being connected to the second channel through a second gate, the said system comprising in addition a plurality of first conductors equal in number to the peripheral elements, each of the said conductors being connected between the switching assembly of a local control unit and the control means of the central control unit in order to transmit to the said control means a character transfer demand signal sent by the said switching assembly, and a number of second conductors equal to the number of peripheral elements, each of the said second conductors being connected between the switching assembly of a local control unit and the control means of the central control unit in order to traNsmit to the said switching assembly a transfer control pulse generated by the said control means in response to a character transfer demand signal sent by the said switching assembly, the said switching assembly being designed to emit a character transfer demand signal in response to the reception of a control signal sent by the decoder, and to transmit a first transfer control pulse emanating from the central control unit, either to the first gate or to the second gate, depending upon the direction of transfer specified by the instruction contained in the instruction register, in order to initiate the transfer of the first of a series of transfer characters, the said switching assembly also being designed to emit thereafter successive transfer demand signals, in response to each of which a transfer control pulse is transmitted to the said assembly and applied to one of the two gates in order to initiate the transfer of a corresponding character.
  3. 4. A data processing system according to claim 3, wherein the instruction memory, the data memory and the permanent data register of the central control unit are connected to the first channel through an output register of the central unit, having a capacity of one character, and wherein the data memory and the code-order register of the central control unit are connected to the second channel through an input register of the central unit, which has a capacity of one character, the output register of the central unit being designed to contain temporarily, either each of the successive characters which are extracted from the instruction memory or from the data memory, or the special character indicating the availability of the central unit, the input register of the central unit being intended to contain temporarily, either each of the successive characters which are successively sent by a peripheral element and are to be stored in the data memory, or a code order which, after having been extracted from the order memory of a functional connecting system, is sent to the central unit, the transfer of a character contained in the output register of the central unit to the input register associated with a peripheral element being initiated by the application of a transfer control pulse to the corresponding first gate, the transfer of a character contained in the output register associated with a peripheral element to the input register of the central unit being initiated by the application of a transfer control pulse to the second gate associated with this peripheral element.
  4. 5. A data processing system according to claim 4, wherein the permanent data register is composed of a first stage which permanently contains the special character representing a signal indicating the availability of the central unit, and of a second stage which contains a particular coded character, called the ''''operating'''' character, which is intended to establish in the switching assembly of a local control unit the switching necessary for the control of the storage of an instruction in the associated instruction register, the said second stage being connected to the output register of the central unit to transmit the said ''''operating'''' character to the said output register, under the control of the control means of the central control unit, the transfer of the said character to the input register of a chosen peripheral element for performing an operation being initiated by the application, to the first gate associated with this peripheral element, of a first transfer control pulse generated by control means of the central control unit and transmitted through the switching assembly of the local control unit associated with the said element.
  5. 6. A data processing system according to claim 5, wherein the instruction register of each of the functional connecting systems is connected to the input register associated with the said system through a third gate subject to the control of the switching assembly of the local control unit of the said System, the decoder of this control unit being also adapted to generate a recognition signal when this input register contains an ''''operating'''' character, the said switching assembly also being adapted to transmit to the control means of the central control unit, in response to the reception of a recognition signal sent by the decoder, a series of character transfer demand signals, for applying to the first gate the first transfer control pulse sent by the control means, so as to initiate the transfer of the first character of an instruction contained in the output register of the said central unit to the said input register, and in addition to apply the said first pulse with delay to the third gate in order to bring about the transfer of this first character contained in the input register into the corresponding instruction register, the transfer of the succeeding characters of this instruction being effected similarly by the application, to the first gate and then to the third gate, of the transfer control pulses generated by the control means of the central control unit.
  6. 7. A data processing system according to claim 6, wherein the instruction register of each of the functional connecting systems comprises, for the storage of an instruction, a number of stages equal to the number of characters constituting this instruction, each instruction comprising a predetermined number of characters established in relation with the nature of the associated peripheral element, including at least one character indicating an operation to be performed, each of the stages of the instruction register being intended to store the corresponding one of the characters of the said instruction.
  7. 8. A data processing system according to claim 7, wherein each local control unit comprises in addition a second decoder connected to that one of the stages of the associated instruction register which is intended to contain the operation-indicating character for performing the decoding of the said character and producing signals indicating the result of the said decoding, the switching assembly of the said local control unit being connected to the said second decoder in order to receive the signals generated by the said decoder and also being adapted to control the operation of the associated peripheral element, in response to the signals received, in order to perform the operation specified by the said operation-indicating character, this operation consisting either in an operation for reading or writing characters on an information-recording medium, or in a positioning of the said medium.
  8. 9. A data processing system according to claim 8, wherein each local control unit comprises in addition means for indicating the state of a register, which are connected on the one hand to the associated instruction register for detecting the state of occupation of the stages of this register and generating a particular signal as soon as all the characters of an instruction have been transferred into the said register, and on the other hand to a first corresponding conductor for transmitting this particular signal to the control means of the central control unit in order to establish in the said means the switching necessary for the control of the storage, in the code-order register, of a code order emanating from the order memory associated with the said local control unit, the transfer of this code order from this order memory to the associated output register being initiated simultaneously with the dispatch of the said particular signal to the control means of the central control unit.
  9. 10. A data processing system according to claim 9, wherein the code-order register is connected to the input register of the central unit through a gate subject to the control of the control means of the central control unit, the said control means being adapted to transmit a transfer control pulse to the said local control unit, in response to the reception of a particular signal emanating from a local coNtrol unit, in order to initiate the transfer of the code order contained in the output register associated with this local control unit to the input register of the central unit and to transmit a pulse to the said gate in order to produce the transfer of the said code order contained in the input register of the central unit to the code-order register.
  10. 11. A data processing system according to claim 10, wherein the central control unit comprises in addition a signal-differentiating member connected on the one hand to the first conductors to receive the signals sent by the local control units and on the other hand to the control means of the central control unit to establish in the said control means a switching which differs in accordance with whether the signal received through a first conductor is a character transfer demand signal or a particular signal sent by a local control unit at the end of the transfer of an instruction into the associated instruction register.
  11. 12. A data processing system comprising a central unit including a central control unit and memory means; a plurality of peripheral elements; said memory means storing data and peripheral control instructions, each of said peripheral control instructions being adapted to control a peripheral element to perform a respective operation; input data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said memory means to said peripheral elements; output data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said peripheral elements to said memory means; a peripheral controlling member coupled to said peripheral elements to control the operation thereof, said peripheral controlling member including an instruction register, an instruction decoder coupled to said instruction register and responsive to the instruction contents thereof to generate a peripheral control signal representative of said instruction contents, an order memory for storing a plurality of code orders, and a local control unit; each of said code orders being adapted to control said central unit to cooperate with a peripheral element in the execution of a respective peripheral operation; said central control unit controlling the retrieval of said peripheral control instructions from said memory means and the transfer of said retrieved instructions from said central unit to the instruction register of said peripheral controlling member; said local control unit responding to the entry of an instruction into said instruction register and controlled by the corresponding peripheral control signal to retrieve the corresponding code order from said order memory and to control the transfer of said retrieved code order to said central control unit; said central control unit being responsive to a code order received thereby for configuring said central unit to participate with the corresponding peripheral element in the execution of the respective peripheral operation represented by said code order received.
  12. 13. A data processing system comprising a central unit including a central control unit and memory means; a plurality of peripheral elements; said memory means storing data and peripheral control instructions, each of said peripheral control instructions being adapted to control a peripheral element to perform a respective operation; input data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said memory means to said peripheral elements; output data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said peripheral elements to said memory means; a plurality of peripheral controlling members coupled to said peripheral elements to control the operation thereof, each of said peripheral controlling members including an instruction register, an instruction decoder coupled to said instruction register and resPonsive to the instruction contents thereof to generate a peripheral control signal representative of said instruction contents, an order memory for storing a plurality of code orders, and a local control unit; each of said code orders being adapted to control said central unit to cooperate with a peripheral element in the execution of a respective peripheral operation; said central control unit controlling the retrieval of said peripheral control instructions from said memory means and the transfer of said retrieved instructions from said central unit to the instruction registers of the corresponding peripheral controlling members; each of said local control units responding to the entry of an instruction into the respective instruction register and controlled by the corresponding peripheral control signal to retrieve the corresponding code order from the respective order memory and to control the transfer of said retrieved code order to said central control unit; said central control unit being responsive to a code order received thereby for configuring said central unit to participate with the corresponding peripheral element in the execution of the respective peripheral operation represented by said code order received.
  13. 14. The apparatus of claim 13, wherein, when the instruction received by a peripheral control member specifies an operation to transfer data from said memory means to a peripheral element, the respective local control unit retrieves from the respective order memory a code order denoting the requirement for a data transfer from said memory means to a peripheral, and wherein said central control unit responds to said code order to activate said input data transfer means for transfer of data.
  14. 15. The apparatus of claim 13, wherein, when the instruction received by a peripheral control member specifies an operation to transfer data from a peripheral element to said memory means, the respective local control unit retrieves from the respective order memory a code order denoting the requirement for a data transfer from a peripheral element to said memory means, and wherein said central control unit responds to said code order to activate said output data transfer means for transfer of data.
US772781A 1967-11-16 1968-11-01 For transferring information between a central unit and peripheral elements Expired - Lifetime US3582903A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR128535A FR1566177A (en) 1967-11-16 1967-11-16
FR137206A FR93930E (en) 1967-11-16 1968-01-24 Improvements to devices allowing the transfer of information between a central unit and peripheral elements

Publications (1)

Publication Number Publication Date
US3582903A true US3582903A (en) 1971-06-01

Family

ID=26180889

Family Applications (1)

Application Number Title Priority Date Filing Date
US772781A Expired - Lifetime US3582903A (en) 1967-11-16 1968-11-01 For transferring information between a central unit and peripheral elements

Country Status (3)

Country Link
US (1) US3582903A (en)
FR (1) FR93930E (en)
GB (1) GB1207710A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3729713A (en) * 1971-08-04 1973-04-24 Ibm Data processing peripheral subsystems
US4225917A (en) * 1976-02-05 1980-09-30 Motorola, Inc. Error driven interrupt for polled MPU systems
US4271466A (en) * 1975-02-20 1981-06-02 Panafacom Limited Direct memory access control system with byte/word control of data bus
US4287560A (en) * 1979-06-27 1981-09-01 Burroughs Corporation Dual mode microprocessor system
US4291372A (en) * 1979-06-27 1981-09-22 Burroughs Corporation Microprocessor system with specialized instruction format
US4292667A (en) * 1979-06-27 1981-09-29 Burroughs Corporation Microprocessor system facilitating repetition of instructions
US4293909A (en) * 1979-06-27 1981-10-06 Burroughs Corporation Digital system for data transfer using universal input-output microprocessor
US4371931A (en) * 1979-06-27 1983-02-01 Burroughs Corporation Linear micro-sequencer for micro-processor system utilizing specialized instruction format
US4669060A (en) * 1982-03-17 1987-05-26 Institut Francais Du Petrole Device associated to a computer for controlling data transfers between a data acquisition system and an assembly comprising a recording and reading apparatus
US6598178B1 (en) * 1999-06-01 2003-07-22 Agere Systems Inc. Peripheral breakpoint signaler

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3029414A (en) * 1958-08-11 1962-04-10 Honeywell Regulator Co Information handling apparatus
US3181121A (en) * 1957-12-12 1965-04-27 Int Standard Electric Corp Electronic programme-control
US3215987A (en) * 1962-06-04 1965-11-02 Sylvania Electric Prod Electronic data processing
US3243781A (en) * 1961-10-06 1966-03-29 Sperry Rand Corp Digital communication system
US3434118A (en) * 1964-05-01 1969-03-18 Vyzk Ustav Matemat Stroju Modular data processing system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3181121A (en) * 1957-12-12 1965-04-27 Int Standard Electric Corp Electronic programme-control
US3029414A (en) * 1958-08-11 1962-04-10 Honeywell Regulator Co Information handling apparatus
US3243781A (en) * 1961-10-06 1966-03-29 Sperry Rand Corp Digital communication system
US3215987A (en) * 1962-06-04 1965-11-02 Sylvania Electric Prod Electronic data processing
US3434118A (en) * 1964-05-01 1969-03-18 Vyzk Ustav Matemat Stroju Modular data processing system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3729713A (en) * 1971-08-04 1973-04-24 Ibm Data processing peripheral subsystems
US4271466A (en) * 1975-02-20 1981-06-02 Panafacom Limited Direct memory access control system with byte/word control of data bus
US4225917A (en) * 1976-02-05 1980-09-30 Motorola, Inc. Error driven interrupt for polled MPU systems
US4287560A (en) * 1979-06-27 1981-09-01 Burroughs Corporation Dual mode microprocessor system
US4291372A (en) * 1979-06-27 1981-09-22 Burroughs Corporation Microprocessor system with specialized instruction format
US4292667A (en) * 1979-06-27 1981-09-29 Burroughs Corporation Microprocessor system facilitating repetition of instructions
US4293909A (en) * 1979-06-27 1981-10-06 Burroughs Corporation Digital system for data transfer using universal input-output microprocessor
US4371931A (en) * 1979-06-27 1983-02-01 Burroughs Corporation Linear micro-sequencer for micro-processor system utilizing specialized instruction format
US4669060A (en) * 1982-03-17 1987-05-26 Institut Francais Du Petrole Device associated to a computer for controlling data transfers between a data acquisition system and an assembly comprising a recording and reading apparatus
US6598178B1 (en) * 1999-06-01 2003-07-22 Agere Systems Inc. Peripheral breakpoint signaler

Also Published As

Publication number Publication date
GB1207710A (en) 1970-10-07
FR93930E (en) 1969-06-06

Similar Documents

Publication Publication Date Title
US3200380A (en) Data processing system
US3573741A (en) Control unit for input/output devices
US3818447A (en) Priority data handling system and method
US4509113A (en) Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
US3582903A (en) For transferring information between a central unit and peripheral elements
US3500466A (en) Communication multiplexing apparatus
US3237164A (en) Digital communication system for transferring digital information between a plurality of data processing devices
GB1108804A (en) Improvements relating to electronic data processing systems
US3560933A (en) Microprogram control apparatus
GB1441128A (en)
US3283306A (en) Information handling apparatus including time sharing of plural addressable peripheral device transfer channels
US3812475A (en) Data synchronizer
US3781821A (en) Selective shift register
US3333250A (en) Buffering system for data communication
GB1357028A (en) Data exchanges system
GB1249209A (en) Machine for transferring data between memories
GB1107661A (en) Improvements in or relating to data processing apparatus
US3475729A (en) Input/output control apparatus in a computer system
US4006456A (en) Loop fault location and isolation
US3456244A (en) Data terminal with priority allocation for input-output devices
US3230508A (en) System for the simultaneous step-by-step setting of a number of movable elements
US3046528A (en) Transfer mechanism for storage devices
US3544966A (en) Method and apparatus for multiplex control of a plurality of peripheral devices for transfer of data with a central processing system
US3139607A (en) Synchronous communication system with nonsynchronous terminals
GB1234473A (en)