US3569683A - Apparatus for determining the optimum combination of one or more of a set of sublengths for a given overall length - Google Patents

Abstract

The following specification discloses a computing apparatus for automatically determining the optimum combination of one or more of a set of M sublengths for a given overall length comprised of a selected one of said M sublengths and a selected one of a set of N incremental lengths such that the sum of the elements of the optimum combination is the largest possible value less than the overall length.

Description

I United States Patent 1 3,569,683

72 Inventor Charles D. Pugh 5 References Cited 21] A I No 23 33 UNlTED STATES PATENTS 3,246,550 4/1966 Galey et al 235/151. lX [22] Filed Mar. 14, 1968 3319 055 5/1967 Patented Mar. 9 97 v Pavenko et al. [73] Assignee Burlington Industries, Inc. Primary Examiner Eugene G. Botz Greensboro, N.C. Assistant Examiner- David H. Malzahn Attorney-Cushman, Darby and Cushman [54] APPARATUS FOR DETERMINING THE OPTIMUM COMBINATION OF ONE OR MORE OF A SET OF SY OVERALL LENGTH ABSTRACT: The following specification discloses a computalms rawmg ing apparatus for automatically determining the optimum [52] U.S. Cl 235/152, combination of one or more of a set of M sublengths for a 235/ 150.1, 83/72 given overall length comprised of a selected one of said M [5 l Int. Cl G06f 15/46 sublengths and a selected one of a set of N incremental lengths [50] Field of Search 235/152, such that the sum of the elements of the optimum combination is the largest possible value less than the overall length.

4 A? DEF-501 m cur LENGTH I" LOGIC clzcurr LOGIC (-IG- 3) cnzcu n- I KEYBOAEU READ our (Frq 2) --1r------ (Flt;- 5c) I SCANNIN SIGNAL PATl-II l Clacu rr' OHZcurr I G U IG' 6 PATENTED MAR 9197i SHEET 8 4 OF R O T v N E V m 6% QWNK [#04 159 i. Paws www ATTORNEY PATENIED MAR 9197:

SHEET [3 5 OF SI'IEET U 7 OF PATENTED MR 9 IHYI I Illllllallllullllllll.Iallllli \v \K mm 3 if E K C imm PATENTEU MAR 9 I971 SHEET (3 8 BF PATENTEU MAR 919m SHEET 0 9 BF H Ci LP EEEEE %\h mkh k km Mn U PATENTEU MR 9 I97! SHEET 1 1 0F agssasea PATENTEUHAR 9mm SHEET 1 2 [JF The present invention relates to computing apparatus and more particularly to apparatus for automatically determining the optimum combination of a plurality of given lengths into which a given overall length of material can be divided such that the amount of wasted material is minimized. ,l,

In industrial processes wherein a long, continuous material, having random defects, is to be cut into one of a predetermined set of cut lengths, a considerable problem arises in attempting to obtain a maximum yield of the raw material. This can be understood by considering the situation wherein a defect appears in the material at a distance from the end which is less than the length of the cut being made. .Under these circumstances, the length of material from the end to the defect would have to be discarded because it would be an odd length.

in the textile industry, for example, long, continuous lengths of cloth are cut into various predetermined lengths for the purpose of making articles such as drapes and the'like. Due to the manufacturing process of the cloth, however, defects occur such as seams, holes, spots and the like, which prohibit the sale of that portion of the material whereat the defect occurs, as first quality products.

In order to better understand the above-mentioned problem and the manner in which the present invention solves it, the remainder of the specification will deal with .the use of the present invention in the textile industry and specifically to the cutting of material for drapes. It is to be understood, however, that the present invention is applicable in general to situations wherein an overall length, comprised of an incremental length and one of a plurality of sublengths is to be divided into a plurality of said sublengths, the sum of which is the greatest possible sum, which is less than the overalllength..-

In the textile industry and particularly in cutting material for drapes, there is a finite number or set of lengths which are used in the manufacture of drapes. In addition, there is normally a plurality of styles of each style including only selected ones of these lengths.

In the cutting of the lengths from a-continuous length of material, an operator is usually assigned to a particular style and a quota of the lengths which can be used in the style. The operator is stationed at a cutting table with a roll of material located at one end thereof. The operator pulls the material across the cutting slot of the table a distance equal to the particular length he is cutting and then operates the cutting mechanism. Should a defect in the material be detected behindthe cutting slot, i.e., between the cutting slot and the supply roll, a distance less than the particular length which he is cutting, he will normally pull the material past the slot and cut out the defect. The leftover material, i.e., the material between the defect and the end, will then be discarded or sold as a remnant, i.e., an odd length of material, at a substantially lower price than first quality or standard length.

The length of the remnant in the above example could have been reduced or entirely eliminated if, upon detection of a defect behind the slot, instead of making the first quality cut, the operator had determined the overall length, i.e., the length of the material from the end to the cutting slot.(cut length) plus the distance from the slot to the defect, and then figured out the optimum combination of the cut lengths, usable in the particular style which he was assigned, which would fit in the overall length. The operator could then make these cuts, remove the defect and continue the cut lengths :which were previously being made. It can be shown that this procedure would reduce the remnant size and often eliminate the remnant entirely and that as the overall length increases, the chances of elimination of the remnant increase since there are a larger number of possible combinations of the possible cut length.

This procedure, however, would be extremely time consuming and the saving due to reduced remnants would probably be offset by the time required for such a determination which would decrease output.

The present invention provides apparatus for rapidly and automatically determining this optimum combination of cut lengths.

In accordance with the present invention a computing apparatus is provided having suitable input means, such as keyboard. The keyboard is arranged such that the operator may input to the computing apparatus the cut length being made, the defect length and the style which he has been assigned. The computer then automatically determines the overall length and the optimum combination of the cut lengths possible for the particular style. The keyboard is also provided for the particular style. The keyboard is also provided with input keys for omitting from the possible cut lengths, selected ones thereof on the basis of sales-inventory statistics.

The present invention may be better understood by referring to the following detailed description along with the attached drawings in which:

FIG. 1 is a block diagram illustrating the relationship of the various components of the present invention;

FIG. 2 is a diagrammatic illustration of the keyboard input;

FIGS. 3a, 3b, c and 3d comprise a schematic wiring diagram of the defect length register;

FIGS. 4a and 4b illustrate the scanning circuit and the preferred combination selection circuit;

FIGS. 5a, b, c and 5d comprise the schematic wiring diagram of the cut length combination logic circuitry and the readout apparatus;

FIG. 6 is a schematic diagram of the preferred embodiment of the signal path circuit; and

FIG. 7 is a schematic illustration of a suitable drive control apparatus for the scanning element.

Referring now to FIG. 1, there is shown a block diagram illustrating the relationship between the fundamental components of the computing apparatus as taught by the present invention. The keyboard 10 constitutes the input to the computing apparatus and is shown in greater detail in FIG. 2. The keyboard is provided with a plurality of groups of keys for enabling the operator to input to the computing apparatus the cut length being made, the style which the operator has been assigned, the defect length noted and omit any lengths which are not desired.

The defect length register 12, which is shown in greater detail in FIG. 3, is responsive to the defect length keys on the keyboard 10 to condition the terminals 13 in accordance with the particular defect length key or keys depressed. A cut length logic circuit 14, which is shown in greater detail in FIG. 5, is also coupled to the keyboard and specifically to the style and omit length keys. The terminals of the logic circuit 14 correspond to the possible incremental values of overall length. The logic circuit 14 is designed to associate with respective ones of the terminals 15, the particular combination or combinations of available cut lengths which is the optimum combination of cut lengths for the overall length corresponding to each terminal. The style and omit keys function to prevent the output from the logic circuit 14 of combinations containing cut lengths not included in the particular style or lengths corresponding to actuated omit keys.

The scanning circuit 17. is provided to scan the terminals 13 of the defect length register, in order, from the terminal corresponding to the greatest defect length to the smallest. The scanning circuit also scans the terminals 15 in synchronism with the scanning of the terminals 13, starting with the terminalcorresponding to the overall length defined by the maximum possible defect length, plus the particular cut length being made. The scanning circuit is coupled to the keyboard and particularly to the cut length keys, whereby the depression of a particular cut length key is effective to condition the scanning circuit to begin the .scan of the terminals R5 at the terminal corresponding to the maximum defect length plus the cut length input. In this manner the apparatus effects the addition of the defect length and cut length as will be more clearly understood hereinafter. The signal path circuit shown in greater detail in FIG. 6 is responsive to the scanning of the terminal 13 corresponding to the particular defect length key depressed to generate a signal which is coupled through the scanning circuit to the terminals 15 of logic circuit 14. If the particular one of terminals 15 being scanned at that moment has a valid combination of cut lengths associated with it, i.e., none of the elements of the combination are precluded by the particular style input or omit inputs, the signal from the signal path circuit will be coupled through the logic circuitry 14 to the output circuitry 18 to indicate the optimum combination of cut lengths for that particular overall length. The readout is also coupled to the signal path circuit to inhibit the passage of signals to the logic circuit 14, once a valid combination of cut lengths has been indicated. Thus it can be seen that the apparatus as shown in FIG. 1 functions to scan available combinations of cut lengths from the highest value to the lowest and to generate an output signal indicative of the optimum combination of cut lengths for the particular combination of defect length and cut length inputs to the device by way of keyboard 10.

Should any of the elements of the most optimum combination be inhibited, due to the selection of a style, or a particular length be omitted, the scanning circuitry will continue to scan until a terminal 15, which has associated therewith only valid cut lengths, is scanned, at which time an output will be indicated, and the signal path circuit will be disabled to pass further signals to the logic circuitry, thus enabling the scanner to continue until it returns to its starting position without indicating additional output combinations.

In order to more easily describe the present invention in detail as it is applied to the textile industry, the following specific values of possible cut lengths and defect lengths and particular style makeups will be used. The present invention is, of course, not intended to be limited to this specific example.

Styles (omitted lengths) Detect length Cut length The keyboard input is diagrammatically illustrated in FIG. 2. The first column of keys S, to S are the style keys which are employed to input to the computer the particular style being run, which in turn excludes certain cut lengths which are not included in the particular styles represented by the pushbuttons S, to 5,, (see the above table). The second column of keys C, to C are the cut length input keys and in accordance with the particular example correspond to the cut lengths as shown within the circles representing the keys in FIG. 2. These cut lengths are in inches. A corresponding group of keys 0, to are the omit keys and correspond to the various cut lengths available. The depression of any one or more of these keys is effective to inhibit the selection of a combination of cut lengths which may include any out lengths corresponding to the depressed omit keys.

The remaining three columns of keys correspond to the defect length input section of the keyboard. These keys are arranged in a column, nine -row adding machine type configuration whereby the three columns correspond to the units, tens and hundreds place in the conventional decimal system. The various input keys just described are preferably the wellknown self-latching type of keys.

The reset button 20 is provided to reset the defect keys and the ready light 21 is provided to indicate that the computing apparatus is ready to accept input information. The read bar activates the computing cycle of the apparatus and also functions to erase any answers in the readout apparatus 18 so that a new answer may be displayed. Once the computing cycle is started by the depression of the read bar, the ready light is cut off, indicating that the computing cycle is in progress. Once the optimum combination is indicated by the readout device, the ready light comes back on again indicating that the computer is ready to begin another computation. The successful readout of an optimum combination also functions to reset the defect length keys.

DEFECT LENGTH REGISTER A preferred embodiment of the defect length register is shown in F IGS. 3a, b, c and 3d, however it is to be understood that other equivalent apparatus may be employed. The defect length register comprises a signal bus 40 which is adapted to connect the signal appearing on any one of the contacts 13, here labeled C, to C to the signal path circuit 16 (FIG. 1 and F IG. 3). Each of the contacts C, to C correspond to incremental defect lengths of l to 120 inches, respectively. Each of these contacts are connected to the signal bus by diodes D, to D respectively. The contacts C, to C represent defect lengths of 1, 2, 5...9 inches, respectively and besides being connected to the signal bus, are also connected to terminals T, to T respectively. Between each of these terminals is con- I nected a switch SW, to SW respectively, which are normally closed switches adapted to be opened in response to the depression of corresponding pushbuttons on the keyboard, i.e., the key in the units column of the defect length keys. The keys in the units column are preferably mechanically coupled to the switches SW, to SW in a well-known manner, however, other methods of coupling are contemplated. Terminal T is further connected through normally closed switch SW to a reference potential such as ground as illustrated at 41. Connected to each of the leads interconnecting terminals C, to C to terminals T, to T are a corresponding plurality of unit defect length buses B, to 8,.

Each of the terminals C C C C and C are connected via corresponding diodes D, D D D,,,, and D to the signal bus 40. Terminal C is also connected via lead 42 to the collector of transistor 0,. The base of transistor 0, is connected through normally closed switch SW and lead 45 to junction 47 between resistors R, and R which are connected in series between a source of potential, for example +10 volts, and ground. In this manner the transistor Q, is biased to conduct when switch 10 is closed. The emitter of transistor Q, is connected via lead 51 through the collection emitter path of transistor 0, and through a plurality of series connected switches SW SW SW, SW SW SW and SW to ground. The base of transistor 0, is similarly connected through a normally closed switch SW to the junction point 47 of resistors R, and R such that when the switch SW is closed, the transistor Q 2 is biased to conduct to thereby ground terminal C Although transistor switching elements are herein disclosed, it is to be understood that any other suitable controllable switching element can be used such as relays, silicon controlled switches, SCRs and the like. The switches SW SW SW are coupled to the keys I to 9, respectively, of the tens column on the keyboard in the same manner as switches SW, to SW The switch SW is coupled to the 01 key in the hundreds column.

The terminals C,, to C which correspond to the defect lengths of 1 l to l9 inches, respectively, are connected via corresponding diodes D,, to D,,, to the terminal C', In addition, terminals C,, to C,,, are connected via diodes D,,' to D,,, to the unit defect length buses B, to B The remaining terminals C to C C to C C,,, to C,,,, are similarly connected to their corresponding tens-unit terminal and to the unit buses.

The terminal C as previously indicated, is connected via diode D to the signal bus 40 and is also connected via lead 53 and normally closed switch SW to ground. The terminal C is connected to the signal bus via diode D and is connected to ground via lead 55 and the emitter collector circuit of transistor Q The terminal (3, is likewise connected to the signal bus via diode D and to ground through the emitter collector circuit of transistor Q The bases of transistor 0;,

and Q, are connected through resistors R and R respectively, to a source of electrical potential, for example lt% volts. The base of transistor O is also connected via lead 57 to the base of transistor Q, and through normally closed switch SW, to the junction 417 between resistors R, and R Similarly, the base of transistor Q., is connected via lead 59 to the base of transistor Q and through switch SW to the junction 47. By selecting proper values for the resistors R, to R the positive votage appearing at junction 47 will bias transistors Q and Q., in the conductive state, thereby maintaining their corresponding terminals C,, and C at ground potential. From the foregoing description, it can be seen that as the terminals C, to C are scanned, by a wiper contact for example, having a voltage applied thereto, no voltage will'appear on the signal bus 46 absent the depression of one or more of the defect length keys. This can be seen by observing the fact that all of the contacts C, to C,, are connected through the various switching arrangements and transistors to ground potential when the switches SW, to SW are closed, i.e., when none of the defect length keys on the keyboard input are depressed. However, should one of the keys be depressed, for example key 05 in the units column, the switch SW would be opened. The opening of switch SW disconnects the junctions T, to T, from the ground terminal 41 whereby as the wiper contact reaches terminal C,,, the voltage thereon, instead of being grounded as it would be at the terminal C to C will pass through diode D to the signal path circuit via signal bus 40.

If the input defect length is 2l inches, i.e., key 02in the tens column and the key 01 in the units column are depressed, the normally closed switches SW and SW, will be opened. The opening of.switch SW in the base circuit of transistor Q causes this transistor to cut off thereby isolating terminal C,,, from ground which enables a signal to pass from C through its corresponding diode D and the signal bus 40 to the signal path circuit. By additionally opening switch SW,, the units defect length bus B, is isolated from ground whereby the contact C,,, is no longer connected to ground through the diode D The remaining unit bus lines B to B however, remain connected to ground through corresponding switches SW to SW, and therefore any signals appearing on contacts C to C,,, will be shunted to ground and prevented from reaching the signal bus 46. Similarly, the normally closed switches SW to SW prevent any signals appearing at contacts C to C from reaching the signal bus. Thus it can be seen that as. the terminals C to C, are scanned, an output will not be generated on the signal bus 40 until the contact scans the terminal C corresponding to the selected defect length. The remaining contacts C to C,,, and their associated switches function in the same manner ad and therefore will not be described in detail.

if the particular defect length encountered is for example, 1 l 3 inches, the operator would depress key 01 in the hundreds column, key ill in the tens column and key 03 in the units column. The depression of these keys opens the normally closed switches SW SW, and SW respectively. The opening of normally closed switch SW in the base of transistor Q, removes the positive bias voltage from the base of transistor 0,, which is then biased to cut off due to the -48 volts potential connected to the base of this transistor through resistor R The opening of the normally closed switch SW prevents the The diodes D and D are required in situations wherein the defect length is in the range of 10+ and inches, respectively. This can be seen by considering the example previously given, wherein a cut length of 21 inches was selectedlt is recalled that for a cut length of 21 inches, the switch SW is opened which not only cuts off transistor Q, but also removes the positive bias from the base of transistor 0,, which under normal circumstances, would cause the terminal C,, to become isolated from ground and thus permit an output signal when the wiper contact of the scanner is on this contact. Due to the presence of diode D however, the terminal C remains grounded through the normally closed switch SW Diode D functions in the same manner for defect lengths of 10 to 19 inches.

Thus, the defect length logic circuitry may be described as containing a plurality of branches, i.e., the various diode combinations and switches associated with each of the various terminals C, to C which, depending on the particular defect length punched in on the keyboard, will'be effective to ground all of the terminals corresponding to defect lengths greater than the input defect length. More specifically, the circuit may be described as a plurality of decade circuits connected between the terminals C, to C and the signal bus 40, when shorting of the terminal C,, to ground through the diode D,,,,. The opening of normally closed switch SW isolates the unit buses B, to B, from ground and consequently, the terminals 13 which are connected thereto. Thus, it can be seen that terminals C,, to C,, are grounded due to the fact that transistor is conductive and that buses B, to B are grounded through the corresponding switches SW, to SW,,.

The terminal C,, is isolated from ground due to the fact that bus 3, is disconnected from ground and that terminal C,,. is also disconnected from ground, thus, as the scanning element scans terminal M3 the signal passes through the diode B and through the diode D to the signal bus lead 40 to the signal path circuit, indicating that a defect length of 113 inches has been selected.

the decimal base 10 number system is being used.

SCANNER CIRCUIT AND PREFERRED COMBINATION SELECTION LOGIC ClRCUlTRY In FIGS. 4a and 4b there is shown in greater detail the scanning circuit l7 (FIG. 1) and also the logic circuitry 14, which is effective to select only one of two or more possible combinations which may be associated with one or more of the input terminals 15. As shown here, there are 183 terminals 15 (227"44") which correspond to the possible incremental overall lengths when the maximum defect length is 120 inches, the maximum cut length is 107 inches and the minimum cut length is 44 inches. The lastterminal on the right in FIG. 4b corresponds to 45 inches overall length and the last terminal on the left in FIG. 4a corresponds to a 227 inch overall length.

The scanner circuit 17 includes a scanning element 102 which is illustrated as a rectangular planar member which is caused to move in rectilinear fashion from left to right in the FIG. under the control of AC motor 104(FlG. 7). The dotted line 103 illustrates a suitable mechanical coupling between the motor and the traveling slider. The slider is schematically depicted here (for ease of description) as being a planar element having rectilinear motion, however, in actual practice, a circular planar element is employed having the various required wiper contacts mounted radially thereon and which is adapted to rotate over and scan the particular terminals of the defect length register and the cut length logic circuitry, which would, of course, be disposed in circular fashion. It is to be further understood, however, that any suitable scanning arrangement can be used and in particular, the use of electronic counter means such as shift registers and the like is also contemplated to effect the scanning function of the present invention.

With specific reference now to FIGS. 4a and 4b, the scanning element W2 is provided with a first wiper contact 105 for wiping or scanning the input contact C to C,, of the defect length register from the contact representing the defect length of the 120 inches to the contact representing a defect length of 1 inch, i.e., from the highest defect length possible to the lowest.

The wiper'contact 1'05 is connected with a source of electrical potential (not'shown), for example +30 volts via lead 107. The voltage on the wiper contact 105 is coupled through the defect length register 12 to the signal bus as explained hereinbefore with regard to HS. 3 and causes the signal path circuit to generate a voltage on lead 109 in a manner to be explained in detail hereinafter with regard to H6. 6.

The signal on lead 1% is connected through the parallel connected, normally open switches, CL, to GL to wiper contacts ill? to H8. The switches CL, to Cl.,, are mechanically coupled to cut length keys C, to C,,, respectively, whereby the depression of one of the cut length keys functions to close the corresponding one of the switchesCL, to Cl..,,. In this manner the wiper contacts 110 to 118 correspond respectively to the cut lengths 44, 53, 62, 71, 80, 92, 98, l03and 107 inches. The contacts are spacially disposed with respect to the contacts C to C and the wiper contacts 110 to 118 are located on the slider in such a manner that each of the wiper contacts 110 to 118 is displaced, in terms of contacts 15, an amount equal to its associated cut length from the wiper 105. As shown in FIG. 4, for example, the contact 105 is on defect length terminal C and wiper contact 110 (which corresponds to the 44-inch cut length) is on the contact 15 which corresponds to an overall length of 120 inches +44 inches or 164 inches. Thus the defect length and the cut length inputs on the keyboard are, in effect automatically added.

In this manner, it can be seen that as the scanning element moves to the right, the selected cut length wiper contact will apply a signal to one of the contacts 15 when the wiper 105 scans the contact C to C which corresponds to the defect length punched in by the operator. Due to the physical relation of the various contacts, as described hereinbefore, the contact 15 which will first receivethe signal from the signal path circuit will correspond to an overall length equal to the defect length input plus the cut length input.

The drive for the slider, as shown in FIG. 7, comprises the AC motor 104 which is driven from a source of electrical energy such as 115 volts AC connected to terminals 122 and 124. These terminals are connected through the driving winding 126 of the AC motor with the normally open relay contacts RlL, connected in series between the terminal 124 and the winding 126. The relay coil 128 is connected to a source of electrical potential such as 12 volts through a normally opened switch 130. which is adapted to be closed by the depression of the read bar on the input keyboard shown in FIG. 2. Connected across the switch 130 is a pair of normallyopen holding contacts RL which are adapted to be closed in response to the energization of the relay coil 128 to cause the relay to remain energized after the switch 130 is opened. The closure of the switch 130 is effective to energize the relay coil 128 and, as just indicated, to close the contacts RI. to maintain the relay energized. Energization of relay coil 128 also closes the contacts RL, to thus energize the motor 104. The motor 104 drives the scanning element from its home position as shown in FIG. 4a, past the various terminals of the cut length logic circuitry and the defect length register, until the scanning element returns to its home position, at which time a mechanical connection between the drive shaft of the motor 104 (indicated by dotted line 101) will cause the contacts R15 to open, thereby deenergizing the relay coil 128 which in turn causes the contacts RL, to open to cut off the motor 104. Thus completing a full cycle and rendering the scanning apparatus ready for its next computation. The depression of the read bar (FIG. 2) is also effective to open the erase switch 304 by suitable mechanical coupling as illustrated by dotted line 105, which resets the read out circuit, as will be explained in greater detail hereinafter with reference to FIG. 50.

It can be seen by referring to FIG. 4 that some of the overall length input terminals 15 are connected in common. This is done due to the fact that for certain overall lengths there is only one optimum combination of cut lengths. As an example, for the overall lengths of 225 to 227 inches the maximum combination of cut lengths, less than 227 inches, is 92 71 62 or 225 inches. Thus, only this one combination is optimum for the overall lengths 225 to 227 inches and therefore the terminals 15, which correspond thereto, are coupled together. There are, of course, other groups of overall lengths which similarly have only one optimum combination.

Due to the finite number of cut lengths, there isa finite number of different combinations which is less than the possible overall incremental lengths. In the present example, 77 different combinations are used. Although there are more than 77 possible combinations in the present example, the use of only 77 has been found to be sufficient.

In accordance with the present example therefore, there are 77 input terminals L to L, to the cut length combination logic circuitry 14. Each of the input terminals 15. are connected to the particular one of the terminals L to L, which correspond to its optimum combination. For example, the terminals corresponding to overall lengths of 225 inches to 227 inches are all directly connected to the terminal L through harness 141. The terminal L,, as will be explained hereinafter, corresponds to the combination 92, 71, 62 inches.

For certain overall lengths there are two or more different optimum combinations of cut lengths which have equal sums. The overall lengths 222 inches and 223 inches, for example, have two optimum combinations, i.e., 92, 62, 62 inches and 80, 71, 71 inches, both of which equal 222 inches. There is no combination available which equals 223 inches. The terminal L corresponds to the combination 92, 62, 62 inches and the terminal L corresponds to the combination 80, 71 71 inches There are, of course, numerous other overall lengths which have two or more equal combinations.

The preferred combination selection logic circuitry 14 is provided to select only one of these possible equal combinations. Before describing the selection circuitry 14", it should further be pointed out that in the above example there are only three styles in which both combinations are possible. More specifically, only styles S and S and S, which are the same as S and styles S, and S are the only styles which do not exclude one or more of the cut lengths 92, 62, 62 or 80, 71, 71. Style 5,, for example, excludes cut lengths of 62 inches (see Table I) and thereforethe only possible combination for overall lengths of 222 inches and 223 inches, given style 8,, is 80, 71, 71 inches. The selection circuit 14 functions to allow the selection of a predetermined one of these combinations given a style S or S,,S-, and the selection of one or the other combination depending on which of the styles 8,, S or S, is is selected. For style 5,, the only valid combination is 92, 62, 62.

The preferred combination selection circuit comprises a plurality of transistor gate circuits, one for each overall length or lengths which have two or more equal optimum combinations. Since all of these gates are similar in structure and function, only the gate G, associated with the overall length terminals corresponding to 222 inches and 223 inches, will be described. The transistor gate comprises a pair of transistors Q and Q1 the bases of which are connected in common through current limiting resistors R andR respectively, to the terminals 15 corresponding to theoverall lengths of 222 and 223 inches. The collector of transistor Q is connected via lead 151 through an isolating resistor R to a source of potential (not shown) of, for example, +10 volts. The collector of transistor O is similarly connected to a source of potential through lead 153 and resistor R The emitters of transistors Q and 0,, are connected via leads 155 and 156 to terminals L and L respectively. The emitter of transistor Q is also connected through diodes 160, 162, and 164 to style buses 813,, SB, and SB, which correspond to the styles in which the combinations 80, 71, 7 land 92, 62, 62 are both possible. Each of the style buses SB, to SB, are connected to ground through their respective leads 171 to 176 and normally open, style select switches ST, to ST,,. These switches are coupled to their respective style keys S, to S, on the keyboard such that the depression of a style key will close its corresponding style select switch. The style select switches are are shown in greater detail in FIG. 5 which illustrates the cut length combination logic circuitry. The style buses extend through the logic circuitry 14" whereby other transistor gates may be similarly connected thereto. Only six style buses are needed since style select switches ST and ST, are connected in common to switch 5T Should a voltage appear on either of the terminals 15 corresponding to 222 or 223 inches, the transistors Q15 and 0 would be biased into conduction through base resistors R, and R Thus current would flow through the collector-emitter path of these transistors to terminals L and L to apparently cause two outputs. Should any of the style select switches S,,, S, or S-, be closed, however, the signal on the emitter of transistor would be grounded, thus preventing an output of the combination 92, 62, 62. The signal on the led lead 155 from transistor 0-,, remains, however, and an output of the combination 80, 71, 71 is obtained. The selection of either combination is predetermined by various considerations and can be easily changed by switching the terminals to which the leads 15S and 1% are connected or by connecting the diodes rm, 162 and 164 to the lead 156 instead.

f neither of the style select switches ST or ST,,ST are closed but instead switch ST, is closed, both transistors will conduct but the cut length combination logic circuitry will ground terminal 74, as will be explained hereinafter, and permit only the output of the combination 92, 62, 62.

The other gate circuits operate in a similar manner. It is pointed out however, that should three combinations be equal for a given overall length, three transistors wouldbe required as shown for gate G2. TransistorsQ Q and Q are connected to the voltage supply (not shown) flirough resistors R,, R and R the third resistor R being required for the third transistor. The bases of these transistors are connected in common through resistors R,,,, R,, and R, to input terminals 15 corresponding to the overall length of 186 inches. The emitters of transistors Q41 to 049 are connected to terminals L to L respectively. The terminal L corresponds to the combination l4, 7T, 71; L corresponds to 71, 72, 53 and L to 80, 53, 53. In this example, the combination corresponding to terminal L is preferred to that corresponding to terminal L,,,, which in turn, is preferred to the combination corresponding to terminal L,,, It can be shown that all three combinations are possible only for style S and that the combinations corresponding to terminals L and L,,, are both possible only for styles 8, and 8,. Since terminal L is preferred, the emitter of transistor 0, is connected through diodes to the buses SB, and 8B,. The combinations corresponding to terminals L and L are both valid only for styles S, and S, so the emitter of transistor Q is connected through diodes to buses SB, and 8B,. In addition, however, the combinations corresponding to terminals L and L can both be valid for styles S and S and therefore, since terminal L,,, is preferred over L,,,,, the emitter of transistor (2,,, must also be coupled to bus 8B,. The gate G functions in the same manner as gate G, except that it selects only one of three possible combinationsinstead of two.

Although transistor gates are shown herein, other and different types of controlled switches may be used. The resistors here shown, i.e., resistors R, to R function to prevent the grounding of one of the emitters of a gate from effecting the current flow through the other transistor;

CUT LENGTH COMBINATION LOGIC CIRCUIT The cut length combination of logic circuitry 14' is shown in greater detail in FIGS. a-d. This logic circuitry is effective to connect signals appearing at any one of the input terminals L, to L with predetermined output indicators I to I (FIG. 50) in accordance with the particular optimum combination of cut lengths associated with each of these input terminals.

The logic circuitry 14' comprises a plurality of cut length buses 290 which are each labeled with the particular cut length to which they correspond. As can be seen, the first five buses, starting from the top, correspond to cut lengths of 44 inches. The next four buses correspond to cut lengths of 53 inches. The next three correspond to 62 inches and so forth, down to the last bus, which corresponds to the cut length of I07 inches. The number of buses corresponding to each cut length is determined by the maximum overall length possible.

Each of the cut length buses are coupled at one end by leads 201 to 224 to the gate terminals of silicon controlled rectifiers SCR, to SCR Each of the terminals L, to L as previously indicated correspond to 77 different cut length combinations employed in this particular example. Each of these terminals are connected through diodes to the particular cut length buses corresponding to the cut lengths which make up the combination to responding to a 44 inch cut length. The terminal L, corresponds to a combination of only one 44 inch cut length since it is coupled to the overall length terminals 15 which represent an overall length of 45 to 52 inches. Terminal L, is therefore only connected to the uppermost bus corresponding to the cut length of 44 inches. The remaining connections for the other terminals L to L are not shown here since they will be readily apparent to those skilled in the art.

The logic circuitry thus far described is effective to couple a voltage appearing on any one of the input terminals L, to L,, to the cut length buses corresponding to the cut lengths of the combination which that one terminal represents to thereby energize the appropriate indicators I, to 1,, in the readout apparatusto indicate the optimum combination of cut lengths.

The style select switches ST, t0 ST, (FIG. 5a) are also coupled to the cut length buses to prevent the output of combinations containing cut lengths which are not usable in the particular style which may be selected. Each of the normally open style select switches ST, to ST; are connected between ground and through diodes, poled to conduct as shown, to the uppermost out length buses representing-each cut length which is omitted from the particular style to which each switch corresponds (see Table I). For example, the switch ST, corresponds to style S, which cannot use cut length of 103 inches and 62 inches. This switch is therefore coupled to the cut length bus corresponding to 163 inches through diode 270 and to the uppermost bus corresponding to 62 inches through diode 271. In this manner, should style key S, be depressed, switch ST, would close to thereby ground, through diodes 270 and 271, all of the terminals L, to L which are connected to one or more of the 62-inch cut length buses or the l07-inch cut length bus, or in other words, all terminals L, to L,, which correspond to combinations containing 62-inch or lll3-inch cut lengths. Should a signal appear on any one of these ter minals, no output would be indicated since the signal would be shunted to ground and therefore could not gate any of the SCRs in the readout apparatus.

The normally open omit switches OS, to OS, are similarly coupled between ground and respective ones of the cut length buses. These omit switches are coupled to omit keys 0, to 0 respectively, and are adapted to be closed in response to the depression of these keys. No diodes are required in these connections, however, since no two switches are connected to the same cut length bus. More specifically, each of the switches OS, to OS are directly connected to respective ones of the uppermost buses corresponding to the cut lengths 44, 53, 62, 71,

80, 92, 98, 103 and 107 inches, respectively. In this manner the depression of the omit keys is effective to inhibit or prevent the output of combinations containing one or more out lengths corresponding to the depressed omit keys.

READOUT APPARATUS The readout apparatus is shown in FIGS. 50 and comprises silicon controlled rectifiers SCR, to SCR,, and a corresponding plurality of indicators I, to I,,, which are preferably conventional light bulbs. The corresponding SCRs and indicator lights are connected in series between lead 301 and ground. The lead 34)]. is connected through normally closed relay contacts 303 and normally closed contacts 304 to a source of electrical potential (not shown) such as +10 volts. The indicator lights correspond to various possible cut lengths, i.e., the cut length buses, and preferably are provided with transparent covers (not shown) having imprinted thereon the particular cut lengths to which the various indicator lights correspond, to provide an easily readable output.

As previously indicated, the gate terminals of each SCR are connected via corresponding leads 201 to 224 to the various cut length buses 200 whereby a voltage present on any one of the cut length buses will trigger the corresponding SCR into conduction, assuming that the contacts 304 and the contacts 303 are closed, to thereby illuminate the indicator lights connected in series with the conducting SCRs.

The normally open contacts 305 are connected between a suitable source of potential (not shown) and ground through relay coil 307. The contacts 305 are mechanically coupled to the reset key on the input keyboard whereby the depression of the reset key will energize the relay coil 307 to open normally closed relay contacts 303 to break the circuit to the SCRs to thus clear" the output. When the relay is deenergized, the SCRs will remain cutoff assuming that no gate potential is applied to any SCR, The switch contacts 304 are mechanically coupled by means (not shown) to the read bar on the keyboard whereby, when the read bar is depressed, the contacts 304 will open to reset the output indicators.

SIGNAL PATH CIRCUIT The junction points between each SCR and indicator lamp is connected to bus 310 through properly poled diodes whereby the display of any output combination will result in a voltage, i.e., the voltage across the indicator lights, appearing on bus 310, which functions to disable the signal path circuit on the occurence of a valid output such that additional output combinations cannot be displayed.

A preferred embodiment of the signal path circuit is shown in greater detail in FIG. 6.

The signal path circuit 16 has a turnon" input terminal 350 which is connected to the signal bus 40 from the defect length register and an output terminal 352 which is connected to lead 109 which is in turn connected to wiper contacts 110- 118, through the cut length switches CL to Cle See FIG. 4a. The signal path circuit is also provided with a turnoff input terminal 354, which is connected to bus 310 from the readout apparatus shown in FIG. 50.

The signal path circuit comprises a bistable flip-flop 360 which includes a pair of transistors Q and Q,, The collectoremitter path of transistor Q is connected between terminal 361 and ground through a load resistor 363. The terminal 361 is adapted to, be connected to a source of positive potential (not shown). The collector-emitter path of transistor Q11 is similarly connected to between terminal 361 and ground through load resistor 365. The base of each of the transistors Q and Q are conventionally cross-coupled to the collector of the other transistor by parallel RC circuits 367 and 369, respectively. The flip-flop 360 is so designed that when the apparatus is turned on, the transistor Q will be conducting and the transistor Q will be cutoff.

The base of transistor Q is also connected to the tumon input terminal 350 through diode 371 and the parallel connected resistor 373 and capacitor 375. The base of transistor Q is also connected to the turnoff input terminal 354 through diode 376, resistor 378 and capacitor 380.

The turnoff input terminal 354 is additionally connected through lead 392 and resistor 383 to the gate terminal 384 of SCR 386 and through capacitor 387*to the base of transistor Q12.

The anode-cathode circuit of the SCR 386 is connected across the input to the signal path circuit, i.e., between input terminal 350 and ground, such that conduction in the SCR will short the input to the signal path circuit.

The collector-emitter path of transistor 012 is connected between terminal 389 and ground through the energizing winding 390 of a solenoid (not shown). The solenoid is effective, upon energization, to cause any depressed defect length keys to popup or reset. A pair of normally open contacts 392 is connected across the emitter-collector path of transistor 0 which contacts are mechanically coupled to the reset key on the keyboard to thereby permit manual reset of the defect length keys.

The output from the flip-flop 360 taken at terminal 395 between the resistor and the collector of transistor Q11. Terminal 395 is connected by lead 396 and resistor 397 to the base of output transistor Q and through resistor 398 to a suitable source of bias potential. The collector of transistor 0 is connected to terminal 361 through lead 400 and the emitter thereof is connected to the output terminal 352 through resistor 401. The base of transistor OH is grounded through transistor Q when it is is conducting and therefore transistor Q is cut off and prevents'an output on terminal 352. When transistor Q is cut off, the transistor Q is biased into conduction thus placing the positive potential at terminal 361 on the output terminal. I

The signal path circuit functions in the following manner. Assuming that the'flip-flop 360 is in its turnon state, i.e, Q 1 conducting Q cut off, no output appears on output terminal 352. When a signal appears on bus 40,'indicating that the desired defect length terminal has been reached by the scanner, the signal will pass through resistor 375, capacitor 373 and diode 371 to the base transistor Qw, thus turning on this transistor. When transistor Q turns on, the transistor O is forced to cut off, thus biasing transistor Q into conduction whereby a positive potential is coupled to the lead 109 and to the wiper contact 110-118 corresponding to the closed out length switch. The flip-flop 360 will remain in this condition even after the removal of the signal on input terminal 350 and thus the voltage will be constantly applied to the wiper contact. When a valid combination is read out, a signal will appear on bus 310 which will pass through turnoff input terminal 354, resistor 3'78, capacitor 380 and diode 376 to thus tumon transistor Q which in turn forces 0 0 to cut off. This action biases transistor 0 to cut off to thereby remove the potential from the wiper contact.

The signal at input terminal 354 also passes through resistor 383 to gate 384 to gate SCR 386 into conduction, thus grounding tumon input terminal 350, to prevent further pulses on bus 40 from switching flip-flop 360. This action allows the scanning element to return to its starting position without causing additional means meaningless output indications since a positive gate signal remains until the output indicators are extinguished by pressing the read bar for another computation or by pressing the reset key.

The signal on lead 382 also momentarily biases 012 into conduction to energize the solenoid coil 390 to reset the defect length keys.

OPERATION Although the operation of the present invention should be clearly understood from the foregoing detailed description, the following specific exemplary operations will be described to enable a complete understanding of the present invention.

Assume that an a operator is making cuts of 107 inches, has been assigned style 8., and no lengths are to be omitted for sales-inventory reasons. Under these circumstances, the operator will depress the cut length key C, which corresponds to a 107-inch cut length and will also depress style key S These keys will remain depressed and cause style select switch ST, to close; Assume further than that prior to making a 107- inch cut, the operator detects a defect ll9 inches in back of the cutting slot. Now, instead of making the 107-inch cut, the operator would enter the defect length into the apparatus by depressing defect key 01 in the hundreds column, key 01 in the tens column and key 09 in the unit column. (This procedure is followed rather than making the 107-inch cut, which would leave only 119 inches of overall length, since 226 inches of overall length enable potentially more efficient combinations).

The operator then depresses the read bar which closes switch to energize relay coil 128 to close contacts RL to energize the motor and RL to hold in the relay after the read bar is released. This initiates the drive of the scanning element 102 from its starting position as shown in FIG. 4. Actually, the

scanning elements starting position will be offset such that wiper contact 105 will not be contacting terminal C The defeet length register will isolate contact C from ground by cutting off transistor and opening switches SW and SW Thus, when the scanner reaches contact C the voltage on wiper contact 105 will be connected to signal bus 40 and thus to turn on input terminal 350 of the signal path circuit. This voltage will set the flip-flop 360 to bias transistor Q into conduction to thus continuously apply the positive voltage at terminal 361 to the wiper contact 118 through closed switch C1 This action takes place instantaneously so that the voltage on wiper contact 118 is applied to the overall length terminal corresponding to 226 inches. This is true due to the fact that the wiper contact 105 is on contact C and that wiper contact 118 is displaced, in terms of overall length, from the wiper contact 105 an amount equal to 107 inches, i.e., 1-19 107 I226.

The voltage on the overall length input terminal is directly connected to terminal L-,-, through an appropriate wire in harness 1411. From terminal L the voltage is connected to the cut length buses 200 corresponding to cut lengths of 92, 71 and 62 inches. Since style select switch ST, does not ground any of the buses corresponding to these cut lengths, the voltage on terminal L is coupled through leads 210, 213, and 219 to gate terminals of SCRs 10, 13 and 19, respectively, to thereby gate them into conduction to energize the indicator lights 1, 1, and 1, to indicate to the operator the optimum combinations for the overall length available. These indicators may be light bulbs fitted with transparent caps, having numbers printed thereon, corresponding to the particular cut lengths.

The voltage now appearing across the indicators I I and i is coupled through bus 310 to the cutoff terminal 354 of the signal path circuit. This voltage will reset the flip-flop 360 to thereby cut off transistor O and remove the voltage from the wiper contact 118. This prevents another output when the wiper contact reaches another overall length terminal having a valid combination associated therewith. The voltage at input 354 also gates SCR 386 to ground the input terminal 350 as long as the output indication remains. This prevents further signals on bus 40 from setting the flip-flop again. This enables the scanner to continue its cycle back to the starting point without producing spurious outputs.

The voltage at input terminal 354 also momentarily, i.e., until capacitor 387 charges, turns on transistor Q to energize solenoid coil 390 and reset the defect length keys.

The scanner, when it returns to its starting position, is stopped by the opening of the motor circuit which is caused by the opening of contacts RL which in turn deenergizes the relay and opens contacts RL,. The apparatus is now ready for another computing cycle.

The scan-seek operation, as well as the preferred combination selection function, can be illustrated by considering the above example, with the omit key 0 depressed.

Following the same procedure, i.e., depressing-the defect key to enter a l 19-inch defect length, and depressing the read bar, the previous output is erased by momentarily opening contacts 304 to extinguish SCR l0, l3 and 19 and to thus remove the input to cut off terminal 354. This will open circuit sCR 386 to permit the input of a signal from signal bus 40.

When the wiper contact 105 reaches C the voltage will gain trigger the signal path circuit to apply a voltage to the wiper contact 118. This voltage will again be directly fed to I- but since omit switch 05 is closed, the contact L is grounded through diode 260, the cut length bus corresponding to 92 inches and switch 08 Thus no output is generated and the voltage on wiper contact 118 remains. At the next overall length terminal, i.e., 125 inches, output is again prevented since this terminal is connected in common to the Elli-inch terminal.

The voltage still remains on lead 109 and wiper 118 as it reaches the next overall length terminal, which corresponds to 224 inches. This terminal is connected directly to terminal L No output occurs however, due to the fact that style select switch ST. grounds this terminal through diode 412, the cut length bus corresponding to 44 inches and diode 414. The scanner then steps to the next terminal, with voltage still present at wiper contact 118. The next terminal corresponds to an overall length of 223 inches. The terminal is connected in common with the terminal corresponding to 222 inches to the base transistors Q15 and Q1 in the preferred combination selection circuit (FIG. 1). The voltage on the wiper contact will therefore turn on both of these transistors but the voltage on the emitter of Q will be grounded through style bus SB and style select switch ST. so that no voltage appears on terminal L The voltage on the emitter 0 however, is connected to terminal L This voltage is then coupled through the proper cut length buses to SCR 13,14 and 16 to produce the output 80, 71 and 71 inches. The signal path circuit will then be reset as before to remove the voltage from the wiper contact 118 and prevent subsequent spurious outputs as the scanner continues its cycle to the start position.

Thus, it can be seen from this last example that the computing apparatus of the present invention is effective to determine the largest valid cut length combination possible for the input parameters including style and omit information, and is also effective to choose between two or more possible optimum combinations for a given set of input parameters.

The present invention, as described hereinbefore with respect to a single preferred embodiment, is thus effective in general to determine the optimum combination of a set of M sublengths which will fit into a an overall length, comprised of a selected one of said M sublengths, and selected one of a set of N incremental lengths, the term optimum" meaning that combination having the largest possible sum of its component sublengths which is less than the overall length.

This invention is further adapted to take into account other information which prevents theme of one or more of the M sublengths and to prevent the selection of any combinations which contain these particular sublengths. The present invention is also capable of selecting the preferred one of two or more possible equal optimum combinations for any given overall length.

It is to be clearly understood therefore that the foregoing detailed description of the present invention, as it is applied to a specific textile industry process, is not intended to limit the scope thereof thereto, but that it (the present invention) is of general applicability to situations wherein it is desired to determine the optimum division of an overall length into one or more given sublengths.

The various elements of the present invention are similarly not limited to the preferred embodiments disclosed and therefore may take other and different equivalent forms which would be readily apparent to those skilled in the art.

I claim: 7 1. Apparatus for determining the optimum combination of a set of M given sublengths for an overall length comprised of a selected one of said M sublengths and a selected one of a set of N incremental lengths, said apparatus comprising:

a plurality of selectable incremental length terminals each corresponding to one of said N incremental lengths;

means for selecting any of said incremental length terminals so that the condition of the selected terminal difiers at least from the conditions of at least the other incremental length terminals associated with greater lengths;

a plurality of overall length terminals corresponding to each of the possible values of overall length;

output means for indicating said optimum combination;

means for connecting each of said overall length terminals to said output means to indicate at least one particular optimum combination for that overall length;

means for scanning said plurality of selectable terminals in order of decreasing length, from the highest possible incremental length;

means for scanning synchronously with said selectable terminal scanning means said overall length terminals in

Claims (17)

1. Apparatus for determining the optimum combination of a set of M given sublengths for an overall length comprised of a selected one of said M sublengths and a selected one of a set of N incremental lengths, said apparatus comprising: a plurality of selectable incremental length terminals each corresponding to one of said N incremental lengths; means for selecting any of said incremental length terminals so that the condition of the selected terminal differs at least from the conditions of at least the other incremental length terminals associated with greater lengths; a plurality of overall length terminals corresponding to each of the possible values of overall length; output means for indicating said optimum combination; means for connecting each of said overall length terminals to said output means to indicate at least one particular optimum combination for that overall length; means for scanning said plurality of selectable terminals in order of decreasing length, from the highest possible incremental length; means for scanning synchronously with said selectable terminal scanning means said overall length terminals in order of decreasing overall length from the terminal corresponding to the overall length equal to the maximum possible iNcremental length plus said selected sublength; means connected to said selectable terminals for generating a signal at said selected terminal when said selectable scanning means scans said selected incremental terminal; and means connected to said selectable scanning means and responsive to said signal for applying a potential to the one of said overall length terminals then being scanned by said synchronously scanning means, said output being responsive to said potential to indicate the optimum combination of said M sublengths for the overall length comprised of said selected incremental length and said selected sublength.

2. The apparatus of claim 1 further comprising output inhibit means connected to said output means and responsive to the output indication of an optimum combination for inhibiting further output indications.

3. The apparatus of claim 1 wherein said means for connecting further comprises means for preventing the output of optimum combinations comprised of one or more undesired ones of said set of M sublengths and wherein said potential is applied to said overall length terminals until an output is obtained.

4. The apparatus of claim 1 including a plurality of selectable circuits, and a plurality of input terminals corresponding to each of said selectable circuits and wherein each of said selectable circuits comprises a conductive connection between an associated input terminal and one of said incremental length terminals and a normally closed switch connecting said conductive connection to ground, each of said circuits being selectable by opening its normally closed switch to isolate said conductive connection from ground, whereby a potential appearing at the input terminal of the selected circuit will be coupled to said incremental length terminal to thereby constitute said signal.

5. The apparatus of claim 1 further including a second plurality of terminals corresponding to a set of C different, predetermined optimum combinations, means for connecting each of said plurality of overall length terminals to the particular one of said second plurality of terminals which corresponds to the optimum combination therefore and means for connecting each of said second plurality of terminals to said output means for indicating the optimum combination to which it corresponds in response to a potential appearing on its associated one of said overall length terminals.

6. The apparatus of claim 5 wherein said means for connecting each of said plurality of overall length terminals to said second plurality of optimum combination terminals comprises a preferred combination selection means for each overall length terminal or group of such terminals for which two or more equal valued optimum combinations are possible, each of said preferred optimum combination selection means being effective to couple its associated overall length terminal, or group of such terminals, to only the one of said optimum combination terminals, which corresponds to the preferred one of said two or more equal valued optimum combinations.

7. The apparatus of claim 5 wherein said output means comprises a plurality of indicators corresponding to the elements of said set of C optimum combinations and wherein said means for connecting said plurality of optimum combination terminals to said output means comprises a plurality of conductive buses corresponding to the elements of said set of C optimum combinations, means connecting said buses to respective ones of said indicators and unidirectional conducting means connecting each of said plurality of optimum combination terminals to the ones of said buses which correspond to the elements of the particular optimum combination to which each of said optimum combination terminals corresponds.

8. The apparatus of claim 7 wherein said output means further comprises a plurality of silicon controlled rectifiers connected in series with respective ones of said indicators between a source of potential and ground, the gate of each of said silicon controlled rectifiers being connected to respective ones of said conductive buses.

9. The apparatus of claim 8 further comprising means for temporarily removing the source of potential from said silicon controlled rectifiers to thereby cut them off and erase the output indication.

10. The apparatus of claim 7 further including means for selectively inhibiting the output of combinations containing at least one of at least one predetermined one of said sublengths, comprising normally open switch means coupled between each of said conductive buses and ground and means for selectively closing said switches to thereby ground each of said optimum combination terminals which are coupled to the conductive buses corresponding to the selectively closed switches.

11. The apparatus of claim 1 wherein said means responsive to said signal comprises a gating circuit having a turnon input coupled to receive said signal, a turnoff input coupled to said output means and an output terminal coupled to said means for synchronously scanning said plurality of overall length terminals, said gating circuit further comprising means for generating a continuous potential on said output terminal in response to said signal and means responsive to a signal on said turnoff input, caused by an output indication, for cutting off said potential on said output terminal and for grounding said turnon input terminal to thereby prevent the application of potential to said overall length terminals subsequent to an output indication and to prevent further signals on said turnon input from causing said gate to generate potential on said output terminal.

12. The apparatus of claim 11 wherein said gating circuit comprises a flip-flop said flip-flop being set in response to a signal at said turn input and reset in response to a signal on said turnoff input, and further comprising an output transistor, said output transistor being cut off when said flip-flop is reset and biased to conduct when said flip-flop is set, the emitter-collector path of said transistor being adapted to be connected between a source of potential and said output terminal.

13. The apparatus of claim 11 wherein said means responsive to a signal at said turnoff input for grounding said turnon input comprises a silicon controlled rectifier having an anode cathode and gate electrode, the anode-cathode path being connected between said turnon input and ground, said gate electrode being connected to said turnoff input terminal.

14. The apparatus of claim 1 wherein said means for scanning said plurality of selectable terminals and means for scanning said plurality of overall length terminals comprise a scanning element having a first wiper contact for scanning said plurality of circuits and a plurality of second wiper contacts corresponding to said sublengths for scanning said plurality of overall length terminals, said plurality of second wiper contacts being positioned on said scanning element such that, when said first wiper contact is scanning the one of said plurality of circuits corresponding to the maximum incremental length, each of said second wiper contacts is in contact with the particular one of said plurality of overall length terminals corresponding to an overall length equal to the maximum incremental length plus the sublength with which each of said second wiper contacts corresponds.

15. The apparatus of claim 14 further comprising a source of potential, means coupling said source of potential to said first wiper contact, a plurality of normally open switches, one terminal of said normally open switches being connected to respective ones of said second wiper contacts, the other terminal of said plurality of normally open switches being connected to said means for generating a potential in response to said signal, and input means for selectively closing the one of said normally open switches corresponding to said selected one of said M sublengths.

16. The apparatus of claim 15 further comprising drive means for causing relative movement between said scanning element and said plurality of selectable circuits and said plurality of overall length terminals.

17. The apparatus of claim 16 wherein said drive means comprises electrical motor means mechanically coupled to said scanning element and adapted to drive said scanning element from a home position over said plurality of circuits and overall length terminals and back to said home position in response to a start command.

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