US3566160A - Simplified race-preventing flip-flop having a selectable noise immunity threshold - Google Patents

Simplified race-preventing flip-flop having a selectable noise immunity threshold Download PDF

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US3566160A
US3566160A US559887A US3566160DA US3566160A US 3566160 A US3566160 A US 3566160A US 559887 A US559887 A US 559887A US 3566160D A US3566160D A US 3566160DA US 3566160 A US3566160 A US 3566160A
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input
transistor
conduction path
current conduction
charge storage
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Thomas E Osborne
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/22—Static coding
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318525—Test of flip-flops or latches
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G—PHYSICS
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    • G06F1/26—Power supply means, e.g. regulation thereof
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    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
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    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/325—Display of status information by lamps or LED's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
    • G—PHYSICS
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G06F3/0227—Cooperation and interconnection of the input arrangement with other functional units of a computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/18—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible a small local pattern covering only a single character, and stepping to a position for the following character, e.g. in rectangular or polar co-ordinates, or in the form of a framed star
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • First and second transistors are arranged as a flip-flop in which the base of each transistor is connected by a separate resistor to the collector of the other transistor, the collector of each transistor is connected by a separate resistor to a source of supply voltage, and the emitter of each transistor is connected to a source of reference voltage.
  • a first input drive circuit is connected to the base of the first transistor.
  • This input drive circuit includes a capacitorand a resistor serially connected between the base of the first transistor and the source of supply voltage. It also includes an input transistor having its collector connected by the capacitor to the base of the first transistor, its base connected by a diode to the collector of the first transistor, and its emitter connected to a source of adjustable voltage having a value intermediate to the values of the supply and reference voltages.
  • a second input drive circuit of the same type as the first is similarly connected to the base of the second transistor. See FIGS. 29 and 29' and under the heading FLIP-F LOP DRIVER AND GATING. Such flip-flops are employed in the internal control and subroutine logic of a calculator.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Computing Systems (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Remote Sensing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Storage Device Security (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)

Abstract

First and second transistors are arranged as a flip-flop in which the base of each transistor is connected by a separate resistor to the collector of the other transistor, the collector of each transistor is connected by a separate resistor to a source of supply voltage, and the emitter of each transistor is connected to a source of reference voltage. A first input drive circuit is connected to the base of the first transistor. This input drive circuit includes a capacitor and a resistor serially connected between the base of the first transistor and the source of supply voltage. It also includes an input transistor having its collector connected by the capacitor to the base of the first transistor, its base connected by a diode to the collector of the first transistor, and its emitter connected to a source of adjustable voltage having a value intermediate to the values of the supply and reference voltages. A second input drive circuit of the same type as the first is similarly connected to the base of the second transistor. See FIGS. 29 and 29'' and under the heading FLIP-FLOP DRIVER AND GATING. Such flip-flops are employed in the internal control and subroutine logic of a calculator.

Description

United States Patent [72] Inventor Thomas E. Osborne San Francisco, Calif.
[21 Appl. No. 559,887
[22] Filed June 23, 1966 [45] Patented Feb. 23, 1971 [73] Assignee Hewlett-Packard Company Palo Alto, Calif.
[54] SIMPLIFIED RACE-PREVENTING FLIP-FLOP HAVING A SELECTABLE NOISE IMMUNITY THRESHOLD 16 Claims, 39 Drawing Figs.
[52] U.S. Cl 307/291, I
[51] Int. Cl I103k 3/12 [50] Field of Search 307/291,
[5 6] References Cited UNITED STATES PATENTS 3,102,208 8/1963 Reach, .lr 307/292X 3,294,980 12/1966 Whittle 328/196X 3,334,249 8/1967 White 307/292X 3,351,778 11/1967 Seelbach et al 307/291 Stern 3,045,128 7/1962 Skerritt 307/292 3,046,413 7/1962 Clapper... 307/292 3,100,848 8/1963 Skerritt 307/292 Primary Examiner-Stanley D. Miller, J r. Att0rney-Roland l. Griffin ABSTRACT: First and second transistors are arranged as a flip-flop in which the base of each transistor is connected by a separate resistor to the collector of the other transistor, the collector of each transistor is connected by a separate resistor to a source of supply voltage, and the emitter of each transistor is connected to a source of reference voltage. A first input drive circuit is connected to the base of the first transistor. This input drive circuit includes a capacitorand a resistor serially connected between the base of the first transistor and the source of supply voltage. It also includes an input transistor having its collector connected by the capacitor to the base of the first transistor, its base connected by a diode to the collector of the first transistor, and its emitter connected to a source of adjustable voltage having a value intermediate to the values of the supply and reference voltages. A second input drive circuit of the same type as the first is similarly connected to the base of the second transistor. See FIGS. 29 and 29' and under the heading FLIP-F LOP DRIVER AND GATING. Such flip-flops are employed in the internal control and subroutine logic of a calculator.
OUTPUT OUTPUT FLIP- FLOP PATENTED FEB23 m SHEET 05 0F 31 ERROR ATTEMPTED BY ZERO COMPARE K05 W05. PUT 516M 0F 000x TD5 FORM [0'5 COMPLEM.
FORM /'5 COMPLfMfNT OF (TIA) AND EACH TD CHARACTER (TIA) *vvm (TD)+WD OF KO -9 mm rue ms comm 15W T0 FIG. 3 5 smre INVENTOR.
BY THOMAS E. OSBORNE @M/ZQJ A TTORA/E Y5 PATH-HEB FEB23 rs?! SHEET 07 0F 31 m QI bk REG INVENTOR. THOMAS E. OSBORNE m wt E 5G 6% 2 $2M? REES PATENTEUFEBNIQYI 3566.160
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KBD ANS TMP WRK F42 MEMO ME/Vll KAENAUGH MAP OF Wow NCOD/NG INVENTOR. ,0 THOMAS 6. 0550mm @Awkiw ATTOK/VEVS PATEHTH] FEB23 m SHEET 11 0F 31 YLCV ///I 1 I weum, vs/m com/e01. LOG/C Fl INVENTOR,
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FROM SIHO SUBROUT/Nf ACCU/VIULATZ 5 0000 FIG... /3
SHEET NOKMAL/ZE INVENTOR. THOMAS E. OSBOk/VE A 770 NE V5 PATENTEDFEBZBIQYI 3566,1550
sum 17 [1F 31 SELECT D SELECT REGISTER TO BE SHIFTED 0000 ISTO, IKBF, IlCF I (CFF) /000 INVENTOR THOMAS if. OSBORNE BY SUBROUT/NE SH/FT 50/0/ 2 4 r w ATTOENEY5 PATENTEUmzamn I 3.566160 SHEET 19M 31 SUI/II 04012 12051 100405400150 CMP K80 LLS WRK I 00/ (1M, 1640, [66F I I IRDR [WI/I J43, 10F] gram 1A], J43, 110, 104/055 Km @0 i wyww 6MP KBD {NVHNTOR 5 0/// THOMAS E. OSBOE/Vf IBY ATTORNEYS

Claims (17)

1. In a J-K flip-flop having: A. first and second switch means adapted to give alternate outputs; B. cross-connection means between the switch means for turning one switch off when the other switch is on; and C. first and second drive means for turning on said first and second switch means respectively; the improvement comprising; 1. a first input transistor for said first drive means and a second input transistor for said second drive means with each of said transistors having, a. a base adapted to be connected to an input line to receive an input signal, b. a collector connected to said drive means for operating the drive means, and c. an emitter; 2. a first diode connecting the base of said first transistor to the output of said first switch means and a second diode connecting the base of said second transistor to the output of said second switch means, said diodes making said flip-flop a J-K flip-flop; and 3. a source of adjustable voltage connected to the emitters of said transistors for controlling the signal level required in said input lines to operate said flip-flop.
2. a first diode connecting the base of said first transistor to the output of said first switch means and a second diode connecting the base of said second transistor to the output of said second switch means, said diodes making said flip-flop a J-K flip-flop; and
2. A flip-flop comprising: first and second switching devices, each of said switching devices having an input and an output and being operable in different conductive conditions; bias means, including a first crosscoupling path connecting the input of said first switching device to the output of said second switching device and a second crosscoupling path connecting the input of said second switching device to the output of said first switching device, for biasing said switching devices to operate in a first state in which the first switching device is in a more conductive condition than the second switching device or to operate in a second state in which the second switching device is in a more conductive condition than the first switching device; a first input drive circuit including a first signal input, a first input drive path connecting the first signal input to the input of said first switching device, and a first charge storage device connected in said first input drive path for driving the input of said first switching device to operate said first switching device in its more conductive condition and thereby cause said first and second switching devices to operate in said first state in response to removal of an input signal applied to said first signal input; and a second input drive circuit including a second signal input, a second input drive path connecting The second signal input to the input of said second switching device, and a second charge storage device connected in said second input drive path for driving the input of said second switching device to operate said second switching device in its more conductive condition and thereby cause said first and second switching devices to operate in said second state in response to removal of an input signal applied to said second signal input.
3. a source of adjustable voltage connected to the emitters of said transistors for controlling the signal level required in said input lines to operate said flip-flop.
3. A flip-flop as in claim 2 wherein: said first input drive path includes a portion of a first current conduction path for charging said first charge storage device in one direction and a portion of a second current conduction path for charging said first charge storage device in the opposite direction, said first input drive circuit being responsive to application of an input signal to said first signal input for charging said first charge storage device in said one direction and being responsive to removal of this input signal for charging said first charge storage device in said opposite direction to operate said first switching device in its more conductive condition and thereby cause said first and second switching devices to operate in said first state; and said second input drive path includes a portion of a third current conduction path for charging said second charge storage device in said one direction and a portion of a fourth current conduction path for charging said second charge storage device in said opposite direction, said second input drive circuit being responsive to application of an input signal to said second signal input for charging said second charge storage device in said one direction and being responsive to removal of this input signal for charging said second charge storage device in said opposite direction to operate said second switching device in its more conductive condition and thereby cause said first and second switching devices to operate in said second state.
4. A flip-flop as in claim 3 wherein: said first input drive circuit includes a first impedance device connected in said second current conduction path in series with said first charge storage device and includes a third switching device having an input connected to said first signal input and having an output connected in said first current conduction path to a point intermediate said first impedance and charge storage devices, said third switching device being responsive to application of an input signal to said first signal input for completing said first current conduction path to charge said first charge storage device in said one direction and being responsive to removal of this input signal for interrupting said first current conduction path, thereby permitting said second current conduction path to charge said first charge storage device in said opposite direction; and said second input drive circuit includes a second impedance device connected in said fourth current conduction path in series with said second charge storage device and includes a fourth switching device having an input connected to said second signal input and having an output connected in said third current conduction path to a point intermediate said second impedance and charge storage devices, said fourth switching device being responsive to application of an input signal to said second signal input for completing said third current conduction path to charge said second charge storage device in said one direction and being responsive to removal of this input signal for interrupting said third current conduction path, thereby permitting said fourth current conduction path to charge said second charge storage device in said opposite direction.
5. A J-K flip-flop comprising: first and second switching devices, each of said switching devices having an input and an output and being operable in different conductive conditions; bias means connecting the input of each of said switching devices to the output of the other of said switching deviCes for biasing said switching devices to operate in a first state in which the first switching device is in a more conductive condition than the second switching device or to operate in a second state in which the second switching device is in a more conductive condition than the first switching device; first input drive means for causing said first and second switching devices to operate in said first state, said first input drive means including a first charge storage device connected to the input of said first switching device, a portion of a first current conduction path for charging said first charge storage device in one direction, a portion of a second current conduction path for charging said first charge storage device in the opposite direction, a first impedance device connected in said second current conduction path in series with said first charge storage device, and a third switching device having an input and having an output connected in said first current conduction path to a point intermediate said first impedance and charge storage devices, said third switching device being responsive to application of an input signal to its input for completing said first current conduction path to charge said first charge storage device in said one direction and being responsive to removal of this input signal for interrupting said first current conduction path and thereby permitting said second current conduction path to charge said first charge storage device in said opposite direction to cause said first and second switching devices to operate in said first state; second input drive means for causing said first and second switching devices to operate in said second state, said second input drive means including a second charge storage device connected to the input of said second switching device, a portion of a third current conduction path for charging said second charge storage device in said one direction, a portion of a fourth current conduction path for charging said second charge storage device in said opposite direction, a second impedance device connected in said fourth current conduction path in series with said second charge storage device, and a fourth switching device having an input and having an output connected in said third current conduction path to a point intermediate said second impedance and charge storage devices, said fourth switching device being responsive to application of an input signal to its input for completing said third current conduction path to charge said second charge storage device in said one direction and being responsive to removal of this input signal for interrupting said third current conduction path and thereby permitting said fourth current conduction path to charge said second charge storage device in said opposite direction to cause said first and second switching devices to operate in said second state; a first unidirectional current conducting device connected between the input of said third switching device and the output of said first switching device, said first unidirectional current conducting device being poled for preventing said third switching device from completing said first current conduction path in response to application of an input signal to its input during operation of said first and second switching devices in said first stage; and a second unidirectional current conducting device connected between the input of said fourth switching device and the output of said second switching device, said second unidirectional current conducting device being poled for preventing said fourth switching device from completing said third current conduction path in response to application of an input signal to its input during operation of said first and second switching devices in said second state.
6. A J-K flip-flop as in claim 5 wherein: said first and second switching devices comprise first and second transistors, each of said transistors having a base comprising its input, a collEctor comprising its output, and an emitter; said third switching device comprises a third transistor having a base comprising its input, a collector comprising its output, and an emitter; said first unidirectional current conducting device comprises a first diode having one terminal connected to the base of said third transistor and having another terminal connected to the collector of said first transistor; said fourth switching device comprises a fourth transistor having a base comprising its input, a collector comprising its output, and an emitter; and said second unidirectional current conducting device comprises a second diode having one terminal connected to the base of said fourth transistor and having another terminal connected to the collector of said second transistor.
7. A J-K flip-flop as in claim 6 wherein the emitter of each of said third and fourth transistors is connected to a source of voltage selected for controlling the minimum input signal level required for causing said first and second transistors to switch from operation in one of said first and second states to operation in the other of said first and second states.
8. A J-K flip-flop as in claim 7 wherein: said first and second charge storage devices comprise first and second capacitors each having a pair of terminals, one terminal of said first capacitor being connected to the base of said first transistor and one terminal of said second capacitor being connected to the base of said second transistor; said first and second impedance devices comprise first and second resistors each having a pair of terminals, one terminal of said first resistor being connected to the other terminal of said first capacitor and one terminal of said second resistor being connected to the other terminal of said second capacitor; and a source of supply voltage connected to the other terminal of each of said first and second resistors.
9. A J-K flip-flop as in claim 8 wherein said bias means comprises: a first direct current connection, including a third resistor, between the base of said first transistor and the collector of said second transistor; a second direct current connection, including a fourth resistor, between the base of said second transistor and the collector of said first transistor; a third direct current connection, including a fifth resistor, between the collector of said first transistor and a source of supply voltage; a fourth direct current connection, including a sixth resistor, between the collector of said second transistor and a source of supply voltage; a fifth direct current connection between the emitter of said first transistor and a source of reference voltage; and a sixth direct current connection between the emitter of said second transistor and said source of reference voltage.
10. A J-K flip-flop as in claim 9 wherein: said first current conduction path includes said first capacitor, said third transistor, and the source of voltage connected to the emitter of said third transistor; said second current conduction path includes said first resistor, said first capacitor, and said first transistor; said third current conduction path includes said second capacitor, said fourth transistor, and the source of voltage connected to the emitter of said fourth transistor; and said fourth current conduction path includes said second resistor, said second capacitor, and said second transistor.
11. A J-K flip-flop as in claim 6 wherein: said first impedance device is serially connected between said first charge storage device and a source of supply voltage; said second impedance device is serially connected between said second charge storage device and a source of supply voltage; the emitter of each of said first and second transistor is connected to a source of reference voltage; and the emitter of each of said third and fourth transistors is connected to a source of voltage having a value intermediate to the values of said reference and supply voltages. 12. A flip-flop comprising: first and second switching devices, each of said first and second switching devices being operable in different conductive conditions and having a first electrode comprising its input, a second electrode comprising its output, and a third electrode connected to a source of reference voltage; bias means connecting the first electrode of each of said switching devices to the second electrode of the other other of said switching devices for biasing said switching devices to operate in a first state in which the first switching device is in a more conductive condition than the second switching device or to operate in a second state in which the second switching device is in a more conductive condition than the first switching device; first input drive means including a first charge storage device connected to the first electrode of said first switching device, a first impedance device serially connected between said first charge storage device and a source of supply voltage, and a third switching device having a first electrode connected to a first input terminal, a second electrode connected to a point between said first impedance and charge storage devices, and a third electrode, said first input drive means being responsive to an input signal applied to the first input terminal for causing said first and second switching devices to operate in said first state; second input drive means including a second charge storage device connected to the first electrode of said second switching device, a second impedance device serially connected between said second charge storage device and a source of supply voltage, and a fourth switching device having a first electrode connected to a second input terminal, a second electrode connected between said second impedance and charge storage devices, and a third electrode, said second input drive means being responsive to an input signal applied to the second input terminal for causing said first and second switching devices to operate in said second state; and the third electrode of each of said third and fourth switching devices being connected to a source of voltage having a value intermediate to the values of said supply and reference voltages.
13. A flip-flop as in claim 12 wherein the source of voltage to which the third electrode of each of said third and fourth switching devices is connected is selected for controlling the minimum input signal level required for causing said first and second switching devices to switch from operation in one of said first and second states to operation in the other of said first and second states.
14. A flip-flop comprising: first and second switching devices, each of said switching devices having an input and an output and being operable in different conductive conditions; bias means connecting the input of each of said switching devices to the output of the other of said switching devices for biasing said switching devices to operate in a first state in which the first switching device is in a more conductive condition than the second switching device or to operate in a second state in which the second switching device is in a more conductive condition than the first switching device; first input drive means for causing said first and second switching devices to operate in said first state, said first input drive means including a first charge storage device connected to the input of said first switching device, a portion of a first current conduction path for charging said first charge storage device in one direction, a portion of a second current conduction path for charging said first charge storage device in the opposite direction, a first impedance device connected in said second current conduction path in series with said first charge storage device, and a third switching device having a first electrode comprising its input, a second Electrode comprising its output, and a third electrode, said third switching device having its output connected in said first current conduction path to a point intermediate said first impedance and charge storage devices, being responsive to application of an input signal to its input for completing said first current conduction path to charge said first charge storage device in said one direction, and being responsive to removal of this input signal for interrupting said first current conduction path and thereby permitting said second current conduction path to charge said first charge storage device in said opposite direction to cause said first and second switching devices to operate in said first state; second input drive means for causing said first and second switching devices to operate in said second state, said second input drive means including a second charge storage device connected to the input of said second switching device, a portion of a third current conduction path for charging said second charge storage device in said one direction, a portion of a fourth current conduction path for charging said second charge storage device in said opposite direction, a second impedance device connected to said fourth current conduction path in series with said second charge storage device, and a fourth switching device having a first electrode comprising its input, a second electrode comprising its output, and a third electrode, said fourth switching device having its output connected in said third current conduction path to a point intermediate said second impedance and charge storage devices, being responsive to application of an input signal to its input for completing said third current conduction path to charge said second charge storage device in said one direction, and being responsive to removal of this input signal for interrupting said third current conduction path and thereby permitting said fourth current conduction path to charge said second charge storage device in said opposite direction to cause said first and second switching devices to operate in said second state; and the third electrode of each of said third and fourth switching devices being connected to a source of adjustable voltage for controlling the minimum input signal level required for causing said first and second switching devices to switch from operation in one of said first and second states to operation in the other of said first and second states.
15. A flip-flop comprising: first and second transistors, each of said transistors being operable in different conductive conditions and having a base, a collector, and an emitter; bias means for biasing said transistors to operate in a first state in which the first transistor is in a more conductive condition than the second transistor of to operate in a second state in which the second transistor is in a more conductive condition than the first transistor, said bias means comprising a first resistor included in a direct current connection between the base of said first transistor and the collector of said second transistor, a second resistor included in a direct current connection between the base of said second transistor and the collector of said first transistor, a third resistor included in a direct current connection between the collector of said first transistor and a source of supply voltage, a fourth resistor included in a direct current connection between the collector of said second transistor and a source of supply voltage, a direct current connection between the emitter of said first transistor and a source of reference voltage, and a direct current connection between the emitter of said second transistor and a source of reference voltage; first input drive means for causing said first and second transistors to operate in said first state, said first input drive means including a first capacitor connected to the base of said first transistor, a portion of a first current conduction path for charging said First capacitor in one direction, a portion of a second current conduction path for charging said first capacitor in the opposite direction, a fifth resistor connected in said second current conduction path in series with said first capacitor, and a third transistor having a base, an emitter connected to a source of voltage having a value intermediate to the values of said reference and supply voltages, and a collector connected in said first current conduction path to a point intermediate said fifth resistor and said first capacitor, said third transistor being responsive to application of an input signal to its base for completing said first current conduction path to charge said first capacitor in said one direction and being responsive to removal of this input signal for interrupting said first current conduction path and thereby permitting said second current conduction path to charge said first capacitor in said opposite direction to cause said first and second transistors to operate in said first state; and second input drive means for causing said first and second transistors to operate in said second state, said second input drive means including a second capacitor connected to the base of said second transistor, a portion of a third current conduction path for charging said second capacitor in said one direction, a portion of a fourth current conduction path for charging said second capacitor in said opposite direction, a sixth resistor connected in said fourth current conduction path in series with said second capacitor, and a fourth transistor having a base, an emitter connected to a source of voltage having a value intermediate to the values of said reference and supply voltages, and a collector connected in said third current conduction path to a point intermediate said sixth resistor and said second capacitor, said fourth transistor being responsive to application of an input signal to its base for completing said third current conduction path to charge said second capacitor in said one direction and being responsive to removal of this input signal for interrupting said third current conduction path and thereby permitting said fourth current conduction path to charge said second capacitor in said opposite direction to cause said first and second switching devices to operate in said second state.
16. A flip-flop as in claim 15 wherein: said first current conduction path includes said first capacitor, said third transistor, and the source of voltage connected to the emitter of said third transistor; said second current conduction path includes said fifth resistor, said first capacitor, and said first transistor; said third current conduction path includes said second capacitor, said fourth transistor, and the source of voltage connected to the emitter of said fourth transistor; and said fourth current conduction path includes said sixth resistor, said second capacitor, and said second transistor.
US559887A 1966-06-23 1966-06-23 Simplified race-preventing flip-flop having a selectable noise immunity threshold Expired - Lifetime US3566160A (en)

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DE1774988C3 (en) 1979-05-03
DE1774988B2 (en) 1978-09-14
DE1774986A1 (en) 1973-08-09
DE1799012B1 (en) 1981-01-29
CA919305A (en) 1973-01-16
JPS544218B1 (en) 1979-03-03
DE1549455A1 (en) 1971-02-18
DE1774986C3 (en) 1975-02-06
DE1774986B2 (en) 1974-06-12
DE1799012C3 (en) 1981-10-15
DE1774988A1 (en) 1973-07-05
DE1774987B2 (en) 1974-06-27
GB1197291A (en) 1970-07-01
FR1529144A (en) 1968-06-14
DE1774987A1 (en) 1973-07-05
DE1774987C3 (en) 1975-02-13

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