US3549874A

US3549874A - Computer for simultaneous computation of a reference signal and an information signal until reference signal reaches a predetermined value

Info

Publication number: US3549874A
Application number: US619710A
Authority: US
Inventors: Alvin Vachitis
Original assignee: DRANETZ ENG LAB Inc
Current assignee: DRANETZ TECHNOLOGIES Inc
Priority date: 1967-03-01
Filing date: 1967-03-01
Publication date: 1970-12-22
Anticipated expiration: 1987-12-22

Description

United States Patent Inventor Alvin Vachitis Englishtown, NJ. Appl. No. 619,710 Filed Mar. 1, 1967 Patented Dec. 22, 1970 Assignee Dranetz Engineering Laboratories,

Incorporated Plainfleld, NJ. a corporation of New Jersey COMPUTER FOR SIMULTANEOUS COMPUTATION OF A REFERENCE SIGNAL AND AN INFORMATION SIGNAL UNTIL REFERENCE SIGNAL REACHES A PREDETERMINED VALUE Primary Examiner-Eugene G. Botz Assistant Examiner-Joseph F. Ruggiero Attorney-Wallenstein, Spangenberg, l-lattis & Strampel ABSTRACT: A computer utilizing a reference signal and an information signal wherein said signals are simultaneously computed (such as division and/or multiplication, or time integration) until the computed reference signal reaches a predetermined value, whereby the computed reference signal indicates the desired computation of the information signal. Where the computation is a time integration over a time interval, the time interval is determined by the time integrated reference signal reaching a predetermined voltage value corresponding to the end of the time interval, and the time integrated information signal indicates the time integral of the information signal regardless of variations in the reference signal and the related information signal. Where the reference and information signals are cyclic wave signals, the integration of said signals is begun at the start of a half-cycle (preferably the first half-cycle) of the reference signal, is continued until the time integrated reference signal reaches at least said predetermined value, and then at the start of an ensuing halfcycle (preferably the next first half-cycle) of the reference signal, the integration is stopped and the integrated reference and information signals are partially discharged until the time integrated reference signal returns to said predetermined value, whereby the time integrated information signal indicates the time integral of the information signal for an integral number of half-cycles or full cycles over the time interval.

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coivrru'rsn FOR SIMULTANEOIIS CONWUTATION or A ssrsnsncs SIGNAL AND AN- i TION SIGNAL UNTIL REFERENCE SIGNAL 2 C PREIDETERMII it VALUE BACKGROUND OF INVENTION 'ageiproducing the signals and, also, where cyclic wave signals are integrated, due to failure to integrate integral numbers of half-cycles or full cycles of said cyclic wave signals.

SUMMARY 0s THE INVENTION In accordance with this invention, the aforementioned deficiencies and inaccuracies are eliminatedl Here, in accordance with one aspect of this invention, .a' reference signal and a related information signal are providedjand computations or integrations with respect to time of bothof these signals are simultaneously continued until thecomputed or integrated reference signal reaches a predetermined'value. Then, the computations or integrations are simultaneously stopped and thecomputed or time integrated'information signal indicates the computation or time integral of the information signal. Unwanted variations in the voltage providing the reference and information signals are completely compensated for, the time interval being shortened upon increases in voltage and being lengthened upon decreases in voltage, with the result that accurate computations or integrations for the time inter valare assured.

Where the reference and information signals are cyclic Wave signals, as for example, AC signals or the like, they are processed, as for example, by inverting the second half-cycles to provide processed reference and information signals which are integrated with respect to time. Here, in accordance with a further aspect of this invention, the simultaneous integrations I of the processed signals are begun at'the start of a half-cycle (preferably the first half-cycle) of the reference cyclic wave signal, are continued until the computed or time integrated reference signal reaches at least said predetermined value, and then, at the start of an ensuing half-cycle (preferably the next fustwhalf-cycle) of the reference cyclic wave signal, the computa'tions or integrations are simultaneously stopped and the computed or integrated reference and information signals are partially discharged or decreased until the computed or integrated reference signal returns to said predetermined value. The computed or time integrated information signal thereuponindicates the computation or time integral of the informa tiori cyclic wave signal for an integral number of half-cycles or full cycles over the time interval, thus avoiding inaccuracies which would be caused by asymmetric integration of the cyclic wave signals, the resultant output being the voltage ratio at the average values of the cyclic signals.

One principal object of this invention resides in the computing method and another principal object of this invention resides in an apparatus for performing the computing method.

Some significant advantages of the computing method and the computer of this invention over other methods and apparatus for obtaining similar functions are as follows. The computation can be performed upon as few as one cycle of information. The input signals may be continuous wave or gated wave trains. With an external trigger or timing signal, the computation can be performed at any desired time after the signal source is turned on. Computations or integrations are always performed for time intervals which preferably are an integral multiple of cycles of the input signals and which are then normalized to a value that would have resulted in the designed time interval. F ullwave synchronous detection reduces the errors resulting from second harmonic distortion of the signal inputs and provides the means for trigonometric computations. After the computation has been performed, the output signal may be pure DC. The output signal may be held at its value for a long period of time dependent only upon the quality of the integrators, namely, the quality of the integrating capacitors and operational amplifiers. An externally controlled DC signal may be applied to perform additional multiplication or division simultaneously with the computation. Any number of additional computing elements (with control circuitry) may be added to the basic unit so that all related computations can be accomplished simultaneously. After the output has been measured, the comparator voltage input may then be varied to perform additional computations.

Other objects of this invention residein the combination of computing steps. and in the combination of elements forming the computer, and in the cooperative relationships therebetween. I

Further objects and advantages of this invention will become apparent to those skilled in the art upon reference to the accompanying specification, claims and drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified schematic wiring diagram generally illustrating the construction and the manner of operation of the preferred form of the computer of this invention for providing integrations over a time interval;

FIG. 2 is a chart generally illustrating the control and integration of the reference and the information signals;

FIG. 3 is a schematic diagram of a sinusoidal AC system for producing reference and information signals with respect to an impedance device wherein the signals may be computed by the computer illustrated in FIGS. 8A and 8B;

FIG. 4 is a schematic wiring diagram similar to FIG. 3 and illustrating different connections to be made to the computer; i

FIG. 5 is a schematic diagram of a system for producing reference and information signals in connection witha device under test and it also may be utilized in connection with the computer of FIGS. 8A and 8B FIG. 6 is a schematic diagram for testing acoustical devices or the like and for producing. reference and information signals to be computed by the computer of FIGS. 8A and 8B;

. FIG. 7 is a schematic diagram of another circuit for producing reference and information signals in connection with a device under test wherein the sine wave signals have high distortion and/or high harmonic components;

FIGS. 8A and 8B constitute a block diagram of the preferred form of the computer of this invention;

FIG. 9 is a series of curves illustrating the various signals present in the reference channel of the computer of FIGS. 8A and 813 under certain operating conditions;

FIG. 10 is a series of curvesoccuring in the information channel of the computer wherein the computer is arranged for computing the series resistance component of the impedance of FIG. 3;

FIG. 11 is a series of curves occuring in the information channel of the computer for computing the series reactance component of the impedance of F IG. 3;

FIG. 12 is a series of curves occuring in the information channel of the computer for computing the magnitude of the impedance of FIG. 3;

FIG. 13 is a series of curves appearing in the information channel of the computer for computing the power factor with respect to the impedance of FIG. 3;"

FIG. M is a series of curves appearing in the reference DESCRIPTION OF THE PREFERREDEMBODIMENTS For a general understanding of this invention, reference is made first to the simplified schematic wiring diagram of FIG. I for providing time integrations over a time interval. Here, a source of voltage is applied to a terminal 50 of a network including series resistances R5 and R6 connected to ground and series resistances R7 and R8 connected to ground. The resistance R8 represents the resistance of an electrical device under test. For 1 percent accuracy of measurement of resistance R8, the resistance R7 should be at least 100 times larger than resistance R8. It is desirable that the ratio of resistance R6 to resistance R5 be equal to the ratio of resistance R7 to the maximum value of resistance R8. The juncture of resistances R5 and R6 provides an information signal E1 which is proportional to the applied voltage, and the juncture of the resistances R7 and R8 provides an information signal E2 which is determined by the value of the: resistance R8 of the device under test. In accordance with' one-aspect of this invention the reference signal E1 and the information signal E2 are simultaneously integrated over a desired predetermined time interval. The resistance R6 is so selected or adjusted that under ideal voltage conditions the integration of the reference signal E1 to a predetermined value will occur in said desired predetermined time interval. The resistance R6 is so selected or adjusted that under ideal voltageconditions the integration of the reference signal E1 to a predetermined value will occur in said desired predetermined time interval. The reference signal E1 is routed through a reference'channel including an integrator which may comprise a resistance RI, a capacitor C1 and an operational amplifier for producing an integrated reference signal E14. The information signal E2 is routed through an information channel including an integrator which may comprisea resistance R3, a capacitor C2 and an operational amplifier 16 for producing an integrated information signal E38. The reference channel integrator and the information channel integrator have the same integrating characteristics and in this respect the resistance values of R1 and R3 are the same, the capacitance values of the capacitors Cl and C2 are the same and the amplifying characteristics of the operational amplifiers 15 and'16 are the same.

The computer also includes avoltage comparator 35, labeled VOLT COMP, to which is supplied a DC comparator voltage signal input E from a terminal B. The computer further includes a pair of switches SW7 and SW15 for controlling the simultaneous application of the reference signal E1 and the infonnation signal E2 to their respective integrators. The reference channel integratorand the information channel integrator are provided with switches SW8 and SW16 which are for the purpose of simultaneously completely discharging the integrators when they are closed. The reference channel integrator and the information channel integrator are also respectively provided with a discharge circuit including resistance R2 and switch SW9 and a discharge circuit including resistance R4 and switch'SW17 for simultaneously partially discharging the integrators when the switches SW9 and SW17 are closed, the resistances R2 and R4 being equal. The operations of the switches SW7, SW15, SW3, SW16, SW9 and SW17 are controlled by control circuits schematically illustrated in dotted lines in FIG. 1 in response to a signal pulse E3 and the voltage comparator 35. The value of the resistance R6 is such that the reference signal E1 is integrated to an integrated reference signal value E14 which is equal to the reference voltage value E25 within the desired predetermined time interval. In other words, if there were no unwanted variations in the voltage applied to the terminal 50 the iarlrtegration would take place precisely within the time interv When a pulse E3 is applied to the control circuitry, the switches SW8 and SW16 are simultaneously closed as indicated at 51 in FIG. 2 so that any prior integrated signals E14 and E38 which may be present will be immediately discharged to zero, the complete discharging being indicated at 52 in FIG.

2, following which the switches SW8 and SW16 are then opened. Also, following such complete discharge of the integrators the switches SW7 and SW15 are simultaneously closed as indicated at 53 in FIG. 2 to start the integration of the reference signal El (which may be processed as indicated at E12) and the information signal E2 (which may be processed as indicated at E36). The integration proceeds as illustrated by the sloping curves E14 and E38 in FIG. 2 until such time as the value of the integrated signal EM reaches the value of the comparator voltage input E25 as indicated at 54 in FIG. 2. Where the voltage source applied to the terminal is a DC voltage, the discharge circuits R2, SW9 and R4, SW17 need not be utilized and, here, the voltage comparator 35 may then produce a signal for opening the switches SW7 and SW15 for stopping the integration, and the integrated information signal E38 at time 54 in FIG. 2 will represent the integrated value of the information signal E2 during such predetermined time interval and may be measured at output A in FIG. l, the signal being a DC signal and being held by the information channel integrator just as the integrated signal E14 is held by the reference channel integrator. In the event that there are no unwanted variations in the voltage supply to terminal 50, the integrations will be completed precisely within the desired predetermined time interval between 53 and 54 as indicated in FIG. 2.

However, unwanted variations in the voltage supply may have an effect upon the integrations of the signals and if there should be increases in the voltage, the slopes of the integrating curves E14 and E38 will increase and the integrations will be terminated before the precise time indicated at 54 in FIG. 2, and upon decrease in the voltage, the slopes of the integrating curves E14 and E38 will be decreased and the integrations will be terminated after the precise time indicated at 54 in FIG. 2. Thus, accurate time integrations of the reference and information signals are obtained and variations in the supply voltage are automatically compensated for. This is true where the voltage supply is DC or in cyclic wave form, such as AC or the like.

Where the voltage supply to terminal 50 is in cyclic wave form, such as AC or the like, the, integrations of the reference signal E1 and the information signal E2 are simultaneously begun at the start of a first half-cycle of the reference signal E1. In this respect, following discharge of the previous integrated reference and information signals E14 and E38, as expressed above and as indicated at 51 and 52 in FIG. 2, the switches SW7 and SW15 are simultaneously closed at the start of a first half-cycle of the reference signal E1 so that the processed reference and information signals E12 and E36 begin to be integrated as indicated at 53 in FIG. 2. The simultaneous integration continues along the sloping curves E14 and E38 until the integrated reference signal E14 reaches a value corresponding to the value of the comparator voltage input signal E25 as indicated at 54 in FIG. 2 and as described above to provide accurate integrations of the reference and information signals over the time interval between 53 and 54.

However, here, when this occurs the voltage comparator 35 produces a signal which is made available for the purpose of opening switches SW7 and SW15 but which does not then do so. As a result, the integrations continue beyond time 54 as illustrated in FIG. 2. However, at the start of the next first halfcycle of the reference signal E1, the voltage comparator signal becomes effective to open simultaneously the switches SW7 and SW15 to stop the integrations as indicated at 55 in FIG. 2. This synchronizing operation is not illustrated in the simplified diagram of FIG. 1, but this operation is detailed below in reference to the operation of the computer illustrated in FIGS. 8A and 88. At the same time, the voltage comparator signal becomes effective to close simultaneously the switches SW9 and SW17 of the discharge circuits of the reference channel integrator and the information channel integrator to simultaneously partially discharge the integrators through their respective resistances R2 and R4 (which are equal to each other) until the integrated reference signal E14 discharges or returns to the value of the voltage comparator input signal E25 as indicated at 56 in FIG. 2; When this occurs, the voltage held and retained at their then DC voltage values;

As a result, the cyclic wave signals E1 and E2 were integrated over at least the desired predetermined time interval (53-54 in FIG. 2) which was corrected to eliminate unwanted variations in the voltage supply, and an integral number of cycles of the cyclic wave signals were integrated by extending the integration time interval (54-55 in FIG. 2). Both integrators integrated correctly (from 53 to 55 in FIG. 2) over a time interval which included an integral number of cycles of the reference signal input El. However, both integrated signals E14 and E38 had a magnitude error at position 55 in FIG. 2, they having been multiplied by the factor T(5354) T(54-55) T(5354) stants R2.C1 and R4.C2 are equal, both capacitors C1 and C2 discharged at the same rate, i.e., the ratio of E38 to E14 remained constant. In other words, both integrated signals E14 and E38 (at 55 in FIG. 2) were rnultipliedhetween 55 and T (53 '54 56 in FIG. 2) by the factor and are now correct. Accordingly, where the information signal E2 is a function of the reference signal E1, the computer of this invention will normalize the integrated information output signal E38 to a precise time interval and will provide an accurate time integration signal of the information Since the time consignal E2 for an integral number of cycles for such precise time interval.

FIG. 3 illustrates a simplified electrical network particularly suitable for computing cyclic wave trains, such as, for example, sinusoidal AC wave trains. Here, a source 60 of sinusoidal AC voltage is applied to one end of the primary 62 of a current transformer 61 having a secondary 63. A resistance R9 is connected across the secondary 63 and one end of the secondary 63 is grounded. The other end of the secondary 63 provides a reference signal E1 which is sinusoidal and is proportional to the AC current flow through the, primary winding 62, it being dependent upon the turns ratio of the transformer 61 and the value of the resistance R9 which may be constant for a desired scaling. The other end of the primary 62 is connected through an unknown impedance Z to ground. The unknown impedance Z may be substantially any electrical devicewhose power and vector components are to be measured and computed. The juncture of the transformer primary 62 and the impedance 2 produces an information signal E2 which is dependent upon the electrical characteristics of the impedance Z.

, tegrated reference and information signals E14 and E18 are 5 The computer diagrammatically illustrated in FIGS. 8A, 8B

may be associated with the network of FIG. 3 for computing the various power and vector components with respect to the impedance Z of FIG. 3, as for example, the voltage magnitude, the in phase component of the voltage, the quadrature component of the voltage, the impedance magnitude, the series resistance component of the impedance, the series reactance component of the impedance, the volt'ampere power (i.e., the vector or apparent power), the real power, the reactive power, the power factor, and the phase angle between the voltage and current.

Referring now to FIGS. 8A, 8B, which when laid side by side diagrammatically illustrate the preferred computer of this invention which includes a reference input tenninal for 1. providing a reference input signal Elwhich may be obtained from FIG. 3. It also includes an information signal input terminal for providing an information input signal E2 which may be obtained from FIG. 3. It further includes an external pulse input terminal for providing a pulse signal E3 for controlling the control circuitry of the computer. A variable pulse signal E4 may be provided by a variable pulse generator 37 and a signal E5 which is 90 out of phase with the reference input signal E1 may be provided by a 90 phase shift network 36.

I The computer further includes a reference channel processing device or synchronous d t s)! sa ke by de e line L". associated with the reference input signal E1 and an information channel processing device or synchronous detector, en-

closed by dotted lines 11, which is associated with the information input signal E2. In addition, the computer'includes a reference channel computer or integrator, enclosed by dotted lines 12, and an information channel computer or integrator, enclosed by dotted lines 13. The computer further includes a timing and control system, enclosed by dotted lines 14.

Switches SW1, SW2, SW3 and SW4 are multiple position manual switches which may be individually manually operated or they may be ganged, as desired, switch SW1 having two positions, switch SW2 having three positions, switch SW3 having three positions and switch SW4 having three positions, the positions of the switches being indicated. The computer also includes switches SW5 through SW17. These-switches are single pole single throw switches which may be electromechanical, such as relays and the like, or solid state such as transistor choppers and the like. For purposes of description, it is assumed that a positive voltage applied to the controP input causes the switches to close (i.e., in & out terminals shorted) and that a-negative voltage causes the switches to open (i.e., in & out terminals open). The reference channel integrator 12 and the information channel integrator 13 respectively include

operational amplifiers

15 and 16 which have low drift and both voltage and current gains of l0 or greater such that for all practical purposes they may be considered infinite. The operational amplifiers l5 and 16 have like operating and electrical characteristics. They also respectively include resistance R1 and capacitor C1 and resistance R3 and capacitor C2, the resistances R1 and R3 being equal and the capacitors C1 and C2 being equal. The control system 14 includes a pair of flipflops l7 and 18 which include a bistable circuit with two inputs. A pulse present at the on" input causes the output to assume the on condition which remains until a pulse present at the o input causes the output to assume the ofi condition. Forpurposes of discussion a positive output represents on, a negative output represents off. Flip-flops l7 and 18 require positive going pulses at their inputs to cause operation, negative pulses being inefi'ecfive in causing operation.

The control system 14 further includes

differentiators

19, 20 and 21 whose outputs are a pulse corresponding in polarity and time to the transitions of input square waves applied thereto. The computer further includes

inverters

22, 23, 24, 25, 26 and 27 which are linear amplifiers with a gain of -l (i.e., a phase inverter). The reference channel detector and the information channel detector respectively include

adders

28 and 29. Each of these adders includes a circuit which provides an output proportional to the sum of its input signals and which also provides for isolation of the input signals. For purposes of discussion the gain in the adders is assumed to be +1.

Adjustable gain amplifiers

30 and 31 are associated respectively with the reference channel detector and they constitute adjustable gain DC amplifiers with outputs linearly related to their inputs. The outputs are equal to K times the inpus. K is the gain and may be positive or negative with a value determined by the desired scaling in the computer. The upper cutofi frequency should be high enough to allow a minimum of phase and gain variation at the highest frequency of. interest,

, for example, 500 KHz.

Two squaring

amplifiers

32 and 33 are also provided. These may comprise an overdriven amplifier or a Schrnitt trigger or the like whose output is some fixed positive value for an input more positive than (v) and some fixed negative value for an input more negative than (v), where (v) is some value which is for all values of input less than'the reference input. The

reference input is E25 which is provided by a reference input terminal B. This reference input E25 is normally a fixed negati'tie voltage.

The 90 phase shift network 36 referred to above provides an output signal E which is shifted 90 in phase to the input signal E1. The variable repetition rate pulse generator 37 referred to above produces a variable repetition rate pulse E4 arid may be manually or otherwise controlled.

{The computer also includes a gated peak detector 38 which may be typical peak detector whose output E40 is proportidnal to the peak amplitude of the input signal El without consideration, but, however, the output is prevented from changing except during the time that the gate input is positive. A detector whose output is proportional to the RMS or average value of the input signal El might also be used. Associated with the gated peak detector 38 is a multiplier-divider 39"which is an analogue compu ftiln g device whose output B41 is :equal to a constant times I The multiplier-di- E40 vider 39 may be like that illustrated in FIG. 15. The computer further includes a V bias terminal and an information output signal terminal A.

The various computations which may be made by the computer of FIGS. 8A, 8B, forexample from the network of FIGS. 3, inay be set up by manipulation of the manual switches SW1 to SW4. The following tabulation sets forth the switch positiohs and the connections made thereby and the formulae for such computations. In the formulae, A is the output signal E38; B is 1 for a fixed comparator reference voltage E25, but may have any value when externally varied; K is a constant, determined by the desired scaling required and it may be positive or negative; E1 is the reference input signal used for amplitude, phase,,frequency or timing control; E2 is the infonnatioii signal input which is a function of E1 in amplitude, phase oizfrequency; I is the phase angle between E1 and E2; and D is a constant and equals 90 for descriptive purposes.

(.1) V. (voltage magnitude) A=KBE2 SW1-1; SW2-3 (132-33); SW3-2 (E231); SW4-2 (E15-30).

(2) V cos 5 (in phase component of V) A=KBE2 cos. SW1-1; SW2-1 (El-33); SW3-2 (E2-31); SW4-2 (E15-30).

('3) V sin (quadrature component of V) A=KBE2 sin SW1-1; SW2-2 (E5-33); SW3=2 (E2-31); SW4-2 (E15-30). E2

(4) Z (impedance magnitude) A=KB E SW1-1;

SW2-3 (E2-33); SW3-2 (E2-31); SW4-1 (El-30). (5) R (series resistance component of Z) A=KB -2 SW1-1; SW2-1 (El-33); SW3-2 (E2-31); SW4-1 (El-30).

(6) X (series reactance component of Z) A=KB SW1-1; SW2-2 (E5-33); SW3-2 (E2-31);

sw4-1 (El-30).

Several specific examples of the operation of the preferred form of the computer of this invention are set forth hereafter. First, reference is made to FIGS. 8A, 8B and to the curves of FIGS. 9 and 10 where the switches SW1 through SW4 are set for the computation of the series resistance component of the impedance Z of FIG. 3, computation (5) above, switch SW1 being in position 1, switch SW2 being in position 1, switch SW3 being in position 2, and switch SW4 being in position 1. Reference signal input E1 is therefore connected to the adjustable gain amplifier 30 and to both squaring

amplifiers

32 and 33, and information signal input E2 is connected to adjustable gain amplifier 31. Reference signal input E1 (FIG. 9)-

is assumed to be a sinusoidal sine wave and information signal input E2 (FIG. 9) to bea sinusoidal sine wave lagging reference signal E1 by a phase angle 1 of Signal E5 (which is not used in this computation) is a sinusoidal sine wave leading the reference signal E1 by a phase angle D of 90.

With both signal inputs El and E2 applied, a trigger pulse E3 (FIG. 9) is applied at 51 (or E4 if switch SW1 is in position 2) and it operates the multivibrator 34 to its on state for producing a positive signal E14 (FIG. 9) for a time interval which is longer than a half-cycle of the reference input signal E1. This signal E18 closes switches SW8 and SW16 over such time interval to completely discharge the capacitors C1 and C2 to zero for causing any previous integrated reference signal output E14 and informafion signal output E38 to be discharged to and return to zero. By the end of such time interval the capacitors C1 and C2 are completely discharged and at the end of such time interval at 52 controlled by the multivibrator 34 signal E18 returns to its off state (negative output) and causes switches SW8 and SW16 to open. Also, at the negative going transition of E18, inverter 24 and differentiator 20 cause a positive pulse to be generated at 1519 which in turn causes flip-flop 17 to change to its on state to provide a positive signal E20 for closing switch SW1 1.

The reference input signal E1 is amplified by the'adjustable gain amplifier 30 and im output E7 is applied to the input of switch SW5 and to the inverter 22 and the output E8 of the inverter 22 is applied to the input of switch SW6. With switch SW4 in position 1, as it here is, signal E7 is the same as signal E1 except for amplitude. (With switch SW4 in position 2, signal E7 is the same as signal E15 except for amplitude). Signal E8 to the input of switch SW6 is the same as signal E7 except that it has an 1 80 phase inversion.

Reference signal input E1 is also applied to the squaring amplifier 32 and to squaring amplifier 33 when switch SW2 is in position 1 and the outputs E15 and E28 therefrom are square wave signals and are positive when signal input E1 is positive and negative when signal E1 is negative (FIG. 9). Signal E15 is applied directly to the control terminal of switch SW5 and to inverter 23. Output signal E16 of inverter 23 is a square wave signal like signal E15 but out of phase therewith and is applied directly to the control terminal of switch SW6. The output signal E28 is a square wave signal and is the same as signal E15 and it is applied directly to the conn'ol terminal of switch SW13 and to the inverter 25. The output signal E29 from the inverter 29 is also a square wave signal which is 180 out of phase with respect to signal E28 and it is applied to the control terminal of switch SW14.

Signal E9 from switch SW5 is identical to signal E7 during the time that square wave signal E15 is positive and is zero when signal E15 is negative. Signal E10 from switch SW6 is identical to signal E8 during the time that square wave signal E16 is positive and iszero when signal E16 is negative. Signals signal E2 exceptforamplitude. Signal E32 to switch SW14 is is a square wave signal which is the same in phase as square R wave signal E15, signal E28 being applied to inverter 25 and to the control terminal of switch SW13, signal E29 being the same as signal E28 except that it has an 180 phase inversion. Signal E33 (FIG. from switch SW13 is identical to signal E31 during the time that square wave signal B28 is positive and is zero when signal E28 is negative. Signal E34 (FIG.

. 10) from switch SW14 is identical to signal E32 during the time that square wave signal E29 is positive and is zero when signal E29 is negative. Signals E33 and E34 are applied to the adder 29 and the output signal E35 (FIG. 10) from the adder is the sum of signals E33 and E34, signal E35 being applied to switch SW15.

Square wave signal E is also applied to difl'erentiator 19 whose output signal E17 (FIG. 9) is positive and negative pulses at the respective transitions of signal E15. As expressed on toproduce a positive signal pulse E for closing switch SW11. The first positive pulse E17, while switch SW11 is so closed, is transmitted through switch SW11 to provide a positive pulse E22 for switching flip-flop 18 to its on state. The output signal E23 I from flip-flop 18 is differentiated by differentiator 21 to provide a positive pulse signal E24 for turning ofi flip-flop 17 which causes switch SW1] to switch off and thereby prevent flip-flop 18 fromv again being turned on until a another trigger pulse E3 or E4 has occurred. The output signal 1523 from flip-flop 18 also simultaneously closes switches SW7 and SW15 for applying the processed signals E11 and E35 to the reference channel and

information channel integrators

12 and 13 as indicated at E12 and E36 in FIGS. 9 and 10.

{The referencechanhel integrator 12 includes a resistance R1 receiving signal E12 and providing signal E13 on one side or; capacitor C1 and an operational amplifier 15 which in produce a time integrated signal E14 on the other side th reof. Likewise, the information channel integrator includes a resistance R3 receiving signal E36 and providing signal E37 onfone side of a capacitor C2 and an operational amplifier 16 which in turn produce a time integrated signal E38 on the other side thereof. The resistances R1 and R3 are equal, the

capacitances C1 and C2 are equal, and the electrical characteristics of the

operational amplifiers

15 and 16 are equal. As expressed above, switches SW8 and SW16 are for the purpose of co rnpletely discharging the integrators when closed, also,

resistance R2 and switch SW9 and resistance R4 and switch SW17 are for the purpose of partially discharging the integratorts, the resistances R2 and R4 being equal.

When switch SW7 is closed as aforesaid, the integration of signal B12 is started at 53 and the integration time is controlled by the time constant Rl C1. When the integrated output, signal E14 (FIG. 9) becomes equal at 54 to the comparatorjf voltage input E (FIG. 9), the voltage comparator 35 responding to such signals changes its output signal E26 (FIG. 9)Ilfrom negative to positive. output signal E26 thus goes positive, switch SW10 is closed. The next positive going pulse E17 from the differentiator 19 is then transmitted through SW10 at E21 to cause flip-flop 18 to turn off and change signal E23 (FIG. 9) from positive to negative, at which time 55, switches SW7 and SW15 are sirriiiltaneously opened to stop the integration. During the timeinterval that flip-flop 18 was on between 53 and 55 the infer-mation integrator 13 was integrating signal E36 with an integration time constant R3 C2 for information signal E38.

At this time 55 both integrators have integrated their respective input signals E12 and E36 for a time of T(5354)+ T( 54-5S). T(5354) is the designed integrating time intervalgstarting at the first positive going transition of reference producing the integrated 1 signal El and ending at the instant that integrated reference E14 equalled comparator reference voltage signal E25.

When the voltage comparator Both integrators continued to integrate, however, for an additional time interval T(54-55) which is the time required for the first positive going transition of reference signal E1 after T(5354). Both integrators have integrated correctly over time periods which are an integral number of cycles of the goes negative at 55 asdescribed above, inverter 27 produces a positive signal which is applied to the control terminal of switch SW12 to close the same. Switch SW12 thereupon applies the positive signal E26 from the voltage comparator 35 to the negative bias signal E27 which overrides the same and causes the same to become positive for closing switches SW9 and SW17. Closure of switches SW9 and SW17 partially discharges the

integrators

12 and 13 through resistances R2 and R4 respectively. The time constants R2 C1 and R4 C2 are equal and, therefore,,both capacitors C1 and C2 discharge at the same rate, i.e., the ratio of integrated signals E38 and E14 remains constant.

When the integrated reference signal E14 is discharged to and becomes greater than the comparator reference voltage signal input E25, the voltage comparator signal E26 becomes negative which in turn causes signal E27 to again become negative at 56 for opening switches SW9 and SW17 to stop the partial discharge of capacitors Cl and C2 at 56. Since both of the integrated .output signals E14 and E38 have been discharged until signal E14'becornes equal to thecomparator voltage input signal E25, then both signalsli14 and E38 have T (53-54) been multrphed by the factor MW QQQLIZ 5 7 and are now correct. Accordingly, where the information signal E2 is a function of the reference signal E1, the integrated information output signal E38 is normalized to a precise time interval (53-54) and will provide an accurate time integration signal of the information signal E2 for an integral number of cycles thereof and regardless of voltage variations afiecting input signals El and E2.

Since it was assumed above that the information signal input E2 lagged the reference signal input E1 by the corrected information signal E36 (FIG. 10) applied to the information channel integrator 13 was symmetrical about zero and, hence, the integrated signal E38. (FIG. 10) remained at zero, indicating that R, the series resistance component of the impedance ZofFIG.3, (A=KB E25? When the computer afiiianfiinafi is set if; for computing X, computation (6) above, the series reactance component of z of FIG. 3 (A=KB switch SW1 is in'position 1, switchSW2 is in position 2 to connect the 90 phase shift network to the squaring amplifier 33,

) was zero.

switch SW3 is in position 2 to connect information signal E2 i to the adjustable gain amplifier 31, and switch SW4 is in position 1 to connect reference signal E1 to the adjustable gain amplifier 30. Under these conditions the various signals pertaining to the reference channel are the same as those discussed above and illustrated in FIG. 9. FIG. 11 represents the significant signals for the information channel for these conditions. The square wave signal E28 from the squaring am- E34 and E33 are added by adder 29 to provide signal E35 and to provide a signal E36 to be integrated by the information channel integrator 13. The integrated information signal E38 following integration shows a substantial series reactance component of the impedance Z.

' When the computer is set up for computing 2, computation (4) above, the impedance magnitude of Z of FIG. 3

E2 (A-Jtb E1 switch SW1 is in position 1, switch SW2 is in position 3 to connect infonnation signal E2 to the squaring amplifier 33, switch SW3 is in position 2 to connect information signal E2 to the adjustable gain amplifier 31, and switch SW4 is in position 1 to connect the reference signal E1 to the adjustable gain amplifier 30. Under these conditions, the various signals pertaining to the reference channel are the same as those discussed above and illustrated in FIG. 9. FIG. 12 represents the significant signals for the information channel for these conditions. The square wave signal E28 from the squaring amplifier 33 is in phase with the information signal E2 and lags signal E15 by 90 and it controls switches SW13 and SW14. When signal E28 is negative, signal B33 is zero and when signal E28 is positive, signal E33 corresponds to the positive going portion of information signal E2. When signal E28 is negative, signal E34 corresponds to the inversion of negative going portion of information signal E2 and when signal E28 is positive, signal E34 is zero. These signals E33 and E34 are added by adder 29 to provide a signal E36 to be integrated by the information channel integrator 13. The integrated information signal E38 following integration shows a substantial impedance magnitude of the impedance Z.

When the computer is set up for computing cos D, computation above, the power factor, with respect to the impedance Z of FIG. 3 (A=KB cos D), switch SW1 is in position 1, switch SW2 is in position 3 for connecting information input signal E2 to the squaring amplifier 33, switch SW3 is in position 3 for connecting reference input sigial E1 to the adjustable gain amplifier 31, and switch SW4 is in position 1 for connecting the reference input signal E1 to the adjustable gain amplifier 31, and switch SW4 is in position 1 for connecting the reference input signal E1 to the adjustable gain amplifier 30. Under these conditions the various signals pertaining to the reference channel are the same as those discussed above and illustrated in FIG. 9. FIG. 13 represents the sigrificant signals for the information channel for these conditions. Switches SW13 and SW14 are controlled by the square wave signal E28 from squaring amplifier 33, like that of FIG. 12, which is in phase with the information signal input E2. When signal E28 is negative, signal E33 is zero and when signal E28 is positive, signal E33 corresponds to the reference signal El. When signal E28 is negative, signal E34 corresponds to the inversion of the reference signal E1 and when signal B28 is positive, signal E34 is zero. These signals E33 and E34 are added by adder 29 to provide signal E35 to provide signal E36 to be integrated by the information channel integrator 13. The processed infonnation signal E36 is symmetrical about zero and, hence, the integrated signal E38 remains at zero, indicat' ing that the power factor (cos 1 is zero.

When the computer is set up for computing 51 computation (ll) above, the phase angle between the voltage and current, with respect to the impedance Z to FIG. 3 (A=KB (D+ l switch SW1 is in position 1, switch SW2 is in position 3 to connect the information signal E2 to the squaring amplifier 33, switch SW3 is in position 1 to connect the squaring amplifier 32 through E to the adjustable gain amplifier 31, and switch SW4 is in position 2 to connect the squaring amplifier 32 through E15 to the adjustable gain amplifier 30. FIG. 14 represents the significant signals pertaining to the reference and information channels for these conditions. Signal E7 from the adjustable gain amplifier 30 is a square wave signal which is the same as square wave signal E15 except for amplitude, and signal E8 from the inverter 22 is the same as signal E7 except for an 180 phase inversion. Signals E9 and E10 (FIG.

14) are added by adder 28 to produce signal E11 which is gated at E12 during the positive pulse E23 to produce the integrated reference signal E14. Square wave signal E28 from squaring amplifier 33 is in phase with the information signal input E2. Signal E31 from the adjustable gain amplifier-31 is a square wave signal which is the same as signal E15 except for amplitude, and signal E32 from inverter 26 is the same as signal E31 except for an 180 phase inversion. Signals E33 and E34 are added by adder 29 to produce signal E35 which is gated at E36 during the positive pulse E23 to produce the iii-- tegrated information signal E38. Since signal E36 is symmetrical about zero, the integration product is zero which indicates that I the phase angle, is the assumption made in connection with the above computations.

Several specific examples, utilizing the curves of FIGS. 9 to 14, for performing the computations of items (4), (5), (6), l0) and l 1) of the above tabulation have been considered in detail for providing a thorough understanding of this invention. It is not considered necessary to further consider in detail the other items of said tabulation other than to note the switch positions and connections made thereby as set forth in the tabulation, the versatility of the computer of this invention being readily apparent from the foregoing description.

If signals E20 from the flip-flop 17 and E26 from the voltage comparator 35 are differentiated and connected to replace the signals E21 and E22 respectively to the flip-flop 18 (differentiator 19 and switches SW10 and SW11 being eliminated) the computer will accept and compute DC or pulse input signals.

The network of FIG. 4 is like that of FIG. 3 except that the signal outputs E1 and E2 thereof are reversed for connecting the same to the computer of FIGS. 8A, 8B. As a result the computer computes the Y or admittance components of the unknown admittance Y under test and, also, current components using voltage as a phase reference by suitable manipulation of the switches SW1 and SW4. The following is a tabulation including the switch positions and connections and formulae for such computations.

15 Y (admittance magnitude) A=KB SW1-1;

SW2-3 (E233); SW32 (E231); SW41 (E130).

(16) G (parallel resistance component of Y) A=KB E2 cos E1 SW1-4; SW2-1 (El-33); SW3-2 122-31 SW4-1 (E130).

(17 B (parallel reactive component of Y) A=KB SW1-1; SW2-2 (E5-33) SW3-2 (E2-31); SW4-l (El-30).

(18) Cos (power factor) A=KB cos SW1-1; SW2-3 (E2-33); SW3-3 (EL-31); SW4-1 (El-30).

(19) (phase angle between V & I) A=KB (D+) SW11; SW2-3 (E2-33); SW3-1 (E15-31); SW4-2 (E15-30) In the light of the foregoing explanations, it is not believed necessary to describe in more detail the operation of the computer of FIGS. 8A, 8B in conjunction with the network of FIG. 4.

FIG. 5 illustrates a network for direct measurement of the transfer functions of a device under test 64, labeled D.U.T., signal E1 being the reference signal and signal E2 being the information signal, and signals E1 and E2 being applied to the computer of FIGS. 8A, 8B. The computations here involved are based on the formula A: K1 K2 E2 and E1 are functions of frequency, K1 is the nominal loss or gain of the device 64 under test, K2 is the scaling factor of where tegrated information signal B38 is a measure of the frequency response. To compute the phase response where the phase angle I is a function of frequency, switch SW1 is in position 1, switch SW2 isin position 3 to connect E2 to 33, switch SW3 is in'position l to connect E to 31, and switch SW4 is in position 2 to connect E15 to 30. The integrated information signal B38 is a measure of the phase angle D.

1 FIG. 6 illustrates a system for making comparison measurements of transfer functions, such as, comparison measurements of transfer functions, such as, comparison measurements between standard and test acoustic receivers or other transducers. Here, an: AC voltage source 60 operates an acoustic transmitter 65 for transmitting acoustic waves to a standard acoustic receiver 67 and an unknown or test acoustic receiver 68. The standard receiver 67. provides a reference 7 signal E1 and the test receiver 68 provides an information signal E2, the signals El and E2 being applied to the computer of FIGS. 8A, 8B. The system also preferably includes a potentiometer 69 for adjusting the comparator voltage signal E25 applied to the terminal B of FIG. 8B.

The computation for the relative frequency response of the 7' where E2 and E1 are functions offrequency, K1 is the nominal scaling factor between E2 and E1, K2 is the scaling factor of the computer including the comparator voltage B times a constant, B is a fixed voltage which may be externally controlled, and A is the information-output signal 38 of the computer. To compute the relative frequency response, switch SW1 is in position 1, switch SW2 is in position 3 to connect E2to 33, switch SW3 isin position 2 to connect E2 to 31 and switch SW4 is in position 1 to connect E1 to 30. The integrated information signal E38 provides a measurement of the relative frequency response.

The computation of the absolute frequency response of the test receiver 68, provided the acoustic intensity of the waves 66'js maintained constant at both

receivers

67 and 68, involves the formula A=K1 K2 E2, where E2 is a function of frequency, and 13 included in K2 is fixed voltage. Here, switch SW1 is in positionl, switch SW2 is in position 3 to connect E2 to33, switch SW3 is in position 3 to connect 39 to 30. The integrated information signal E38 provides a measurement of the absolute frequency response. Wherethe-intensity of the acoustic waves 66 cannot be maintained constant at the

receivers

67 and 68, the comparator reference voltage source B (E25) can be varied, as by the potentiometer 69, proportionally to the known response of the standard receiver 68. A curve follower or similar device may be used for automatic adjustment of the voltage B(E25 or it may be adjusted manually in discrete steps so that voltage B(E25) is made to correspond to the normalized reference signal input E1, i.e., to the known response of a standard receiver.

FIG. 7 discloses a network for power measurements of a device under test wherein the sine wave signals are of high distortion and/or have high harmonic components. Here, a source of alternating current 60 is connected to one end of the primary 62 of a current transformer 61 having a secondary 63, the other end of the primary 62 being connected through the device under test 70, labeled D.U.T.', to ground. The current source 60 directly provides the reference signal input E1 which is utilized only for timing purposes. A resistance R9 is connected across the secondary 63 of the transformer 61, one end of the resistance R9 being connected to ground and the other end thereof being connected to the input of an amplifier 71Q'l'he output of the amplifier 71 is connected to ground through a winding 72 of a Hall effect device 73. Reference signal E1 .is applied to the Hall effect device 73, labeled H. E.D., which also is grounded. The signal outputs of the

Hall receivers

67 and 68 is based on the formula A: K1 K2 effect device are connected to the inputs of a differential amplifier 74 and the output of the differential amplifier 74 provides information signal E2. Reference and information signals El and E2 are applied to the computer of FIGS. 8A, 8B.

Signal E2==CVI (in instantaneous values where v is the signal voltage and I is the current in the primary circuit, and where C is a scaling factor and is constant. Thus, in computing the power measurement A=K1-. J F2 dt. other words, A=KB times the integra tli1e instantaneous power over the time interval 0 to T, ",or A=KB times the average power over interval 0 to T. In this computation switch SW1 is in position 1, switch SW2 is in position 3 to connect E2 to33, switch SW3. is in position2 to connect E2 to El; and- 1 switch SW4 is in position 2 to connect E15 to 30. The integrated reference signal E38 or A following the integration is a measure of the average instantaneous power over the integration interval. If the squaring amplifier 33 is disabledsu ch that its output E28 is either on or off, the average power is measured.

By adding additional information channels including processing device 11 and integrating device 13, as illustrated in broken linesin FlGS. 8A and 8B, :along with appropriate control connections thereto, computations of a multiplicity of functions of the information signal E2 may be simultaneously performed. Also, by varying the value of the comparator volt age input signal Ell multiplication and division computations may also be provided.

,fThe computer shown in block diagram in FIGS. 8A, 8B is Pai'ticularly adap b for computing the Parameters trical or electronic networks and electromechanical devices and systems in the audio frequency range from 10.0 Hz. to 500 Hz., because of the commercial importance of parameter measurements in this frequency range and the readily available electronic circuit building blocks for this frequency range from manufactures which are more or less off the shelf. In addition to measurement of steady DC or pulses or slowly varying AC by making the above-described revisions to the computer, measurements in the megacycle frequency range and above may also be made. in accordance with this invention, but this would requiremore sophisticated electronic circuit building blocks which are not normally ofl the shelf" items.

FIG. 15 diagrammatically illustrates another form of a computer providing a simple approach of a multiplier-divider suitable for use where two inputs E40 and F are limited in range and have the same polarity. The third input E15 may have any value or polarity or maybe cy clie. 'l 'he mathematical 0 tion erforrned is I C pera p s C E4 tive when signal B84 is greater than signal E and negative when signal B84 is less than signal E85. Switches SW81 and SW82 are closed (shortcircuit) when signal E86 is positive and are open (open circuit) when signal E86 is negative. One end of a resistance R15 is connected to the signal ,input,.E40 and the other end thereof is connected to ground through capacitor C11, to ground through resistance R16 and switch SW81, and to the voltage comparator 83 at E84. One endof a resistance Rl7 is connected to the signal input E15 and the other end thereof is connected to ground through capacitor C12, to ground through resistance R18 and switch SW82, and to the signal output terminal C at E41. The ratio of resistance R15 to resistance R16 is equal to the ratio of resistance R17 to resistance R18 and the product (R15) (C11) is equal to the product (R17 (C12). Signal E40 is always greater than signal E85. Signals E40 and E85 are DC or slowly varying and only for descriptive purposes herein are always positive. The ratio of resistance R15 to resistance R16 is established such that at steady state with switch SW81 closed signal E84 is always less than signal E85 with signal E40 at its designed maximum value.

The operation of the computer of FIG. 15 is illustrated by the curves of FIG. 16. For providing a division computation signal E85 is fixed at a desired value. Switches SW81 and SW82 have previously been closed to discharge the capacitors C11 and C 12 to bring the signals E84 and E41 to zero and to make signal E86 negative. The switches SW81 and SW82 were then opened and were held open by the negative signal E86. At time 90 signals E40 and E15 are simultaneously applied and capacitor C11 charges toward signal E40 through resistance R15 (signal E84) and capacitor C12 charges toward signal E15 through resistance R17 (signal E41). When signal E84 becomes greater than signal E85 at time 91, the voltage comparator 83 operates to make its output signal E86 positive. Note that a small delay in the operation of the voltage comparator 83 has been shown to clarify the operation of the computer. When the voltage comparator output signal E86 thus becomes positive, the switches SW81 and SW82 are simultaneously closed to simultaneously discharge the capacitors C11 and C12 through resistances R16 and R18, respectively, (signals E84 and E41). Whensignal E84 becomes less than signal E85 at time 92, the voltage comparator 83 causes signal E86 to again become negative to again cause

switches

81 and 82 simultaneously to open, whereupon capacitors C11 and C12 begin again to charge. The discharge and charge cycles repeat continuously thereafter. The average value of the output C (sign al E4 1) therefore has a value of (E15) (F) Em, where F 18 fixed. This cor responds to division.

Alternately, signal E40 may be fixed with F (signal E85) variable. Here, the avergg valueof theoutput C (signal E41) hasavalue 01' C average: (E15) (Eg wlfiri'eilll is fixed. This corresponds to multiplication. By simultaneously or progressively varying signal E40 and signal E85 (F) both multiplication and division may be accomplished.

The input signal E40 may be considered a reference signal and the input signal E15 may be considered an information signal, both of which are time integrated until the integrated reference signal E84 reaches the comparator voltage signal E85, with the result that the time integrated information signal represents the multiplication or division computation.

If signal E15 is a cyclic wave signal, such as a square wave signal illustrated in FIG. 17, and the time constants are adjusted to be less than the half-cycle periods of signal E15, such a cyclic wave signal may be multiplied or divided as shown in FIG. 17, curve E15 being the square wave input signal and curve E41 being the C average output signal for each halfcycle of the input signal. This particular arrangement using the square wave input signal E15 is admirably suitable for the multiplier-divider 39 of the computer of FIG. 8A. There, the voltage comparator input signal F(signal E85)-is an internal adjustment.

By adding additional information channels as indicated by block 95 in FIG. 15 with appropriate control connections thereto, multiplication and division of other additional functions may be simultaneously performed. While for purposes of illustration several forms of this invention have been disclosed, other forms thereof may become apparent to those skilled in the art upon reference to this disclosure and, therefore, this invention is to be limited only by the scope of the appended claims.

I claim:

1. A computing method comprising the steps of providing a reference cyclic wave signal having amplitude, phase and frequency components, providing an information cyclic wave signal having amplitude, phase and frequency components which are functions of those of the reference cyclic wave signal, processing said cyclic wave signals to provide processed reference and infonnation signals, simultaneously starting integration with respect to time of both of said processed signals at the start of a half-cycle of the reference cyclic wave signal for producing time integrated reference and information signals, simultaneously continuing such time integration of said processed signals until the time integ'ated reference signal reaches at least a predetermined value, and then at the start of an ensuing half-cycle of the reference cyclic wave signal simultaneously discontinuing such integrations of said processed signals and simultaneously proportionately decreasing the values of the time integrated reference and information signals until the time integrated reference signal returns to said predetermined value, whereby the time integrated information signal indicates the time integal of the processed information signal over an integral number of half-cycles of the reference cyclic wave signal.

2. A computing method as set forth in claim 1 wherein the simultaneous starting of the integrations of both of said processed signals take place at the start of a first half-cycle of the reference cyclic wave signal, and wherein the simultaneous discontinuation of the integrations of the processed signals and the simultaneous proportionate decrease of the time integrated reference and information signals take place at the start of the first half-cycle of the reference cyclic wave signal after the time integrated reference signal reaches said predetermined value, wherebythe time Etegra ted information signal indicates the time integral of the processed information signal over an integral number of full cycles of the reference cyclic wave signal.

3. A computing method as defined in claim 1 wherein the processing of the cyclic wave signals comprises the steps of inverting botln of said cyclic wave signals during the second-half cycles to provide the processed reference and information signals.

4. A computing method as defined in claim 2 wherein the processing of the cyclic wave sigials comprises the steps of inverting both of said cyclic wave signals during the second-half cycles to provide the processed reference and information signals.

5. A computer comprising means for providing a reference signal, means for providing a comparator voltage input signal of predetermined value, a first computer device associated with the reference signal for computing the same and providing a computed reference signal corresponding to the computation, a second computer device associated with the informa tion signal for computing the same and providing a computed information signal corresponding to the computation, the computing characteristics of the second computer device corresponding to those of the first computer device, switch means associated with the first and second computer devices and operable to a first condition for causing simultaneous computations of said reference and information signals and to a second condition for simultaneously discontinuing said computations, control means including means for operating said switch means to said first condition for simultaneously starting said simultaneous computations of said reference and information signals, said control means including a voltage comparator associated with said comparator voltage input signal and the computed reference signal of the first computer device and responsive to the computed reference signal of the first computer device reaching the comparator voltage input signal for controlling the operation of said switch means to said second condition to terminate simultaneously the computations by both said first and second computer devices, the computed infonnation signal of the second computer device indicating the desired computation of the infonnation signal computed thereby.

6. A computer device as defined in claim 5 and including means for adjusting the value of the reference signal or the value of the comparator voltage input signal for dividing or multiplying the computed infonnation signal.

7. A computer as defined in claim wherein said first and second computer devices are time integrators for providing time integrations of the reference and information signals.

8. A computer as defined in claim 6 wherein said first and second computer devices are time integrators for providing time integrations of the reference and information signals.

9. A computer as defined in claim 5 wherein said first and second computer devices are time integrators for providing time integrations of the reference and information signals for producing time integrated reference and information signals, wherein said comparator voltage input signal which is reached by the time integrated reference signal determines the desired time interval of said time integrations, and wherein the computed information signal indicates the time integral of the information signal over said desired time interval.

10. A computer as defined in claim 5 wherein said first and second computer devices are time integrators for providing time integrations of the reference and information signals wherein the time integration interval is determined by the values of the reference signal and the comparator voltage input signal which is reached by the time integrated reference signal, and wherein the computed information signal indicates the time integral of the information signal over such time interval.

11. A computer as defined in claim 10 and including means for adjusting the value of the reference signal or the value of the comparator voltage input signal for dividing or multiplying the time integrated information signal.

12. A computer comprising means for providing a reference cyclic wave signal having amplitude, phase and frequency components, means for providing an information cyclic wave signal having amplitude, phase and frequency components which are functions of those of the reference cyclic wave signal, a first processing device associated with the reference signal and providing a processed reference signal, a second processing device associated with the information signal and providing a processed information signal, a first integrator associated with the processed reference signal for integrating the same over a time interval for providing a time integrated DC reference signal, a second integrator associated with the p ocessed information signal for integrating the same over a time interval for providing a time integrated DC information signal, the integrating characteristics of said second integrator corresponding to those of the first integrator, means for providing a DC comparator voltage input signal of predetermined value, switch means operable when closed for connecting the processed reference and information signals respectively to the first and second integrators for simultaneous time integrations of said processed signals, control means including means responsive to the start of a half-cycle of the reference cyclic wave signal for closing said switch means for simultaneously starting said simultaneous time integrations of said processed reference and information signals, said control means including a voltage comparator associated with said DC voltage comparator input signal and the time integrated reference signal of the first integrator and responsive to the integrated DC reference signal reaching the DC comparator voltage input signal value for producing a control signal but allowing continued integration by both the first and second integrators, a corresponding discharge circuit for each of said first and second integrators, said control means including means responsive to the start of a half-cycle of the reference cyclic wave signal following production of said control signal for simultaneously opening said switch means to terminate simultaneously the time integrations by both of said first and second integrators and for simultaneously closing said corresponding discharge circuits for simultaneously partially discharging both of said integrators therethrough, said control means including means responsive to elimination of said control signal when said control signal is eliminated by the partial discharge of the integrated DC reference signal of said first integrator to the DC comparator voltage: signal input value for simultaneously opening said corresponding discharge circuits to prevent further discharging of both of said first and second integrators therethrough, the time integrated DC information signal of the second integrator indicating the time integral of the processed information signal over an integral number of half-cycles of the reference cyclic wave signal.

13. A computer as defined in claim 112 wherein said means of said control means which closes said switch means is responsive to the start of a first half-cycle of the reference cyclic wave signal, and wherein said means of said control means which opens said switch means and closes said corresiamiig discharge r neansis responsive to the start of the next ensuing first half-cycle of the reference cyclic wave signal following production of said control signal, whereby the time integrated information signal indicates the time integral of the processed information signal over an integral number of full cycles of the reference cyclic wave signal.

14. A computer as defined in claim 12 wherein said first and second processing devices include means for detecting the cyclic wave signals and inverting the second half-cycles to provide the processed signals.

15. A computer as defined in claim 12 wherein said first and second processing devices include means for detecting the cyclic wave signals and inverting the second half-cycles to provide the processed signals.

16. A computer as defined in claim 5 wherein said means for providing the reference signal and the related information signal comprise a voltage source, a circuit powered by the voltage source and including a device under test, means coupledto the circuit and responsive to the volta e source for providing the reference signal and means coup ed to the eucuit and responsive to the device under test for providing the related information signal.

17. A computer as defined in claim 12 wherein said means for providing the reference signal and the related information signal comprise a voltage source, a circuit powered by the voltage source and including a device under test, means coupled to the circuit and responsive to the voltage source for providing the reference signal, and means coupled to the circuit and responsive to the device under test for providing the related information signal.

18. A computer as defined in claim 12 and including a source of energy, a standard transducer and a test transducer subjected to the energy produced by said source, said standard transducer producing the reference signal and said test transducer producing the related information signal.

19. A computer as defined in claim 12 and also including an adjustable gain amplifier and a squaring amplifier for each of the first and second processing devices, a phase shift device, and a plurality of switches for selectively interconnecting the reference signal, the information signal, the 90 phase shift device, and the squaring amplifier of the first processing device to the squaring amplifier of the second processing device and the adjustable gain amplifiers of the first and second processing devices for desired vector component computations.

20. A computer as defined in claim 12 and also including an adjustable gain amplifier and a squaring amplifier for each of the first and second processing devices, a 90 phase shift device, a multiplier-divider device, and a plurality of switches for selectively interconnecting the reference signal, the information signal, the 90 phase shift device, and the multiplier-divider device to the squaring amplifier of the second processing device and the adjustable gain amplifiers of the first and second processing devices for desired power computations.