US3544780A - Electronic multiplying apparatus and circuitry therefor - Google Patents

Electronic multiplying apparatus and circuitry therefor Download PDF

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Publication number
US3544780A
US3544780A US624877A US3544780DA US3544780A US 3544780 A US3544780 A US 3544780A US 624877 A US624877 A US 624877A US 3544780D A US3544780D A US 3544780DA US 3544780 A US3544780 A US 3544780A
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voltage
terminal
transistor
terminals
commutator
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US624877A
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English (en)
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Pierre Jorgensen
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Saint Gobain Techniques Nouvelles SA
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Saint Gobain Techniques Nouvelles SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E1/00—Devices for processing exclusively digital data
    • G06E1/02—Devices for processing exclusively digital data operating upon the order or content of the data handled
    • G06E1/04—Devices for processing exclusively digital data operating upon the order or content of the data handled for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/388—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4824—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices using signed-digit representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/16—Digital recording or reproducing using non self-clocking codes, i.e. the clock signals are either recorded in a separate clocking track or in a combination of several information tracks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • CI 235/ 194 base electrodes of two transistors for receiving a voltage 307/229 representative of B and an output terminal for delivering a [51] In, (I L063 1/16 voltage representative of said product; and said multiplier cir- [50] Field Search 235/194, cuit in combination with a two-phase control motor and with magnetic memory means.
  • the present invention relates to electrical apparatus and more particularly to solid state conduction control circuitry adapted, among other things, for use in electronic calculators and the like.
  • An object of the present invention is to provide a novel scalar multiplier circuit.
  • Another object is to provide novel solid state electronic circuitry adapted for producing the algebraic product of two quantities representable by electrical values.
  • a further object is to provide a novel electronic scalar multiplier for producing an algebraic product of two numbers in strict fashion when one of the numbers is quantified'according to two or three values, such as, for example, positive without value and negative and in approximate fashion for those quantifications of a higher order. 2
  • Still another object of the invention is to provide'a novel phase demodulator embodying multiplier circuitry of the" above character.
  • Still another object of the invention is to provide an electronic multiplier circuit of the above character in novel combination with a magnetic memory device.
  • the basic multiplier circuit contemplated by the invention comprises a device embodying two transistors or comparable conduction control means capable of deliveringon two output electrodes voltages representative of the positive and .negative of a number A if a voltage representing the number is applied to an input terminal of the device.
  • a commutator circuit Connected to said device is a commutator circuit having an output terminal, a control terminal for receiving a signal indicative of a number B and'two input terminals connected to the output terminals of said device.
  • the commutator circuitry is such that if B is positive, the commutator output is connected by a solid state switch to the commutator input electrode which receives a voltage representative of the number A, whereas if B is negative, the commutator output electrode is connected by a solid' state switch with the commutator input terminal thereof which receives a voltage signal representing the number --A. Finally, if B is without value, both input terminals of the commutator will be connected to each other and with the output terminal thereof.
  • the commutator output voltage V will be- It will be noted that the sign of the voltage V corresponds to the product of the signs of the input signal voltages A and B.
  • FIG. I is a circuit diagram illustrating one embodiment of the invention.
  • FIG. 2 is a duplicate of FIG. 1 wherein exemplary values of some of the components are indicated;
  • FIG. 3 is a circuit diagram showing a second embodiment
  • FIG. 4 is a diagram illustrating the combination of the apparatus of FIGS. 1 or 2 with a two-phase control motor
  • FIG. 5 is a graphic illustration of typical input and output voltages of apparatus embodying the invention.
  • FIG. 6 illustrates a phase demodulator embodying the circuitry ofFlG. l;
  • FIG. 7 is a diagrammatic plan view of a magnetic memory device
  • FIG. 8 is an end elevation view of the device of FIG. 7 looking in the direction of the arrow VIII;
  • FIG. .9 is adiagrammatic detail view of a recording track and a reading her head therefor;
  • FIGS. 10A, 10B, l0C, l0D,- 10E, 10F and. 10G are respectively graphic representations of voltage plotted against time of a'reference signal that can be taken from the reading head ofFIG. 9, a signal representing the positive state, the product of those ,two signals, a signal representing the No Value state, the product of that signal and the referencesignal, a signal representing the negative state and the product of that signal and the reference signal;
  • FIG. 11 is a diagram showing memory device-reading heads in combination with circuitry shown in FIG. 1;
  • FIG. 12 is adiagram of circuitry adapted for recording signals on the memory track of the device of FIG. 7;
  • FIG. 13 is a duplicateof a portion of the diagram of-FIG. 12 wherein exemplary values of some of the components are indicated.
  • FIGS.. 1V and 2 One embodiment of the present invention is illustrated in FIGS.. 1V and 2, by way of example, as including a twotransistor device-L comprising an NPN-type transistor T1 and aPNF'type transistor T2 which may be transistors known commercially as Texaslnstruments Company types 1.305 and L306. Each of said transistors has collector, emitter and base terminals or electrodes. Electrical energy is supplied to the transistors by a suitable source such as a 24-volt battery throughacircuit comprising conductors 1 and2. The voltage on conductor 1 may bedesignated Vb and that on conductor 2 may be zero or ground potential. Conductor l is connected to thecollector. terminal of transistor T1 and the emitter terminal of. transistor; T2 through a resistor R0 at a. junction D.
  • a twotransistor device-L comprising an NPN-type transistor T1 and aPNF'type transistor T2 which may be transistors known commercially as Texaslnstruments Company types 1.305 and L306.
  • Conductor 2 isconnected to the emitter terminal of transistor T1 through a resistor R1 and junction point F1 and to the collector terminal of transistor T2 through a resistor R2 and a junction point F2, said resistors being ofequal value.
  • the base terminal of transistorTl is connected to-asignal input terminal A through-a resistor R3, and the base terminal of transistor T2 is connected at a junction point C, between resistors R4 and R5 which are connected in series between conductors 1 and 2.
  • a terminal P- is also connected to conductor 1 between resistances (FIG. 2) or. other voltage dividing or distributing means 6. (FIG. 1).
  • Corresponding resistors in FIG. 6 are designated R10 and R11.
  • the supply voltages at points D, F1 and F2 may be designated V V and V respectively.
  • the voltage at point C, predetermined by the componentsR4 and R5 may be designated V
  • the points F1 and F2 are output terminals of the device L and are connected in the embodiment of FIG. 1 to input terminals of a commutator circuit M.
  • the latter comprises two solid statev conduction.
  • control devices which in the form shown are an NPN-type transistor T3 and a PNP type transistor T4, each transistor having collector, emitter and base electrodes or terminals.
  • the collector terminal of T3 is connected to terminal F1
  • the emitter terminal of transistor T4 is connected to terminal F2.
  • a signal input terminal B is connected to the base terminals of transistors T3 and T4 through resistors R6 and R7, respectively.
  • the emitter terminal of. transistor T3 and the collector terminal of transistor T4 are connected through equal resistors r3 and r4 respectively, to a single commutator output terminal S.
  • resistance components thereof have the values indicated for corresponding components in FIG.v 2, or other values in the same proportion.
  • R1. is equal to R2
  • R6. is equal to R7
  • r3 is equal r4 and by reason of the PN junction at transistor T2, the voltage V at point D will be equal to the voltage V at point C, and by reason of the NP junction at transistor T1 the voltage V at terminal F1 is equal to the voltage V,, at input terminal A.
  • the intensity of the current i t traversing resistance R0 is equal to the sum of the current i1 and i2 traversing the resistors R1 and R2, respectively.
  • V in each vertical column is the product of the signs of A and B in the same column, the module of this product being equal to at least the modules of A andB.
  • R5 are given values proportional to and resistances R4 and R Iy.
  • R0 may have a value of l k when R4 has the same value and R5 has a value of 2 k as indicated in FIG. 2.
  • the point P is brought to a potential Accordingly, the three potentials -g g values 0 and in the table above.
  • FIG. 3 The embodiment of the invention illustrated in FIG. 3 is identical with FIG. 1, except that the two-transistor commutator M is replaced by apparatus Mcomprising two vibration emitters 3a and 3b connected in series between point C and conductor 2 with a center tap 5 connected to control terminal B.
  • Vibration receivers 40 and 4b the electrical characteristics of which vary under action of the vibrations of the cor responding vibrations of the corresponding vibration emitter, have the input terminals thereof connected respectively to terminals F1 and F2.
  • the output electrodes or terminals of receivers 40 and 4b are connected to the common output terminal S by resistances rb and ra, respectively.
  • Vibration emitters 3a and 3b may be discharge tubes, such as nonpolarized gaseous discharge tubes, Hertzian radiating oscillators or electric or electromagnetic vibrators.
  • the corresponding receivers 4a and 4b may be photoelectric resistance, resistances, transistors havingbases equipped with antennae or carbon granule microphones.
  • the output voltage V When one of the control voltages, for example, V is an alternating current voltage, the output voltage V,- which will also be alternating will be eitherin-phase or out-of-phase or null. (without value) in relation to V depending upon whether V is positive, negative or without value.
  • the output voltage V may be used to control the operation and direction of of rotation of a two-phase electric motor, for
  • the motor as illustrated by way of example comprises a rotor 7 which may be caused to rotate in either direction by two fixed windings 8 and 9 mounted with their axes 8a and 9a perpendicular to each other.
  • terminal 11 may be connected to output terminal S of the multiplier L,M through suitable amplifying means, such as a push-pull amplifier N embodying transistors T5 and T6 of type NPN and PNP.
  • suitable amplifying means such as a push-pull amplifier N embodying transistors T5 and T6 of type NPN and PNP.
  • the voltages V and V may both be alternating current voltages.
  • Voltage V V sinmt having a maximum value V and a frequency to applied between terminal 22 and terminal P of a If desirable or necesmultiplier circuit L, M as well as to the ends of winding 21 of a selsyn rotor and to point B of the multiplier circuit through a resistor R8, generates in stator coil winding 20 connected between terminals P and A a voltage V, V C086 sinapt proportional to the cosin of the angle 0 and between the axes 20a and 21a of windings 20 and 21.
  • the circuit embodying the invention may serve to take a predetermined fraction of a value or of a voltage, to inverse that value or that voltage, to calculate the square of that value, etc.
  • One of its most important applications consists of a magnetic-coated dynamic memory tape or track presenting three states: a state of positive magnetization, a state of demagnetization and a state of negative magnetization.
  • one form of dynamic memory device of this type includes a base 30 on which a drum 31 with a magnetizable coating 32 is rotatably mounted. Suitable power means 33 are provided for rotating drum 31 relative to fixed reading heads 34a, 34b and 34c also mounted on base 30.
  • the reading heads are of known construction and may be made up of a magnetic circuit or split core 35 which carries magnetic flux and a coil or winding 36 having terminals 37 and 38 as shown in the enlargement of FIG. 9.
  • the surfaces or tracks 32 a, 32b and 320 of magnetic coating situated under the reading heads 34 may have the infonnation signals-h 0 and recorded thereon, respectively, in the form of positive dipoles N-S, demagnetized zones O-0 O-O and negative dipoles S-N.
  • a reference signal vr (FIG. 10 A) which can be read by one of the reading heads. This may by accomplished as illustrated in FIG. 11 by associating reading head 34c with a memory track 32c on which a series of positive dipole zones N-S have been recorded. This results in the generation of a voltage signal vr at terminals 370, 380.
  • the potential V at output terminal S varies with time according to curves S1, S2 or S3 FIGS. 10 C, 10 E and 10 G), respectively, thus restoring the signals 0 and
  • One may, if desired, record a series of negative dipoles S-N on track 320 in order to obtain output signals V having signs contrary to those recorded on track 32a, for example (Fig. 1 1
  • comparison circuit W contains-two transistors T7 and T8 of the same type, for example NPN, having collector, emitter and base terminals.
  • the collector terminals of transistors T7 and T8 are connected by a conductor 50 and resistances R12 and R13, respectively, to asourceof I voltage V,,.
  • the base of transistor T7 and the emitter of transistor T8 are connected through resistors R14 and R15 respectively, to a signal input terminal 51.
  • the base of transistor T8 and the emitter of transistor T7 are connected through resistors R17 and R16, respectively, to a terminal 52. Connections are made at points 53 and 54 to connect the collectors of transistors T7 and T8 to the base terminals of two type PNP transistors T10 and T9, respectively.
  • transistors T9 and T10 are connected to a junction 55 through resistors R18 and R19, respectively, and the emitter terminals thereof are connected to a junction 56 which is also connected through a resistance R20 to conductor 50 and hence to the source of voltage V.
  • transistor T11 of the same type as transistors T9 and T10 has its emitter terminal connected to junction 56 and its collector terminal connected through a resistor R21 to a junction 55 which isin turn connected to the mass or ground.
  • the base terminal of transistor T11 is connected through a resistor'R22 to supply line 50 and through resistors R23 and R24 to junctions 57 and 58, respectively, and thence to the collectors of transistors T9 and T10.
  • The: commutator circuit; M1 comprises a NPN-type transistorTlZ andaPNP-y type transistor T13.
  • An input terminal 59 is connected to the collector terminal of transistor T11 and through resistors R25 and R26 to the base electrodes of transistors T12 and T13, respectively.
  • the collector terminal of transistor T12 is connected to aterminal 61, and the emitter terminal of transistor T13 is connected to junction 58 and hence to the collector terminal of transistor T10.
  • the emitter terminal of transistor T12 and the collector terminal of transistor T13 are connected. directly to an output terminal 60 and thence to one terminal 37d (or 38d) of the winding of a recording head'-34d,-the construction of which is similar to the reading heads described above.
  • some signal voltages V,, V, and v representing the values 0 and are supplied attenninal 51.while the points 52 and 38d (or 37d) are carried to voltage V,,, the point 55 is carried to voltage V;.and the terminal 61 is carried to a high frequency (about kilocycles) alternating current voltage having a mean value equal to V If the signalinput at terminal 51 has a voltage of V, greater than V the voltage of the base tenninal of transistor T7 becomes greater than the voltage of its emitter terminal, the voltage on the base'terminal of transistor T8 becoming in turn less than that on its emitter tenninal. The result. is that transistor T8 is blocked, transistor T7 is conductive, and the potential of point 53 and of the base terminal of transistor T10 is lowered.
  • transistor T7 is blocked, transistor T8 becomes conductive, and thepotential at point 54 and the base of transistor T9 islowered. Since transistors T10 and T11 remain blocked as doalso-the:transistors T12 and T13, the voltage on terminal 3.72i-of the recording head is equal to V, for recording a negative signal on the track 32.
  • resistances R22, R23 and R24 thanks to which the base of transistor T11 is placed under voltage, allow for establishing equal thresholds,fields or paths for the voltages applied to terminal 51, according to the invention.
  • An electronic multiplier circuit for effecting the product of two numbers A and B represented by means of electrical voltages indicative of positive values, negative values and no value which voltages may be supply phase and control phase voltages for a two-phase motor or supply voltages for the rotor and stator of a synchronous motor, said circuit comprising a device capable of delivering on two output electrodes voltages indicative of numbers A and A when a voltage indicativeof the number A is supplied to an input electrode of said device, and a commutator, having an output terminal, a control terminal for receiving a voltage indicative of number B and two input terminals connected to said output electrodes of said device, said commutator being adapted, if B is positive, to connect its output terminal with said output electrode deliveringthe voltage indicative of the number A and, if B is negative, to connect said output terminal with said output electrode delivering the voltage indicative of the number A, and finally, if B has no value, to connect both said output electrodes of said device to said output terminal of said commuta- 01.
  • a circuit as defined in claim 1 wherein said device comprises first and second transistors of inverse types each having an en emitter, a collector and a base, the emitter of the first transistor and the collector of the second transistor being connected in parallel to one terminal of a source of electrical current through a common resistance, the collector of the first transistor and the emitter of the second transistor being connected to said output electrodes of said device and through separate equal parallel resistance to the other terminal of said source, the base of one .of the transistors being connected to said input electrode of the device, and the base of the other of the transistors being connected to a point in the circuit having a predetermined potential.
  • a circuit as defined in claim 2 comprising a resistance connected between said input electrode of the device and the base of said one transistor.
  • the vibration emitters are Hertzian radiating oscillators and said receivers are transistors having base terminals equipped with antennae.
  • vibration emitters are electric vibrators and vibration receivers are carbon granule microphones.
  • said commutator comprises two vibration emitters coupled to the control terminal thereof and two vibration receivers, the electrical characteristics of which vary in response to the vibrations of the corresponding vibration emitters, each of said vibration receivers being connected in series with a resistance between one of the input terminals of the commutator and the output terminal of the commutator, the resistances in series with said receivers being of equal ohmic value.
  • vibration emitters are nonpolarized gaseous discharge tubes and said vibration receivers are photoelectric resistances.
  • said commutator comprises two vibration emitters connected in series across said source of electrical current and having a center tap connected to said control terminal, and two vibration receivers the electrical characteristics of which vary in response to vibrations of the corresponding vibration emitters, each of said receivers being connected in series with a resistance between a respective commutator input terminal and commutator output terminal.
  • Electrical apparatus comprising a source of electrical energy, circuit means connected across said source comprising first and second resistors, a first solid state conduction control device interposed between said resistors in series therewith, a third resistor and a second solid a state conduction control device interposed between said first and third resistors in series therewith, each said conduction control device havingan input terminal connected to said first resistor, an output terminal connected to a respective one of said second and third resistors and a control terminal, a source of variable signal voltage, means including said source of signal voltage for connecting the control terminal of one of said conduction control devices to a source of voltage of predetermined constant amplitude, and means for connecting the control terminal of the other of said conduction control devices to a source of voltage of predetermined constant amplitude.
  • said conduction control devices are transistors having emitter, collector and base terminals.
  • ' one transistor is of PNP type.

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  • Engineering & Computer Science (AREA)
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  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
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  • Computer Networks & Wireless Communication (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Automation & Control Theory (AREA)
  • Evolutionary Computation (AREA)
  • Fuzzy Systems (AREA)
  • Nonlinear Science (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Control Of Stepping Motors (AREA)
US624877A 1966-03-21 1967-03-21 Electronic multiplying apparatus and circuitry therefor Expired - Lifetime US3544780A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR54262A FR1509926A (fr) 1966-03-21 1966-03-21 Circuit multiplicateur scalaire
FR98430A FR93361E (fr) 1966-03-21 1967-03-13 Circuit multiplicateur scalaire.

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US6005A Expired - Lifetime US3688284A (en) 1966-03-21 1970-01-07 Transistor recording circuit with commutator

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US (2) US3544780A (forum.php)
BE (1) BE695793A (forum.php)
FR (2) FR1509926A (forum.php)
GB (1) GB1186572A (forum.php)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3683165A (en) * 1970-07-23 1972-08-08 Computer Sciences Corp Four quadrant multiplier using bi-polar digital analog converter
US4053832A (en) * 1976-05-24 1977-10-11 National Semiconductor Corporation A.C. power meter
WO1991018363A1 (en) * 1990-05-16 1991-11-28 Analog Devices, Inc. Wideband differential voltage-to-current converters

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7424501B2 (en) 2003-06-30 2008-09-09 Intel Corporation Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations
US7539714B2 (en) * 2003-06-30 2009-05-26 Intel Corporation Method, apparatus, and instruction for performing a sign operation that multiplies

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Publication number Priority date Publication date Assignee Title
BE549248A (forum.php) * 1955-07-05
NL224364A (forum.php) * 1957-01-28
US3246219A (en) * 1957-05-03 1966-04-12 Devol Ferroresonant devices
CA673363A (en) * 1958-06-23 1963-10-29 N. Mellott Robert Computer magnetic drum writing circuits
US3034111A (en) * 1958-11-24 1962-05-08 Ibm Data storage system
US3290487A (en) * 1962-04-16 1966-12-06 Sperry Rand Corp Signal transducer
US3217183A (en) * 1963-01-04 1965-11-09 Ibm Binary data detection system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3683165A (en) * 1970-07-23 1972-08-08 Computer Sciences Corp Four quadrant multiplier using bi-polar digital analog converter
US4053832A (en) * 1976-05-24 1977-10-11 National Semiconductor Corporation A.C. power meter
WO1991018363A1 (en) * 1990-05-16 1991-11-28 Analog Devices, Inc. Wideband differential voltage-to-current converters
US5126586A (en) * 1990-05-16 1992-06-30 Analog Devices, Inc. Wideband differential voltage-to-current converters

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NL6704166A (forum.php) 1967-09-22
US3688284A (en) 1972-08-29
FR1509926A (fr) 1968-01-19
NL167043C (nl) 1981-10-15
GB1186572A (en) 1970-04-02
FR93361E (fr) 1969-03-21
BE695793A (forum.php) 1967-09-20
NL167043B (nl) 1981-05-15

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