US3522478A

US3522478A - Directional relay for circuit interrupters

Info

Publication number: US3522478A
Application number: US622213A
Authority: US
Inventors: Norbert J Reis
Original assignee: McGraw Edison Co
Current assignee: Cooper Industries LLC
Priority date: 1967-03-10
Filing date: 1967-03-10
Publication date: 1970-08-04
Anticipated expiration: 1987-08-04
Also published as: GB1176010A; DE1588559A1

Description

Aug? 1970' N. J. REIS DIRECTIONAL RELAY FOR CIRCUIT INTERRUPTERS Filed March '10. 1967 3 Sheets-Sheet l y w mm a n5 P z mJ w F 5 A It W K WM w m \J M w w W M f K W W llll iliJ. W w 1 u u WW :I G .F 3 iv 7 w j 6 a E 7 IL; C 5 JlDl z a 7 4 a L L k L gw A 7m m w v Ti l llll Ill? r 5) QMZLIQ H c) W. fi w I, #4

Aug. 45-1970 N. J. REIS DIRECTIONAL RELAY FOR CIRCUIT INTERRUPTERS Filed March 10. 1967 3 Sheets-Sheet 2 r m l. l I 5 |.l /fl| 7 tall: 54 I- I F w 1 V l! I III III A. 5/ M ll. :4

dlforbert J Reds 5 and WM Sheet 5 3 Sheets- Aug.4 1970 N. J. REIS DIRECTIONAL RELAY FOR CIRCUIT INTILRRUFTERS Filed March 10. 1967 United States Patent O 3,522,478 DIRECTIONAL RELAY FOR CIRCUIT INTERRUPTERS Norbert J. Reis, Wauwatosa, Wis., assignor to McGraw- Edison Company, Milwaukee, Wis., a corporation of Delaware Filed Mar. 10, 1967, Ser. No. 622,213 Int. Cl. H02h 7/26, 3/28 US. Cl. 317-18 20 Claims ABSTRACT OF THE DISCLOSURE A polyphase circuit interrupter having normally inactive time delay switch opening means and an individual directional control for each phase and for ground faults and each operative to initiate a switch opening operation if fault current flow is in the preferred direction. Each directional control includes a first circuit for producing a signal functionally related to the polarity of the voltage between two phases, a second circuit for producing a pulse in a time delayed relation to alternate changes of sense of the current in the third phase and a third circuit which produces an electrical signal when the current in the third phase is of fault proportions. Each directional control also includes an AND gate which is responsive to a signal from each of its associated circuits for actuating an output circuit which in turn initiates a time delayed switch opening operation.

BACKGROUND OF THE INVENTION Directionally controlled circuit interrupters may be provided, for example, in loop circuits or parallel connected load circuits and are generally constructed and arranged to produce an open-circuit condition if the flow of fault current is in a preferred direction. If fault current flow is in the reverse direction, however, the circuit breaker opening operation is blocked so that service can be maintained to nonfaulted portions of the system while the faulted section is isolated by other protective devices.

Many prior art directional relays were of the integrating type, that is, an output function would be performed only if the integral of the directional signals equaled a predetermined quantity. This required that the directional signals, which were generally functionally related to line current and voltage, have some minimum amplitude.

SUMMARY OF THE INVENTION In general terms the invention comprises a directional control for a protective device comprising first circuit means for producing a first signal upon the occurrence of an abnormal condition in the system being protected, second circuit means coupled to the system for producing an output signal when one of the system voltage and current quantities has a predetermined polarity, third current means coupled to the system'for producing an impulse signal functionally related to the occurrence of the alternation of the other system quantity, and logic circuit means for initiating a control function when the signals have a predetermined relation.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 schematically illustrates a conventional circuit interrupter incorporating the directional control, according to the instant invention;

FIGS. 2, 3 and 4 are vector diagrams illustrating the operation of the directional control illustrated in FIG. 1;

FIG. 5 illustrates the preferred embodiment of the instant invention; and

FIGS. 6A, 6B, 6C and 6D graphically illustrate the interrelation between the signals generated by the various components of the directional control shown in FIG. 5.

PREFERRED EMBODIMENT OF THE INVENTION FIG. 1 shows a three phase circuit interrupter incorporating a preferred embodiment of the instant invention and including main switch means 10 for interrupting the fiow of current in a three phase system ABC. The circuit interrupter includes a switch control circuit 11 and a directional control 12 having phase

directional circuits

14, 15 and 16 respectively associated with the phases A,

B and C and a ground directional circuit 18.

The circuit interrupter control circuit 11 may include a normally inactive timing circuit 20 whose operation is normally initiated upon the occurrence of an overload in the system ABC and a trip circuit 21 which is operative to open the main switch 10 upon the receipt of an actuating signal from the timing circuit 20. Operation of the timing circuit 20 is initiated in the illustrated embodiment by the receipt of an appropriate signal from the directional control 12 to which the timing circuit is connected by a conductor 23 and a transistor Q1.

The operation of the directional control 12 will be discussed in greater detail hereinbelow, it being sufficient at this point to state that when an overcurrent, or ground fault, occurs in the system ABC and current flow is in the preferred direction, normally nonconductive transistor Q1 will be rendered conductive.

The timing circuit 20 is connected to the phases A, B and C by current transformers T1, T2 and T3, respectively, and corresponding full wave rectifiers D1, D2 and D3 whose output terminals are connected in parallel. Resistors R1, R2 and R3 are connected across each of the secondary windings of current transformers T1, T2

and T3, respectively, so that a voltage will be derived across each rectifier which is proportional to the peak current in its respective phase, and the largest of these voltage drops will appear across capacitor C1.

The timing circuit 20 may include a timing capacitor C2 connected in series with a first timing resistor R4 and a diode D4 and the series combination is connected in parallel with a second timing resistor R5. As more fully described in co-pending application Ser. No. 800,567, filed Mar. 19, 1959, and assigned to the assignee of the instant invention, the impedance values of capacitor C2 and resistors R4 and R5 determine the charging time for any given fault current in the system ABC.

In operation, the current flowing to the collector of a charging transistor Q2 will split between the parallel paths defined by the timing resistor R5 and the series combination of timing resistor R4 and the timing capacitor C2. In the absence of an overcurrent having the preferred direction, capacitor C2 is prevented from charging because it is shunted by a leakage resistor R6 to which it is connected by diode D5. As a result of this leakage current, the terminal 25, at the junction between resistor R6, diode D5 and the collector of transistor Q1, has some positive potential. Transistor Q1 which is normally nonconductive isolates junction 25 from the ground bus 26.

As will be pointed out in greater detail below, when a fault current or ground fault occurs in the system ABC and it has the preferred direction, a base current signal will be received through conductor 23 to render transistor Q1 conductive to connect the terminal 25 to the gr ound bus 26. This, in turn, causes terminal 25 to assume ground potential so that leakage current can no longer flow from capacitor C2. As a result, the timing capacitor C2 is prevented from discharging through the resistor R6 and, therefore, begins charging. In this man ner, the timing operation is initiated. The diode D5 prevents reverse current flow from junction 25 to charging capacitor C2.

As timing capacitor C2 charges up, the potential at the junction 27 between diode D4 and the base of a coupling transistor Q3 will begin rising so that transistor Q3 emitter current which flows through resistor R7 will be functionally related to the voltage at point 27. As a result, a second transistor Q4, whose base is connected to resistor R7, will draw functionally related current through resistors R8 and R9 so that the potential of point 28 therebetween will also follow the potential of point 27. The base of a signal comparing transistor Q is connected to point 28 while its emitter is held at a constant potential by a Zener diode D6 and a resistor R10 which are connected across the

power supply buses

26 and 30.

After timing capacitor C2 has charged for a predetermined time, which is the time delay of the device, the potential at point 28 will reach a point where transistor Q5 is rendered conductive. This energizes relay 31 to initiate an opening operation of the main switches 10 in a manner well known in the art.

In the preferred embodiment of the invention, each of the phase directional circuits 14, and 16 and the ground directional circuit 18 is identical except for the manner in which each is connected to the system ABC and, for the sake of brevity, therefore, only directional circuit 14 is illustrated in detail and will be discussed.

Reference is now made to FIG. 2, which shows the vector relationships between the line current and line-toline voltages in the system ABC when current flow is in the preferred direction and assuming a balanced load and unity power factor. It can be seen that the current I in phase A lags the voltage V from phases B to C by 90. Should a fault occur in phase A, the fault current will fall back by an additional 45 70 so that it will have the approximate position I and lag the voltage V by approximately 150, as seen in FIG. 3. When current flow in the system ABC is in the nonpreferred, or opposite, direction, all of the current vectors I 1,; and I will be reversed 180 so that the current -I will lead the voltage V by 90, as shown in FIG. 4.

These vector relationships are employed by the directional current circuit 14 for initiating a switch opening operation when fault current is in the preferred direction. Toward this end, the directional circuit 14- generates a first signal upon the occurrence of a fault current in phase A, a second signal representative of the voltage vector V and a third signal representative of the current vector I If the fault current signal occurs when the voltage and current vectors have a predetermined relation, indicating fault current flow in the preferred direction, a control function is initiated.

The preferred embodiment of directional circuit 14 is shown in FIG. 1 to include an overcurrent sensing circuit 32 which is coupled to the phase A by a current transformer T4 and a full wave rectifier D7 and which produces an output signal when a fault current occurs in its associated phase. A phase peaking circuit 34 is also coupled to the rectifier D7 for producing a signal related to the current vector I and which takes the form of an impulse functionally related to alternate occurrences of the change in sense of the sinusoidal current wave I In addition, a voltage squaring circuit 36 is coupled to phases B and C by a potential transformer T5 for producing a signal functionally related to the voltage vector V and which takes the form of a signal which occurs whenever the voltage V has a predetermined polarity. An AND circuit 38 is provided for actuating an output circuit 40 when the signals from

circuits

32, 34 and 36 have the proper relation whereby the operation of the timing circuit is initiated in the manner discussed hereinabove.

Referring now to FIG. 5 which shows the preferred embodiment of the directional circuit 14 in greater detail, the overcurrent sensing circuit 32 is shown to include an input transistor Q6 Whose emitter and base are coupled 4 to the rectifier D7 through resistor R11 so that a transistor Q6 collector current will flow through resistors R12 and R13 which is functionally related to the highest peak current in phase A. This produces a potential on the base of a level detecting transistor Q7 which is also functionally related to said peak current. The emitter of transistor Q7 is held at a fixed potential by a Zener diode D8 and a resistor R15 which are connected in series with each other and across the

power supply buses

26 and 30. The collector of transistor Q7 is connected to the ground bus 26 through resistors R16 and R17. The base of an output switching transistor Q8 is connected to the junction between resistor R16 and R17 while its emitter is connected to ground bus 26 through a resistor R18 and its collector is connected to positive bus 30.

The components of the overcurrent sensing circuit 32 are so chosen that level detecting transistor Q7 will be nonconductive when normal current flows in phase A. However, should a fault current occur in phase A, the voltage drop across resistor R13 will reach a point where transistor Q7 will be rendered conductive to provide collector current through resistors R16 and R17. Upon this event, transistor Q8 becomes conductive to couple point 42 to the positive bus 30, whereupon the potential at this point changes from ground potential to some positive value. Point 42 is connected to the AND circuit 38 by conductor 43. In this manner, the overcurrent sensing circuit 32 will provide a positive voltage signal to the AND circuit 38 whenever an overcurrent occurs in phase A. This voltage signal is illustrated in FIG. 6A wherein the potential E goes from ground to some positive value upon the occurrence of a fault at time t The phase peaking circuit 34 performs the function of producing an impulse which is functionally related to alternate changes in sense of the current in phase A or, in other words, related to current vector I of FIGS. 3 and 4. More specifically, the circuit 34 includes an input transistor Q10 whose base is coupled to the rectifier D7 by diode D10 and to the

supply buses

26 and 30 by bias resistors R20 and R21, respectively, and its collector is connected to one terminal 44 of capacitor C4 and to the positive bus 30 by resistor R22.

The other terminal of capacitor C4 is connected to ground bus 26 through resistor R23 and through diode D12 to the base of normally nonconductive transistor Q11 of a monostable flip-flop circuit 45 which also includes a normally conductive transistor Q12. The base of transistor Q11 is also connected to the ground bus 26 through resistor R24 and its emitter is connected thereto by resistor R25 and its collector connected to positive bus 30 through resistor R26. The base of the second transistor Q12 of flip-flop circuit 45 is connected to ground bus 26 through resistor R28 and to the collector of Q11 by the parallel combination of capacitor C5 and resistor R29. The emitter of Q12 is connected to the emitter of Q11, and its collector is connected to the base of Q11 by capacitor C6 and to the positive bus 30 through resistors R30 and R32.

The base of an output switching transistor Q14 is coupled by a capacitor C7 to the junction between resistors R30 and R32 and by a resistor R33 and a diode D13 to the positive bus 30. In addition, the emitter of Q14 is connected to the postive bus 30 and its collector is connected through resistor R34 to the ground bus 26.

The voltage at the anode of diode D10 will follow the alternating wave form at rectifier D7 which is functionally related to the current wave in phase A. Transistor Q10 is conductive when its base potential is positive whereby terminal 44 of capacitor C4 is connected to the ground bus 26. However, when the base of transistor Q10 swings negative, it is rendered nonconductive so that the potential on terminal 44 of capacitor C4 begins rising to that of the positive bus 30 to which it is connected by resistor R22. This provides base current to transistor Q11 which turns on to turn transistor Q12 off. After capacitor C4 has become charged, base current continues to flow to transistor Q11 through resistors R30 and R32 and capacitor C6 until the latter also becomes charged. When capacitor C6 is fully charged, transistor Q11 turns oil and transistor Q12 turns on to provide a base current to transistor Q14 through resistors R30 and R33 and capacitor C7. This turns transistor Q14 on to connect point 46 to the positive bus 30 so that its potential goes from ground to that of bus 30. Capacitor C7 charges relatively rapidly so that transistor Q14 remains turned on for a relatively short time to provide a voltage pulse at point 46 which is connected to the AND circuit 38 through conductor 47. This pulsating voltage is illustrated in FIG. 6B.

The voltage pulse E appearing on conductor 47 represents the change in sense of the current flowing in phase A, but as the result of thre time delay introduced by capacitor C6 this current impulse is delayed. This is shown in FIG. 3 where the voltage E is shown to lag the current peak by 135. The pulse E is, of course, not a vector quantity so that it is represented by broken lines to indicate when it occurs in relation to the voltage V and the current I The voltage squaring circuit 36 includes a switching transistor Q16 whose base is connected to the potential transformer T through resistor R35 and to its emitter by diode D14. The collector of Q16 is connected to ground bus 26 through resistor R36 and to the AND circuit 38 through conductor 48. When the junction between resistor R35 and transformer T5 goes negative relative to the emitter of transistor Q16, the latter turns on to connect conductor 48 to the positive bus 30. On the other hand, when the junction between transformer T5 and resistor R35 swings positive, the transistor Q16 will be reversed biased by the drop across diode D14 so that it will be nonconductive and conductor 48 will go to ground potential. Thus produces the square wave form E on conductor 48, as shown in FIG. 6C.

Referring again to FIG. 3, it can be seen that the voltage peaks E will occur when the voltage E 48 is positive, as shown in FIGS. 63 and 6C. In addition, because the occurrence of the fault at time t will cause E to assume a positive voltage, as shown in FIG. 6A, a positive voltage signal will appear at each of the inputs of the AND circuit 38 at time t in FIGS. 6A, 6B and 6C.

The AND circuit 38 consists of diodes D15, D16 and D17, respectively connected to conductors 43, 47, 48 and a resistor R37 which is connected to each of said diodes and to the positive bus 30. As those skilled in the art will appreciate, there will be no output from the AND circuit 38 through diode D18 unless all of the conductors 43, 47 and 48 are connected to the positive bus 30 or, in other words, unless there is a simultaneous output signal from the overcurrent sensing circuit 32, the phase peaking circuit 34 and the voltage squaring circuit 36, as shown by the line t in FIGS. 6A, 6B and 6C. As stated hereinabove, this occurs where there is a fault in phase A and current How is in the preferred direction.

Should the current in the phase A be in the nonpreferred direction, the current vector --I would lead the voltage V by 90, as seen in FIG. 4. Since the voltage -'E47 would be delayed 135 it would then lag the voltage V as shown in FIG. 4. Should a fault current occur in the reverse direction, the voltage -E will be delayed an additional 60, as shown by -E After the occurrence of the fault at time t the voltage impulse E would occur at time t when the voltage B was zero, as shown in FIGS. 6C and 6D. As a result, when a fault occurs and current flow is in the preferred direction, an output would occur through diode D18 from the AND circuit 38, but no output would occur when 6 the current was in the alternate, or nonpreferred, direc tion.

The output circuit 40 includes a first transistor Q17 whose base is coupled to the diode D18 of the AND circuit 38 and to the ground bus 26 through resistor R38. The emitter of Q17 is connected to ground bus 26 through resistor R39, and its collector is connected through resistor R40 to terminal 50 of capacitor C8, the other terminal of which is connected to the positive bus 30. The base of a second transistor Q18 is connected to the emitter of Q17 while its emitter is connected to ground bus 26 and its collector is connected to the collector of Q17.

The output circuit 26 also includes a third transistor Q19 whose base is connected through resistor R41 to the junction 50 between resistor R40 and capacitor C8 and through resistor R42 to positive bus 30. The emitter and collector of Q19 are respectively connected to the positive bus 30 and the ground bus 26 through resistors R43 and R44.

It will be appreciated that the AND circuit 38 will provide an output circuit through diode D18 for relatively short intervals corresponding to the voltage impulses at the output of phase peaking circuit 34. These output signals through diode D18 are amplified by transistors Q17 and Q18. The amplified signal charges capacitor C8. When the charge on capacitor C8 reaches a predetermined value, the transistor Q19 is rendered conductive to provide an output signal to the timing circuit 20 through conductor 23.

It will be recalled that when transistor Q1 of the timing circuit 20 was nonconductive the current through the timing capacitor C2 was shunted through resistor R6. However, when transistor Q19 is rendered conductive, a base current is provided to transistor Q1 wherein the latter also becomes conductive to isolate resistor R6 from capacitor C2. In this manner a switch opening operation is initiated.

As seen in FIG. 1, directional circuit 15 is coupled to receive signals functionally related to current I and voltage V and directional circuit 16 is coupled to receive signals functionally related to the current I and voltage V In addition, the ground circuit 18 is coupled to each of the phases by transformers T6 and T7 in a manner well known in the art for receiving a voltage and current signal functionally related to the unbalance voltage and current in the system ABC.

While the switch control circuit 11 is shown in the illustrated embodiment to be dependent on the directional control 12 for overload sensing, those skilled in the art will appreciate that it can also be provided with an overload sensing circuit similar to circuit 32. In the latter event this overload sensing circuit would be normally disabled to be rendered operative by transistor Q1 or the like.

It will also be appreciated that the output circuit 40 is similarly connected to each of the

directional circuits

15 and 16 and to the ground circuit 18. As a result, when a fault occurs in any of the phases A, B or C, or a ground fault occurs, and the current flow is in the preferred direction, the output circuit 40 will be actuated and this, in turn, will actuate the timing circuit 20 so that a switch opening operation will be performed.

If it is desirable to provide operation of the ground circuit 18 according to a different characteristic than that of the phase

directional circuits

14, 15 and 16, the ground circuit 18 could be provided with an individual output circuit similar to output circuit 40 and/or an individual timing circuit similar to timing circuit 20.

Those skilled in the art will also appreciate that the peaking circuit 34 and the squaring circuit 36 can be rcversed relative to the system voltage and current. In other words, the invention contemplates that, instead of the current peaking circuit 34 and the voltage squaring circuit 36, a current squaring circuit and a voltage peaking circuit could be provided. In the latter event, a wave similar to that of FIG. 6C would be provided whenever the system current had a predetermined polarity, and a pulse similar to that of FIGS. 6B and 6D would be provided in a timed relation to the alternation of the voltage wave.

In addition, while in the preferred embodiment the voltage is sensed across the other two phases relative to that from which the current quantity is sensed, the voltage could be sensed between any two phases or between any phase and ground or neutral.

Also, while the invention has been illustrated and described in relation to a three phase system, it could also be employed with a single phase system wherein only a single directional circuit would be employed.

Accordingly, while only a single embodiment of the instant invention has been shown and described, other modifications thereof will become apparent to those skilled in the art once the inventive concept is known.

I claim:

1. In an electrical system for producing alternating polarity voltage and current quantities, a protective device having a separate directional control for each phase and ground circuit of said system comprising first circuit means coupled to said system for producing a first output signal upon the occurrence of an abnormal current condition, second circuit means having a single coupling with said system for producing an output signal when one of said quantities has a predetermined polarity, third circuit means having a single coupling with said system for producing an output signal functionally related to the change in polarity of the other one of said quantities and fourth circuit means coupled to said first, second and third circuit means to receive said signals for producing an output function when said signals all occur during a predetermined time period.

2. The protective device set forth in claim 1 and including input circuit means for producing a first input signal functionally related to the current quantity in said system, said first circuit means being operative to produce said first output signal when said first input signal has a predetermined value.

3. The directional control set forth in claim 1 and including input circuit means for producing an input signal functionally related to said voltage quantity and another input signal functionally related to said current quantity, said second circuit means being operative to produce said second output signal when either one of said input signals has a predetermined polarity, and said third circuit means producing said third output signal in a time rela tion to the change in polarity of said other one of said input signals.

4. The directional control set forth in claim 1 and including input circuit means for producing a first input signal functionally related to the current quantity in said system and a second input signal functionally related to said voltage quantity and a third input signal functionally related to said current quantity, said first circuit means being operative to produce said first output signal when said first input signal has a predetermined value, said second circuit means being operative to produce said second output signal when either one of said second and third input signals has a predetermined polarity, and said third circuit means producing said third output signal in a time relation to the change in polarity of said other one of said second and third input signals.

5. The protective device set forth in claim 4 wherein said fourth means comprises logic circuit means for producing said output function upon the simultaneous occurrence of said output signals.

6. The protective device set forth in claim 5 and including switch means and time delay switch opening means coupled to said system for opening said switch means in an inverse time-current relation, means normally rendering said switch opening means inactive, said switch opening means being coupled to said fourth circuit means for being rendered operative in response to said output function.

7. The protective device set forth in claim 4 wherein said second circuit means is operative to produce said second output signal when said second input signal has a predetermined polarity, said third circuit means being operative to produce said third output signal in a time relation to alternate changes in sense of said current quantity.

8. The protective device set forth in claim 4 wherein said first circuit means includes level detecting means and output switching circuit means, said level detecting means being operative to actuate said output switching circuit means to provide said output signal when said first input signal equals a predetermined value.

9. The protective device set forth in claim 8 wherein said second circuit means includes switching circuit means constructed and arranged to become operative for producing said second output signal when one of said second and third input signal has a predetermined polarity, said third circuit means includes peaking circuit means and time delay circuit means and output switching circuit means and being operative to provide an output impulse signal having a time delayed relation to alternate changes in sense of the other of said second and third input signals.

10. The protective device set forth in claim 4 wherein said second circuit means includes switching circuit means constructed and arranged to become operative to produce said second output signal when said second input signal has a predetermined polarity, and wherein said third circuit means includes peaking circuit means and time delay means and output switching circuit means and being operative to provide an output impulse signal having a time delayed relation to alternate changes in sense of the other of said second and third input signals.

11. The protective device set forth in claim 10 wherein said first circuit means includes level detecting means and output switching circuit means, said level detecting means being operative to actuate said output switching circuit means to provide said output signal when said first input signal equals a predetermined value.

12. The protective device set forth in claim 11 and including switch means and time delay switching opening means coupled to said system for opening said switch means in an inverse time-current relation, means normally rendering said switch opening means inactive, output circuit means being coupled to said logic circuit means and to said switch opening means for rendering the latter operative in response to said output signal.

13. A protective device for a three phase system and including a directional control comprising a phase direction control circuit associated with each of said phases and a ground direction control circuit, each of said phase control circuits including input circuit means for sensing the current quantity in its associated phase and the voltage quantity associated with at least one of the phases, said ground control circuit being coupled to each of said phases for sensing the unbalance voltage and current quantities in said system, each of said control circuit means including first circuit means for producing a first output signal when its respective current quantity exceeds a predetermined value, each of said control circuits also including second, third and fourth circuit means, each of said second circuit means being operative to produce a second output signal when one of its voltage and current quantities has a predetermined polarity, each of said third circuit means being operative to produce a third output signal in a timed relation to the alternation of the other of its voltage and current quantities, each of said fourth circuit means being operative to initiate the simultaneous current interruption in each of said phases when said output signals have a predetermined relation.

14. The protective device set forth in claim 13 wherein the voltage quantity is taken across the other two phases.

15. The protective device set forth in claim 14 wherein each of said second circuit means includes switching circuit means constructed and arranged to become operative to produce said second output signal when its voltage quantity has a predetermined polarity, and wherein said third circuit means includes peaking circuit means and time delay means and output switching circuit means and being operative to provide an output impulse signal having a time delayed relation to alternate changes in sense of its current quantity.

16. The protective device set forth in claim 15 wherein each of said first circuit means includes level detecting means and output switching circuit means, said level detecting means being operative to actuate said output switching circuit means to provide said first output signal when its current quantity equals a predetermined value.

17. The protective device set forth in claim 16 wherein each of said fourth circuit means comprising logic circuit means for producing said output function upon the simultaneous occurrence of said output signals.

18. The protective device set forth in claim 17 and including switch means and time delay switch opening means coupled to said system for opening said switch means in an inverse time-current relation, means normally rendering said switch opening means inactive, said switch opening means being coupled to each of said fourth circuit means for being rendered operative in response to said output function.

19. The combination according to claim 1 wherein said fourth circuit means has first, second and third input circuits and an output circuit, said first, second and third circuit means being respectively coupled to said first, second and third input circuits and being also coupled to said output circuit.

20. In an electrical system for producing alternating polarity voltage and current quantities, a protective device having a directional control comprising input circuit means for producing a first input signal functionally related to the current quantity in said system and a second input signal functionally related to said voltage quantity and a third input signal functionally related to said current quantity, first circuit means being operative to produce a first output signal when said first input signal has a predetermined value, second circuit means being operative to produce a second output signal when either one of said second and third input signals has a predetermined polarity, third circuit means for producing a third output signal in response to the change in polarity of the other one of said second and third input signals and fourth circuit means coupled to said first, second and third circuit means to receive said output signals for producing an output function when said output signals all occur during a predetermined time period.

References Cited UNITED STATES PATENTS 2,879,454 3/1959 Hodges et a1. 3l728 2,973,462 2/ 1961 Chevalier 317-48 X 3,178,616 4/1965 Blackburn et a1. 31736 X 3,273,017 9/1966 Mathews 3l728 X JAMES D. TRAMMELL, Primary Examiner U.S. C1. X.R.