US3508246A - Fine-resolution digital position encoder - Google Patents

Description

-April 21, 1970 QELENZ 3,508,246

FINE-RESOLUTION DIGITAL POSITION ENCODER Filed June 11, 196s s sheets-sheet 1 c DIGITAL PHASE c,

DEMoDuLAToR 3 1 2\ I VTT- "5 "L T I DIGITAL l 7 PERIOD x I Two-PHASE l Xe., 0UNT c CARRIER I GENE'WOR I IHGREHENTAL er I x IouTPuT erq I |314 SIGNA SHAFT PHASE I x ccw 9+ ANGLE SHIFT 0 M1; ZERO P2 COUNTER 'Mmm l y .A o TTRANGDUGER i' grssmm@ :D SELECTOR l" DET|:cT\oR c' Aeo- 1 w 4/ l 5' cl l Tea I I c2 X PERIOD I/` Two-PHASE I eb L L couHTER x l cLocK I 8 cn l I L ..f. 1

*HHC I7 I9 f l MMIII/umlIIIIIIIII, f 2T cLocK s. I2 sa 's3 *s4 'ss l C20 I\|/I IIIIIIIIIIIIII. T 31' ET Imf/e l-I3 LOGICAL XI' M I l I l I I l REFERENCE 0 M CARRIERS mf-Pl l l XmO-L'I- I I L I L I I. f Em /.I5 Ie sINusDIDAL er o I REFERENCE E T... CARRIERS E m '6 2 e gL\/ O\/\ t q EI m DuANTIzATIoN ELEMENT as 2| 24 ^q=l 27 .l/-Q

TRANsDUcE e EIRL" k'mfc o O \l 'Em 30 z Aq? is f4 We lNvENToR.

I- A A 4=2 34 3' Bom Q3 q CHARLES LEHz BY FIG .2 @7

. ATTORNEY April 21, 1970 c. E. LENz 3,508,245 l FINE-RESIIUTION DIGITAL POSITION ENCODEI.

Filed June 1l, 1965 3 Sheets-Sheet 2 l T I l F |o| I F|o| l Flol Burgh/q UNTER 7 ENABLING SIGNAL Xea FIG. 4

April 21, 1970 c. E. LENZ 3,508,246

FINE-RESOLUTION DIGITAL POSITION ENCODER Filed June 1ll 1965 cLocK LoelcAL rr-ERENCE {Xr y RmER QuANTlTlzED T TRANsDucER |o| QuTPuT XPF zERo F|o| cRossmo DETEcToR X1 2= Floz COUNTER X sELEcToR l G 20| xeb= 5202 xca=v couNTER 7 G30| couNTER a MoTloN ^e= DETEcToR AND A50 ouTPuT SIGNALs A 5 3 Sheets-Sheet 3 MIIWIIQIIWlHr/H,

gjr/lfl/llllllllulllll,

omr-

Otlgr t2 i3 f4 's t o T v 55/ sYNcHRoNous SAMPLING IN V EN TOR.

v CHARLES E. LENZ ATTORNE United States Patent() 3,508,246 FINE-RESOLUTION DIGITAL POSITION ENCODER Charles E. Lenz, Fullerton, Calif., assignor to North American Rockwell Corporation, a corporation of Delaware Filed June 11, 1965, Ser. No. 463,090 Int. Cl. G08c 1/00 U.S. Cl. 340-347 9 Claims ABSTRACT OF DISCLOSURE A position encoder for generating digital signals as a function of angular or linear position, wherein a periodically varying signal, modulated as a function of input position, is applied to a zero crossing detector which produces enabling signals as a function of the phase of the input signal. Counter means, responsive to the enabling signals, provides rst pulses of predetermined duration as a function of alternate enabling signals and second pulses of predetermined duration as a function of the remaining enabling signals. A motion detector responsive to the first and second pulses provides a rst output pulse when the rst and second pulses are simultaneously true and a second output pulse when the first and second pulses are simultaneously false.

Thisiinvention pertains to a position encoder system for converting angular or linear position to a corresponding digital signal or more particularly to an encoder system which first transforms shaft angle or linear displacement into a proportional carrier-signal phase shift and then converts this phase shift into a digital signal.

Some of the particular advantages of the invention are: freedom from fundamental limitations of many earlier encoders in respect to ultimate resolution and physical size; the ability to convert a standard resolver in an existing system to adigital encoder, thereby providing the advantages of digital data transmission and compatibility with a digital computer without extensive system modification; and the ability to very accurately measure either rotary or linear motion directly without mechanical linkages which are susceptible to wear, backlash, or inaccuracy.

These advantages are achieved by converting shaft angle to a carrier phase shift by utilizing a transducer such as an optical or electromagnetic resolver having any speed or number of pole pairs. Logical elements then convert the resultant phase-shifted carrier to an incremental digital signal such that each pulse on the first or second of two signal lines represents an increment of clockwise or counterclockwise motion.

`To achieve these advantages it becomes a major object of the present invention to provide an encoder for converting angular or linear position to a corresponding digital signal.

It isv another object of this invention to provide an improved encoder for generating a digital output signal of finer resolution than heretofore attainable.

`It is a further object of this invention to provide a unique position encoder system.

It isstill a further object of this invention to provide a .fine-resolution digital position encoder for converting angular or linear position to an incremental or wholevalue digital signal. v

These and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings in which:

FIG. 1 is a block diagram of the position encoder system;

3,508,246 Patented Apr. 2l, 1970 ICS FIG. 2 illustrates various waveforms utilized by the position encoder system;

FIG. 3 is a logic diagram of a portion of the position encoder;

FIG. 4 is a logic diagram of another portion of the position encoder; and

FIG. 5 illustrates various wave forms related to the position encoder system.

THE #SYSTEM It is to be understood that although an angular type encoder will be specifically described, it will be obvious to those persons skilled in the art how to apply the invention disclosed herein to encode linear motion.

Referring to FIGS. l and 2, the basic components of the position encoder system are a two-phase clock 1, a digital two-phase carrier generator 2, a phase-shift transducer 4, and the components of the digital phase demodulator 3. The digital phase demodulator 3 includes a zerocrossing detector 5, a counter selector 6, two period counters 7 and 8 and a motion detector 9.

The position encoder system has a single input, the mechanical shaft angle HOU) to be measured. Counterclockwise rotation will be considered positive, clockwise rotation negative. The angular shaft velocity is assumed to be constrained by the relation Where the fixed reference-carrier frequency wr is to be defined later. An initial encoder-shaft position mn=l.(0) mn (2) will also be assumed. The positive integers m and n, design parameters of the encoder, will be discussed further in the subsequent text.

Two output signals are provide, A00+(t) and A0C-(t), from which the net variation of the shaft angle 0(t) since the esablishment of initial conditions at t=0 can be determined. Both A00+(t) and A0o*(t) are normally false two-valued logical signals. If the encoder shaft is rotated only counterclockwise (or only clockwise), one pulse will be emitted at output A60+(t) (or output mo-(O) for each i21r/ (mn) radian of motion.

The output signals A00+(t) and A05-U) resulting from bidirectional shaft rotation are most easily considered in the steady state wherein the shaft velocity for an adequate period; no pulses will then be emitted at either A0o+(t) or Aro-(t) as long as Equation 3 remains valid. If after t=0 a total of p+(t) pulses has been emitted at the output A0O+(t), and a total of p-(t) pulses has been emitted at output AGO-(t), then the eucoder shaft position at time t is Within the range in the steady state and the interval of uncertainty is closed only on the left. The shaft position 0o at time t can thus be determined within plus or minus one-half resolution-element width by multiplying the resolutionelement width 21r(mn) by the net difference p+(t) -p-(t) between the numbers of pulses emitted at the outputs A+(t) and 1100"(1). This characteristic constitutes the basic principle of operation of the encoder.

The above discussion can now be extended to include operation of the encoder when it is not in the steady state. Equation then still applies, but the tolerance e(t) will be somewhat larger than shown in Equation 6 because of the slight delay in response due to sampling within the encoder. It is significant, however, that Equation 6 once more applies as soon as the encoder again enters the steady state; thus no cumulative error develops.

In the following discussion the position encoder will be viewed externally as a complete system, the dynamic response of which is to be determined. Consequently,

explanation of the physical significance of certain of the quantities relevant to internal operation of the encoder will be deferred for later consideration.

The encoder is essentially a sampled-data device. The ith synchronous sampling period (z' 0) starts at the sampling time ts, defined by t1+Tefsi=)7' 1'i-T+Te (7) where 1- is the clock period, Te is the minimum time interval for which an enabling input -must have been true at the time of a trigger-pulse trailing edge to initiate flipiiop response to that trigger pulse, and t, is obtained by solving the equation wr+n0o(t1)`ll8o:27r(i1) where )80 is a bias angle to be defined later. The left side of Equation 8 represents the argument of the sinusoidal carrier output of the phase-shifting transducer 4 used in the position encoder. Thus each positive-slope zero crossing of this phase-shifted carrier, delayed until a succeeding trailing edge of a clock pulse, initiates a new synchronous sampling period. Equation 7 is introduced to accommodate the effects of synchronization. In it j is a non-negative integer chosen to satisfy the inequality shown there. The ith asynchronous and synchronous sampling periods extend over the respective intervals 00(1) is quantized into mn equal resolution elements, each of width 21r/ (mn) radian, by the encoder. The encoder. The center of the qth resolution elements thus lies at mn (12) When 000i) lies within the qth resolution element,

' i meow l v2 2W q'l'2 (13) 27V 1 @ow-M [mi-5] (14) where the range of uncertainty is closed only on the left. The range over which the integer q must vary to include al1 possible values of 00(1) is established by the application; in some cases q must vary without limit. For cases Where the range of q exceeds mn the shaft will be positioned between the same physical limits for values of q which differ by an integral multiple of mn.

The encoder functions by measuring variation of the index q(t) of the resolution element within which the output-shaft `position 000) lies at time t as defined by Equations 12 through 14. Let the variation of q(t) dur- 4 ing the ith asynchronous sampling period defined by Equation 9 be Aqi. Then,

(l) If Aq1 0, the first AqiCU) clock pulses after the ith synchronous sampling period defined by Equation 10 will be emitted at output A0o+(t).

(2) If Aqi 0, the last --AqiC(t) clock pulses during the ith synchronous sampling period will be emitted at output A60-(t).

(3) If Aqi=0, no pulses will be emitted at outputs A0+(t) Ior Ao-(r) either immediately Ibefore or after the end of the ith synchronous sampling period.

Thus during synchronous sampling period z', the number of pulses emitted at output A0o+(t) is p AC11-1, A11 1 0, 122 (15a) 1 0, f=1 or mais), 122, (15b) and the number emitted at output 10o-(t) is f-q1, Aq1 0. il (16a) l" l0, Aq1=0, 121 f (16h) where A11=q(fi+1)q(1), (17) Under dynamic conditions, it now also becomes possible to determine the encoder shaft angle 00(t) by observing the incremental outputs A60+(t) and A00"(t). To achieve this result, it is first noted that the index of the center angle 00(tk) of the resolution element within which @olies at time tk defined by Equation 8 is t A i+ t k 1 QM) q 9(1) (18) where Aqi is defined by Equation 17. From Equations 2, 8, and 13, it follows that In Equation 18 it is necessary to evaluate y(tk) from the observable quantities 111+ and p1. This can be accomplished by substituting Equations l5 and 16 into Equation 18 to yield The two summations shown equal, respectively, the total number of pulses p+(ts(k+1)) emitted at output A60+(t) before the synchronous sampling time ts(k+1) and the total number of pulses p(tsk) emitted at output A00'*(t) before the synchronous sampling time tsk. Thus By substituting Equation 21 into Equation 14, it follows that 0 (k)=2l|:29+(l5 GMD-1V@ +l] mn E s *2 (22) where the interval of uncertainty is closed on the left only.

Equation 22 defines the dynamic response of the position encoder system in terms of the shaft angle 0o at the time tk of any positive-slope zero crossing of the sinusoidal output eo(t) of the phase-shift transducer 4. It states that this shaft angle equals the product of the mechanical quantization width 21r/ (mn) and the difference p+-p between the total numbers of positive and negative incremental pulses emitted at outputs A00+(t) `and 10(0), respectively. The total p* is taken at the synchronous sampling time tsk following tk; the total p+ is taken at the synchronous sampling time ts k+n following the next positive-slope zero crossing of e(t) at tk+1. It is the quantizing element in which 0o lies at Ik that is established by Equation 22; thus 000k) is defined within a tolerance of il/z quantizing width.

OPERATION OF COMPONENTS Operation of the components of the position encoder system shown in FIG. 1 will now be described in detail. The discussion will begin with brief reference to the generalized logic eleements from which these components are synthesized.

The trigger T101 has an input and two outputs identified by the symbols shown with T101 in FIG. 3. These symbols have the following significance:

TTk`= analog input of trigger Tk, Ik=normal logical output of trigger Tk, Tk=complement logical output of trigger Tk,

where k is assigned a positive integral value to designate a particular logic element.

The instantaneous value of each logical output just defined is the complement of the other. A trigger converts an analog input to a logical output in accordance with the equation The preceding equation defines the instaneous logical value of the logical signal Tk. In general, the correspond ing instantaneous electrical value of such a signal can exist only within one of two mutually exclusive ranges. One such electrical range is defined as corresponding to the logical value l; the other electrical range is define as corresponding to the logical value 0.

All flip-flops employed are of the JK type. (Ref.: Montgomery Phister, Ir., Logical Design of Digital Computers, pp. 128-129, 134-135.) Trailing-edge triggering whereby each flip-flop is responsive only to 1to0 transitions at the trigger input is used throughout. For clarity, the normally false clock signals C1(t) and C2(t) (FIG. 2) will be shown as idealized pulse trains in which the pulse length T rnust be no shorter than the enabling time fe of the flip-flops employed.

Symbols associated with the inputs and outputs of a typical flip-flop are shown with F101 in FIG. 3. These symbols are defined in the generalized form as follows:

1F16: set-enable input of flip-flop Fk, TFk=trigger input of flip-flop Fk, 0Fk=resetenable input of flip-flop Fk, Fk=normal output of flip-flop Fk, F11-:complement output of flip-flop Fk.

Each gate employed, for which the symbol Gk is typical, is of the nand type. Such a gate produces a false output if, and only if, all inputs are true. A logical inverter functions much as a single-input nand-gate to produce a logical output which is the complement of its input; Ak is a typical symbol for such an element. The output of either a nand-gate or a logical inverter is denoted by the same symbol as the logic element' itself. In FIG. 3, G201 and A501 are typical examples of these two elements; a small circle is employed to indicate the function of producing the logical complement in both cases.

Except where otherwise stated, all transmission of information between components is by means of two-level logical electrical signals; one such level is assigned the logical value 1, the other the logical value 0.

TWO-PHASE CLOCK 1 AND DIGITAL TWO- PHASE CARRIER GENERATOR 2 Two sources of reference signals are employed in the position encoder system, a two-phase clock and a digital two-phase carrier generator (1 and 2, respectively, in FIG. l).

The logical outputs C1(t) and C2(t) of. the two-phase clock, each a pulse train of period fr, are shown in FIG. 2. All waveforms will be shown only for t 0 and are in the steady state at t=0 unless otherwise stated. The first pulse of C1(t) shown is last true at T, the first pulse of C?) at r/ 2. Idealized pulses of length 1c approaching zero are shown in both trains. Both clock signals are identical except for time displacement, i.e.,

where t is elapsed'time. Each clock signal is normally false (i.e., normally has the logical value 0) and of low duty cycle. The clock-pulse length is typically during each such interval, a clock pulse remains continuously true.

The digital two-phase carrier generator 2 has as the only input the clock signal C1(t). This component generates two fixed-frequency sinusoidal carriers such that C1(t) and C2(t) pulses occur at the same angular positions within each cycle. Thereference and quadrature Outeru) :Em sin (wt-i730) (25) puts are and erq(f)=Em COS (wifi-160) (26) where Em is a constant of dimension volts,

21r "fr (27) and 27M'e mf (2s) Here the positive integer m is the interpolation ratio of the encoder; it typically is an integral multiple of 4 equal to the number of internal states of the carrier generator and of each period counter 7 and 8. The bias ,o is introduced to premit a mechanical resolution element to be centered at 00:0. As Equation 28 shows, the bias required approaches zero when the ratio Te/r decreases sufiiciently. A device which may be utilized to perform the functions of generator 2 is disclosed and claimed in applicants co-pendiug U.S. patent application, Ser. No. 394,977, filed Sept. 8, 1964, entitled Digital Reference Source and assigned to North American Aviation, Inc., the assignee of this invention.

Theperiodic logical signals Xr(t) and X1q(t) shown in FIG. 2, each of 50% duty cycle, are generated within the two-phase carrier generator 2. The period of each of these signals is mf, where the positive integer m (typically a multiple of 4) equals the number of internal states of the carrier generator. In the example of the position encoder to be discussed, m` is set equal to 4 for simplicity. Each transition of Xr(t) and of X,q(t) is initiated by a l-to-O transition of C(t), the first l-to-O transsition of Xrq(t) for t greater than 0 Ibeing initiated by the C2(t) trailing edge which occurs at t=m1/4. The two logical carrier signals are related by the equation The electrical outputs of the digital two-phase carrier generator 2 are the sine and cosine waves er(t) and e,q(t), each of angular frequency wk. These signals are defined by Equations 25 and 26. They are the fundamental sinusoidal components of the logical reference carriers Xr(t) and X), respectively, obtained by passing each of these logical signals through a separate bandpass filter. Each filter can be detuned slightly from w, to introduce a phase shift which permits Equations 25 and 26 to be satisfied exactly. Alternatively, each filter can be tuned to w, and the rotor of the phase-shift transducer displaced slightly on the shaft to obtain the same effect. It is sig nificant that C1(t) pulses are generated having the same time relationships to each positive-slope zero-crossing of .e,(t) and em(t). For example (Ref: FIG. 2), the trailing edge of C1(t) at (17) lags the positive-slope zero crossing of e,(t) at (18) by mvo/ (21r), and the trailing edge of the C1(t) pulse at (19) lags the positive-slope zero crossing of e,q(t) at (20) by the same amount.

PHASE-SHIFT TRANSDUCER The phase-shift transducer 4 of speed n has as inputs the shaft angle 0(t) to be measured and the two-phase sinusoidal carriers er(t) and e,q(t) defined by Equations 25 and 26. It shifts lthe instantaneous phase of er(t) by an amount which is a linear function of the shaft angle (t). The resultant phase-modulated output is eo(t):Em sin [NH4-(#00)] (30) where Several types of transducers are suitable for use as component 4 to vary the phase (,(t) of the sinusoidal reference carrier er(t) as a linear function of the shaft angle l 6.(t) in accordance with Equation 31. The speed or the transducer employed is typically an integer equal 'to or greater than l, a higher speed yielding finer mechanical resolution with a given phase demodulator 3.

A suitably excited resolver can be used as the phaseshift transducer 14. Utilization of a resolver is based upon the trigonometric identity for the sine of the sum of two angles x and y, viz,

sin (x-f-y)=cos y sin x+ sin y cos x (33) If the definitions x=wrt`io (34) and yare made, if Equations 34 and 35 are substituted into Equation 33, and if the result is multiplied by Em, it follows that Em sin [wrtln0o(t) 'iol :9010) leo2(t) :600) (36) in accordance with Equation 30 where e01(t)=Em cos 110(t) sin (wrt-l-o) (37) and e020) :Em sin n00b?) cos (wrt-f-o) (38) Equations 37 and 38 can be mechanized by attaching an n-speed resolver having rotor-angle sine and cosine chan- 'nels to the rotating member of which the position 0(t) is to be measured. A resolver having unity maximum gain in each channel will be assumed. If the rotor-angle cosine channel of the resolver is now excited by er(z) and the sine channel is excited by erq(t) as defined by Equations 25 and 26, the respective voltages shown in Equations 37 -and 38 result. These voltages can be added by conventional means to obtain the required output voltage e0(t) The phase-shift transducer input 0(t) shown in FIG. 2

`at 21 will be used to illustrate operation of the position encoder. Shown with 0(t) are the interfaces between quantization elements -1 and 0 at 22 and between quantization elements 0 and 1 at 23. The encoder shaft angle 0(t) is (l for t() and remains 0 until it starts to increase at 24. At 25 @0(t) moves between quantization elements 0 and 1 to reach a maximum value of vr/(Zn) radians at 26. The shaft angle then decreases to pass between quantization elements 1 and 0 at 27 and 0 and -l at 28. Finally, at 29 00(1) reaches a steady-state value of 1r/(2n) radians.

The corresponding phase-shifted carrier output e0(t) of the phase-shift transducer 4, as defined by Equation 30 appears at 30. In accordance with Equation 8, with i=l and 00(t1)=0, the rst positive-slope zero crossing shown, which appears at 31, occurs at 8 'I'he instantaneous angular frequency of e0(2) remains of constant value wr until 32. It is greater than 'wr between 32 and 33 because of the positive slope of 00(t)'within that interval and less than wr between 33 and 34 due to due to the corresponding negative slope of '00(1). With waveform is shown the time tk of each positive-slope `zero crossing initiating an asynchronous sampling period, the boundaries of each asynchronous sampling period, and the net total of quantization-element interfaces Aqk crossed during each asynchronous sampling period. Each corresponding time tsk at which a C2(t) trailing edge initiates a synchronous sampling period is shown with the waveform of C20). The manner in which the phase demodulator 3 responds to the eo(t) waveform shown will be discussed in the following text.

DIGITAL PHASE DEMODULATOR The digital phase demodulator 3 receives as inputs the phase-modulated sinusoidal carrier e(t) of phase 0(t) defined by Equation 31, along with the clock signals C1(t) and C20). This component is a sampled-data device `which quantizes the phase angle o(t) with a quantizing width 21r&m electrical radians and, consequently, quantizes the shaft angle 0(t) with a quantizing width 21r/(mvz) mechanical radians. The z'th synchronous sampling period begins at the time ts, when the iirst C2(t) pulse terminating at least an interval re after the time t, of the ith positive-slope zero crossing of eo(t) is last true; is, is identified by a zero-crossing detector 5 which is responsive only when o(t) 0. If the phasedemodulator should respond to a too-fully truncated C2(t) pulse when the phase angle O(t) is marginal, a design feature of the demodulator prevents any permanent output error from developing; any uncertainty due to truncation in one sampling period is vautomatically compensated in the following sampling periods.

Two incremental output signals are generated by the phase demodulator, A0o+(t) and A60+(t). To define these signals, let the shaft and phase angles 0(t) and 0(t) lie within resolution element q(t1) at time t1 and within resolution element q(t1+1) at time t1+1. If the shaft angle 0(t) moves to a more counterclockwise resolution element during the asynchronous sampling period z' extending from ti to n+1, the first q(ti+1-q(ti) pulses of C1(t) during synchronous sampling period i|1 are emitted at the output A00+(t). Similarly, if 00(1) moves to a more clockwise resolution element during the period from t1 to n+1, the last q(ti)-q(t1+1) pulses of C1(t) during synchonous sampling period i are emitted at the output AGO-(t). Such operation is in accordance with Equations 15a, b and 16a, b.

The digital phase demodulator determines phase variation by measuring equivalent time displacement. The necessary relationship between phase and time can be established by iirst noting from Equation 39 that If 0001) lies within the resolution element q(ti), then By substituting the value of 00(11) from Equation 40 into Relation 41 and employing solutions for wr and o from Since is, can be defined as the time when a C2(t).pulse is last true at least an interval fre after ti, it follows from Relations 42 and 43 that Through solution for q01), successive substitution of the values k and k+1 for i, and subtracting, there results Aqk=q(fk+1)1(k)f=[(s1 +m1')-s k+1 ]/T (45) This equation states that the absolute value of Aqk` equals the number of successive periods of duration -r between the times tsk-Fmr and tsg-i-m-r. The sign of Aqk is positive if 13111.11) occurs before tsk-l-m-r and negative if the converse situation exists.

Equation 45 is mechanized in the digital phase det modulator. The contents of one of the m-state cyclic period counters 7 or 8 are set to l by the iirst C10) pulse after each time tsk. Thereafter that counter continues to count C10) pulses, recycling to 0 at the time It follows that the number of C10) pulses between tgk and ts(k+1) equals Aqk. A motion detector 9 directs all of these selected C10) pulses to the output Moi-0) 1f ts(k+1) fgk OI' t0 the Output AO`() if gk fs(k+1).

'I'he two identical period counters 7 and 8 employed in the demodulator are started alternately by a counter selector 6. This arrangement is necessary because counterclockwise shaft rotation, which causes both 000) and 1:00) to increase, can result in the condition Relation (47) requires period count k+1 to begin before period count k is complete 'and the counter involved has recycled to for the necessary interval r.

This requirement is met by the alternate use of two period counters.

ZERO-CROSSING DETECTOR The zero-crossing detector 5 receives as inputs the lphase-modulated sinusoidal transducer output e00) and the clock signal C). This component converts the asynchronous signal e00) into the logical output signals X010) and X020) with transitions synchronized to trailing edges (i.e., l-to-O jumps) of C20), thereby permitting fully synchronous operation of the remainder of the phase demodulator. The positive-slope zero-crossing signals X010) and X020) initiate counting by one of the period counters 7 or 8 by assuming the state for a single clock period fr beginning at times t1(i 0), i.e., with the iirst l-to-O transition of C20) occurring more than an interval re after' each zero crossing of co0) for which 00) 0.

As shown in FIG. 3, the trigger T101 is connected to go true (i.e., to assume the output state T1010)=l) whenever e00)0 but to remain false otherwise. Flipflop F101 assumes the same logical state as T101 in response to the iirst l-to-O transition of clock signal C20) .to occur at least an enabling interval Ire after T101 changes state. One clock period r later, the state of F102 becomes the same as that of F101. The normal output of flip-flop F101 is the zero-crossing detector output X010); the complement output of ip-iiop F102 is the detector output X020).

The logic equations governing operation of the zerocrossing detector 5 are listed below: T1' 101=e0, Trigger T101 input equation Flip-Hop F101 input equations Flip-ilop F102 input equations Output equations.

waveforms show the response of the phase demodulator v to the specific phase-shift transducer output signal e00) shown in FIG. 2 at 30. For reference, the signals C10), C20), and X10) which appear at 11, 12, and 13 in FIG. 2 are also shown at 67, 75, and 76, respectively, in FIG. 5. As before, the time tsk(kl) at which each synchro nous sampling period begins is shown with C20) at 12.

Since T101(l)=1 Whenever the phase shift transducer output e00)0, T1010) goes through aO-to-l transition at the start ik of each synchronous sampling period. This signal controls the response of flip-flop F101 at 78 to C20) pulses. The signal F1010), in turn, controls vthe response of flip-flop F102 at 79 to C20) pulses.

When T1010) goes true at 35, F101 responds to the 1to0 transition of C20) at 518 by assuming the same true state at 37. One clock period fr later, the C20) trailing edge at 59 causes the true state of flip-flop F101 to shift to F102 at 39.

At 36, T1010) goes false when e00) becomes negative. As before, at the next C20) trailing edge 60 at least re later, the logical state of trigger T101 shifts to ip-flop F101 at 38. Similarly, at the next C20) trailing edge 61 the false state of F101 shifts to F102 at 40.

crossing of e00) for other components of the phase demodulator 3.

COUNTER SELECTOR 6 The counter selector 6 receives signal inputs X010) and X020) from the zero-crossing detector 5. Whenever these inputs are simultaneously true, the counter selector generates a false pulse alternately at one or the other of the two outputs X000) or X000). Both outputs are nor- -mally true.

As shown in FIG. 3, the inputs, of the nand-gates G201 and G2M02 are connected to X010), to X020), and to F2010) or F2010). Each gate generates a false output when, and only when, X010) and X020) are simultaneously true, and the gate is enabled by the output of F201 to which it is connected. The ip-op F201 is connected to toggle on each 1-to-O transition of X020). Thus each nand-gate is disabled as soon as it emits a false pulse and remains so until a false pulse has been emitted by the other nand-gate; consequently, these nand-gates generate false output pulses alternately. As FIG. 3 indicates, the outputs of the gates G201 and G202 constitute the outputs X000) and X000), respectively, of the counter selector 6.

The logic equations governing operation of the counter selector 6 appear below:

TF201= 02, Flip-iiop F201 input equations omar-:1,

typical instances, X010) and X020) are simultaneously I true in consecutive intervals from 37 to 39 and from 62 to `63. For the duration of each such interval, a false output pulse is generated at either of the normally true 'transition at 39 causes flip-flop F201 to toggle to the false state at 41; the following O-to-l transition of F1020) at 63 then causes flip-flop F201 to again toggle to the true state at 64. This sequence is continuous.

Since the signal F2010) is true during the first interval shown in which Xp1(t)Xp2(t)=1, i.e., from 37 to 59, a false pulse 43 is emitted at Xe1,(t) (note that m is illustrated in FIG. and that Xpz would have the complementary levels, therefore, during the period from time t=0 to period 39, Xpz would be at the 1 level); conversely, the false state of F2010) during the second such interval from 62 to `63 causes a false pulse 46 to be emitted at Xeb1t). False pulses continue to be emitted alternately at Xe(t) and X1,1,(t) as shown at 65 and 66.

PERIOD COUNTERS 7 AND 8 The input and output connections to the two period counters 7 and 8 are shown by the logic diagram in FIG. 3. Period counter 7 starts to count C1(t) pulses when the normally true input Xe(t) goes false for an interval including one C1(t) pulse. The normally false output X050) of this counter goes true as soon as Xe(t) goes false and remains true for a period (m-1)r after the trailing edge of the C1(t) pulse cited, where the integer m is the number of internal states of the counter.

The number m of internal states of each period counter must equal the number of C1(t) pulses occurring during each cycle of the reference carrier e1(1). Because a C1(t) pulse must trigger each zero crossing of both the reference and quadrature carriers er(t) and c1110), m must be an integral multiple of 4. Conventional procedures are available for designing an m-state counter to meet these re quirements. (Ref.: Montgomery Phister, Jr., Logical Design of Digital Computers, pp. 117-121.)

Since the total number of resolution elements per shaft revolution (i.e., per 2r mechanical radians) is mn, where n is the speed of the phase-shift transducer 4 employed, considerable versatility can be attained through appropriate counter design to provide a resolution-element Width equal to a standard angular measurement unit in applications Where this feature is required. Some values of mn necessary to obtain standard resolution-element widths are shown in Table l, along with corresponding prime factors; each value of mn shown is divisible by 4. Selection of a transducer-and-counter combination to obtain a given standard resolution-element width requires that all of the prime factors shown for that resolution be apportioned to two products, one equal to the transducer speed n, and the other equal to the number of periodcounter states m. A variety of apportionments can be made as long as the resultant lvalue of m is an integral vmultiple of 4. Even in the case of the widest resolution TABLE L-STANDARD RESOLUTION ELEMENTS PER REVOLUTIO Resolution Elements per Revolution, 77m

Resolution-Element Width Prime Factors of mu 1.00 degree .00 are second Cyclic counters with 21r states, where the integer j 1, are generally more eicient than other counters in terms 12 of internal states per logic element. Although the number of transducer speeds which can be used to yield a standard resolution-element Width is reduced by employing such a counter, where either this condition or anonstandard resolution-element Width is acceptable, this type of counter can be employed. The design of a counter in which the number of internal states is for an arbitrary number of stages j will be described in the following text. The value j=2 will then be assigned to obtain a value of m corresponding to the number of C1(t) pulses shown per cycle of e ,(t) in FIG. 2.

The logic diagram of period counter 7 and/or 8 is shown in FIG. 4, both counters being identical in construction and operation. Period counter 7 is a j-stage straight-binary counter with contents defined by the equation l-l 0.o): F 1 ioni 30 (5 which, once enabled, counts C1(t) pulses and recycles to Ca(t)=0 in response to the next C1(t) pulse upon reaching saturation. Similarly, the contents of period counter 8 are The basic unit of the counters 7 and 8 shown in FIG. 4 is the flip-flop doublet typified by F3111 and Fm. The output of such a doublet is the normal output of the highest-order Hip-flop, in this case F302. The first doublet is triggered by C1(t); each other doublet is triggered by the output of the preceding doublet. Both enabling inputs of the lowest-order Hip-flop of the rst doublet are driven by the mand-gate G3111; the enabling inputs of the lowestorder flip-flop of each remaining doublet are permanently connected to a signal having the fixed logical value 1. Obviously, only a counter with an even number of stages can be synthesized entirely of flip-flop doublets. If an odd number of stages is required, a single stage such as F3011+1 in FIG. 4 is added at the output. Counters composed of flip-Hop doublets require no more logic elements than a conventional ripple counter of the same capacity, yet have only approximately half the settling time.

Operation of the period counter 7 is controlled by the gate G3111. This nand-gate has as inputs both the normally true enabling signal Xc1,(t) and the complement output of each flip-flop in the counter. The output of gate G3111 constitutes both the period-counter output X1,,(t) and the enabling inputs for flip-flop F3111. Thus when Xc(t)=1 for a single period of C2(t), the counter is enabled by the signal G3111(t)=1 and continues to count C1(t) pulses cyclically until C(t) returns to 0. The counter then remains in this state until X1,(t) again goes false for a single C1(t) pulse. The cycle described repeats continuously.

The logic equations governing operation of period lcjoilmter 7 when two counting stages are employed appear e ow:

TF3 01 :Cb Flip-110D F301 input equations Gaol) 1F3 02:17 301, TF302= C1, FhP'OP F302 Input equatlons XcazGaolzamFBozXea Gate and output equation Period counter 8 is identical to period counter 7; in the logic diagram and logic equations, however, XebU) replaces XeaU), Xc1,(t) replaces Xc(t), and is added to the index of every logic element employed. .Thus the logic equations governing operation of period counter 8 Xcb=G401^=F401F402XebL Gate and output equations.

} Flip-flop F402 input equations Logic equations for period counters'having a larger number of stages can also be written on the basis of the preceding design principles.

The logical waveforms and states of both period counters are shown in FIG. 5. As shown at 48, the normally false output Xa(t) of period counter 7 responds to the Xe(t) pulse at 43 by going true at 47. At 49, the contents Ca(t) of period counter 7, initially 0, start to increase as kC1(z) pulses, are counted. The counter-active signal Xc(t) remains true until, n response to the C1(t) pulse at 69, the contents `C(t) recycle to and Xa(t) again goes false at 80. This cycle is repeated in response to the Xe,(t) pulse at 65 and to those which succeed it.

As shown at 50, the normally false output Xcb(t) of period counter `8 is similar to Xc(t) but responds to Xeb(t) at 64. The Xeb(t) pulse at 46 causes Xcb(t) to go true at 51, thereby causing the contents Cb(t) of counter 8 shown at 52 to increment in response to the C1(t) pulses from 70 to 71. When the C1(t) pulse at 71 causes period counter 8 to recycle to Cb(t)=0, Xcb(t) again goes false at 84. This cycle is repeated in response to the Xeb(t) pulse at 66 and to those which succeed it.

The time tgk at which each counting cycle ends is identified adjacent to the presentations of the instantaneous contents of period counters 7 and 8 at 49 and 52. This function is defined by Equation 46.

MOTION DETECTOR 9 The logic diagram of the motion detector 9 is the final one to appear in FIG. 3. This component receives the signalsv Xc(t) and Xcb(t) from period counters 7 and 8, respectively. In functioning, it emits every C1(t) pulse which occurs when Xca(t) and Xcb(t) are simultaneously true at the output A0o+(t) and emits every C10) pulse which occurs when XcaU) and Xcb(t) are simultaneously false at the output A60-(t).

As shown in FIG. 3, the motion detector 9 utilizes the two mand-gates G501 and Gm with associated logical inverters to provide the required response. The logic equations governing operation of the motion detector follow:

Waveforms ofthe normally false output signals ABO-PU) and A-(t) of the motion detector appear at 53'and 55 in FIG. 5. Although Xca(t)i=Xcb(t) =0 from y80 to 51 and from 84 to 83, a pulse output is not emitted at AGU-(t) because no C1(t) pulse occurs in either of these intervals. From 85 to 81, Xca(t)= Cb(t)=1; in this interval a single C1(t) pulse 72 occurs and is emitted at output A0o+(t) as shown at 54. Finally, Xc,(t)i=Xcb(t) =0y in the interval from 86 to 82, during which two C1(t) pulse-s occur at 73 and 74. Both of these pulses are emitted at output A0C-(t) as shown at 56 and 57.

As a final summary to the operation of the position encoder system, the intervals of five contiguous asynchronous sampling periods, each initiated at a time tk (lkS),

l Gate equations Inverter equations Output and inverter equations.

have been transferred from 30 in FIG. 2 to appear with i A0o+(t) at 53 in EFIG. 5. The net total Aqk of the quantization-element interfaces crossed by the shaft angle 0(t) during each such sampling period is also shown. Similarly, the intervals of the corresponding five synchronous sampling periods, each initiated at a a time tsk (lkS) shown at 12 in FIG. 2, appear with output ABO-(t) at 5i5. The total numbers pk+ and pkof C10) pulses emitted at outputs A00i'(t) and A0"=(t), respectively, during each synchronous sampling period are also shown at 55. In every case, Aqk, pkt', and pk are related as predicted by Equations 15a, b and 16a, b.

Although the invention has been illustrated and described in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only by the terms of the appended claims.

I claim:

1. A position encoder comprising in combination:

a crossing detector having as an input a zero-crossing phase-modulated signal, modulated as a function of input position, said detector responsive to said zero crossings of said signal providing two output signals having true and false levels at times dependent upon said modulated signal;

a counter selector having two normally true level output signals responsive to simultaneous true level signals from said crossing detector for alternately changing to a false level said output signals;

a source of clock pulses;

a first and second counter each having a normally falselevel output signal and each being responsive to one of said counter-selector false-level output signals for providing a true-level signal indicative of a predetermined number of counted clock pulses; and

a motion detector responsive to said first and second counters providing pulses from a specified set of pulses from said clock source at a first output terminal when the signals from said counters are simultaneously true and for providing pulses from said clock source at a second output terminal when the signals from said counters are simultaneously false.

2. A position encoder comprising in combination:

means providing periodic clock pulses;

a reference signal generator providing a periodic reference signal as a function of said clock pulses; means phase modulating said reference signal as a function of position;

means detecting the crossing of a predetermined level by said modulated signal providing a first and second outlet signal at the time of said crossings;

selector means responsive to said first and second output signals alternately providing as a function of one of said output signals a first and second enabling signal;

a first counter having a normally first level output signal responsive to said first enabling signal to provide a second level output signal indicative of a number of counted clock pulses less than a predetermined number; v

a second counter havinga normally first level output signal responsive to said first enabling signal to provide a second level output signal indicative of a number of counted clock pulses less than a predetermined number; and f motion detector means responsive to said counters for providing a clock pulse at a first output when the output signals from said counters are simultaneously at said first level and for providing a clock pulse at a second output when the output signals from said counters are simultaneously at said second state.

3. The combination recited in claim 2 wherein said means detecting the crossing of a predetermined point is comprised of:

a trigger adapted to provide first complementary signals indicative of whether said phase modulated ref- 15 erence signal is above or below said predetermined level;

a first flip-flop responsive to said first complementary signals and said clock pulses yproviding second complementary signals, one of said second signals being a first output signal; and

a second flip-flop responsive to said second comple mentary signals and said clock pulses providing a second output signal delayed one clock period from said first output signal.

4. The combination as recited in claim 3 wherein said selector means comprises:

a flip-flop responsive to said second output signal for providing complementary output signals;

rst gate means responsive to said first and second output signals and one of said complementary output signals providing said first enabling pulse; and

second gate means responsive to said first and second output signals and the other of said complementary: output signals'providing said second enabling pulse.

S. The combination as recited in claim 4 wherein said counter means is comprised of an m-state counter where the number m equals the number of clock pulses occurring during each cycle of said reference signal.

6. The combination as recited in claim 5 wherein said counter means is adapted to count Inl-1 pulses and to recycle to zero upon receipt of the mth pulse.

7. Apparatus for encoding a phase-modulated periodic information signal comprising in combination:

means responsive to said phase-modulated periodic information signal for producing enabling pulses, at least one such pulse being produced during a cycle of said phase-modulated periodic signal and at a predetermined level thereof and a plurality of enabling pulses being produced during successive cycles of said signal; first and second pulse generating means, each having an output and an input, and each for producing at its output a pulse of a desired signal level and of a single predetermined duration in response to receipt of one of said enabling pulses at the input thereof; pulse distributing means for transmitting said enabling pulses alternately to said inputs of said first and second pulse generating means; detection means responsive to pulses at said outputs of said first and second pulse generating means, said detection means having first and second output terminals for producing an output pulse at said first output terminal when said first and second pulse gen- `1&3 erating means provide concurrent pulses of aj predetermined combination of signal levels and for producing a pulse at said second output terminal when said first and second pulse generating means provide pulses of a second predetermined combination of signal levels. 8. Apparatus according to claim 11 further comprising in combination: a source of periodic clock pulses, said phase modulated signal having a period which is a function of a predetermined number of Said clock pulse periods and said pulses at said rst and second output terminals having a period which is a function of said predetermined number of said clock pulse periods.

9. Apparatus for encoding a phase-modulated information signal comprising in combination:

means responsive to said phase-modulated signal to produce a plurality of enabling pulses during at least a plurality of successive crossings of a predetermined reference level of the phase-modulated signal for detecting changes in phase lthereof; first and second pulse generating means, each having an output and an input, and each for producing at its output a pulse of a desired signal level and of a single predetermined duration in response to receipt of one of said enabling pulses at the input thereof;

pulse distributing means for distributing alternate enabling pulses to said first and second pulse generating means;

detector means having first and second detector output terminals and responsive to a predetermined period of said concurrent output pulses of said pulse generating means for producing a pulse at said first dector output terminal and responsive to absence of pulse output beyond a predetermined minimum period t-o produce a pulse at said second detector output terminal.

References'Cited UNITED STATES PATENTS Brook 340-347 MAYNAR-D R. WILBUR, Primary Examiner G. EDWARDS, Assistant Examiner

Images