US3487386A

US3487386A - Shiftable counter using a magnetic core as the counting element

Info

Publication number: US3487386A
Application number: US614897A
Authority: US
Inventors: Ronald A Kokesh; Donald J Rotier
Original assignee: DONALD J ROTIER; RONALD A KOKESH
Current assignee: DONALD J ROTIER; RONALD A KOKESH
Priority date: 1967-02-09
Filing date: 1967-02-09
Publication date: 1969-12-30
Anticipated expiration: 1986-12-30

Description

Dec. 30. 1969 R. A. KOKESH ET AL 3,487,386

SHIFTABLE'COUNTER USING A MAGNETIC CORE AS THE COUNTING ELEMENT Filed Feb. 9, 1967 I l I I I I W410 ,4. (042-674 BY 004 40 d Ear/2 Mal/W United States Patent US. Cl. 340-174 7 Claims ABSTRACT OF THE DISCLOSURE Electrical control apparatus including a saturable magnetic core having a plurality of stable states wherein the first and last of the plurality of stable states constitute the saturated limits of a substantially rectangular hysteresis loop, at least a count winding and a reset winding magnetically coupled to said core with input means connected to the count winding whereby coercive current pulses are selectively provided to the count winding to sequentially drive the core through the plurality of stable states from the first to the last stable state, count shift means connected to the input means and adapted to be selectively enabled to vary the number of coercive current pulses necessary to drive the core between the first and last stable states, output means connected to the core for providing a signal when the core is driven to the last stable state, and reset means connected to the reset winding for driving the core from the last stable state to the first stable state. In addition, switch means are provided including a capacitor and at least first, second and third impedance means, the switch means and the first impedance means being serially connected across the source of energy, with the capacitor and the second impedance means serially connected across the first impedance means and the third impedance means and the count winding being serially connected across the second impedance means so that when the switch means is switched on, the capacitor will charge, and when the switch means is switched off, the capacitor will discharge through the count winding to provide a coercive current pulse for changing the stable state of the core.

This invention is concerned with control apparatus, and more particularly with an electro-magnetic counter circuit, the total count of which is shiftable or variable.

Briefly described, the apparatus of this invention includes a saturable magnetic core of high flux retentivity, and having a plurality of stable states, the first and last of which are the saturated limits of a substantially rectangular hysteresis loop. Wound on the core are a count winding and a reset winding. An input circuit is connected to the reset winding, and includes a capacitor such that when an input signal is present the capacitor will charge through the count winding to provide a coercive current for stepping the core through its plurality of stable states, and upon removal of the input signal the capacitor will discharge.

A count shift circuit is connected to the input circuit, for varying the total number of input pulses required to drive the core from its first to its last stable state. The count shift circuit comprises circuit members which when actuated provide a bucking voltage in the discharge path of the input circuit capacitor to prevent complete discharge, thus varying the coercive current fiow through the reset winding when the capacitor charges.

An output circuit, which can be in the form of an amplifier, is controlled by being connected to the count winding. When the core reaches its last saturated state, the impedance in the count winding changes sutficiently to provide a signal to the output circuit. The output cir- 3,487,386 Patented Dec. 30, 1969 cuit can feed its signal directly to a load, or can provide a signal to a latch circuit, which can be comprised of another amplifier. The latch circuit provides a continuous output, while the output circuit provides a pulse outlet. A latch inhibit circuit is also provided, which can be used either to break a latch, or to prevent a latch when an output pulse occurs.

The reset winding is connected to the output of the output circuit so that each time an output pulse appears, coercive current flows through the reset winding to reset the core to its first stable state, to be ready for the next count sequence. An alternate reset circuit is also connected to the reset winding to allow resetting of the core at any time prior to the output pulse.

In the drawings:

The single figure of the drawings is a schematic representation of a circuit embodying the apparatus of this invention, as it would appear on a circuit board.

Because the apparatus of this invention lends itself Well to circuit board mounting, and because the apparatus is particularly useful when similar circuits can be interchanged, such as by the use of circuit boards, the preferred embodiment of the single figure of the drawing has been shown mounted on a circuit board. It is not intended that the scope of this invention be limited to such use of the apparatus of this invention.

In the single figure of the drawing there is shown a circuit board 10 on which is mounted a connector strip 11. On strip 11 there are mounted a plurality of terminals 12-23. Terminal 12 is adapted to be connected to the positive terminal of a source of energy (not shown). Terminal 13 is a direct input terminal to a latch circuit to be described below. Terminal 14 is a pulse output terminal from an output circuit to be described below. Terminal 15 is an input terminal in OR circuit with terminal 13. Terminal 16 is a count shift signal input terminal connected to a count shift circuit to be described below.

Terminals

17 and 18 are connected in OR circuit and are count signal input terminals connected to a count input circuit to be described below. Terminal 19 is adapted to be connected to the negative terminal of the source of energy. Terminal 20 is a reset signal input terminal connected to an alternate reset circuit described below. Terminal 21 is a latch output terminal connected to the output of a latch circuit to be described below. Terminals 22 and 23 are connected in OR circuit and are latch inhibit signal input terminals connected to a latch inhibit circuit to be described below.

There is also shown a load 25. Load 25 can be connected between terminal 19 and output terminal 21. When terminal 21 is connected to either of terminals 13 or 15, the latch circuit to be described below will provide a continuous latched output. Load 25 can also be connected between pulse output terminal 14 and, for example, terminal 19.

Mounted on board 10 there is shown a magnetic core 30 having wound thereon a count winding 31 and a reset winding 32. Count winding 31 is connected between a pair of

junctions

34 and 35. A resistor 36 is connected between junction 34 and terminal 12. Another resistor 37 is connected between junction 35 and terminal 12. A capacitor 39 is connected between junction 35 and another junction 41. A resistor 38 is connected between junction 41 and terminal 12.

Also mounted on board 10 is a transistor 45 having an emitter 46, a collector 47 and a base 48. Collector 47 is connected to junction 41. Emitter 46 is connected to terminal 19. A resistor 49 is connected between base 48 and terminal 19. A capacitor 51 is also connected between base 48 and terminal 19. A resistor 52 is connected between base 48 and terminal 18, while another resistor 53 is connected between base 48 and terminal 17.

There is also mounted on board a transistor 55 having an emitter 56, a collector 57, and a base 58. Emitter 56 is connected to terminal 19. Collector 57 is connected through a resistor 54 to junction 41. Base 58 is connected through a resistor 61 to terminal 19, and through a resistor 62 to terminal 16.

Also mounted on board 10 is a transistor 65 having an emitter 66, a collector 67 and a base 68. Emitter 66 is connected to terminal 12. Base 68 is connected to junction 34. Collector 67 is connected to a lead 70. A diode 71 is connected between lead 70 and a junction 73. Junction 73 is connected to terminal 14. A resistor 72 is connected between junction 73 and another junction 74.

Also mounted on board 10 are a pair of transistors 75 and 85. Transistor 75 has an emitter 76, a collector 77 and a base 78. Transistor 85 has an emitter 86, a collector 87 and a base 88. A diode 79 is connected between junction 74 and base 78. A resistor 81 and a capacitor 84 are connected in parallel between base 78 and emitter 76. Emitter 76 is also connected to terminal 19. Collector 77 is connected through a resistor 82 to base 88. Base 88 is connected through a resistor 83 to emitter 86. Emitter 86 is connected to terminal 12. Collector 87 is connected to terminal 21. A diode 89 is connected between collector 87 and terminal 19.

Also mounted on board 10 is a transistor 95 having an emitter 96, a collector 97 and base 98. Emitter 96 is connected to terminal 19. Collector 97 is connected through diode 79 to base 78 of transistor 75. Base 98 is connected through a resistor 99 to emitter 96. Base 98 is also connected by a resistor 101 to terminal 22, and by resistor 102 to terminal 23.

Also mounted on board 10 is a transistor 105 having an emitter 106, a collector 107 and a base 108. Emitter 106 is connected to terminal 19. Base 108 is connected through a resistor 109 to emitter 106. Base 108 is also connected through a resistor 123 to a junction 122. Junetion 122 is connected to terminal 20. Junction 122 is also connected through a resistor 124 to base 98 of transistor 95. Also mounted on board 10 is a transistor 115 having an emitter 116, a collector 117 and a base 118. Base 118 is connected through a resistor 111 to collector 107 of transistor 105. Base 118 is also connected through a resistor 119 to emitter 116. Emitter 116 is connected to terminal 12. Collector 117 is connected by a serial combination of a resistor 120 and a diode 121 to lead 70.

To best understand the following description of the operation of this embodiment of the invention, it is preferable to relate the above described individual components to broader functional circuitry. It should be understood that the following functional circuit descriptions will not include all of the above mentioned components, because many are obvious to those skilled in the art, as for example, bias resistors, by-pass capacitors and input impedances.

Core 30 comprises a counting core due to its multiplicity of stable states and its substantially rectangular hysteresis loop. It is well known that the impedance of a count winding such as winding 31 on a core such as core 30 will vary perceptively as core 30 changes from one saturated limit of its hysteresis loop to the other saturated limit. It is also well known that the impedance change is very small as core 30 is stepped on its hysteresis loop between the two saturated limits. Therefore, when the core reaches its last saturated limit, the major change in impedance can be used to provide an output signal.

A count input circuit is used to provide coercive current to count winding 31 for stepping core 30 from its first to its last saturated state. The count input circuit comprises

resistors

36, 37 and 38, and capacitor 39, in combination with a switch here shown as NPN transistor 45.

The apparatus of this invention also uses a count shift circuit for varying the number of steps or counts between the saturated limits of the hysteresis loop of core 30. The count shift circuit includes another switch, here shown as NPN transistor 55, which is connected to the count input circuit.

An output circuit is connected to winding 31 for providing an output pulse when the impedance of core 30 changes due to core 30 reaching its last saturated state. Here the output circuit is shown as an amplifier comprising PNP transistor 65.

There is also shown a latch circuit for providing a continuous output in the presence of the pulsed output from the output circuit and with load 25 connected as previously described. The latch circuit comprises another amplifier including NPN transistors and PNP transistor 85.

A latch inhibit circuit is provided to break or prevent latching when desired. The latch inhibit circuit comprises another switch here shown as NPN transistor 95.

A reset circuit is provided by connecting winding 32 between the output terminal of the output circuit comprising transistor 65, and a terminal on the source of energy. Thus whenever an output pulse appears, coercive current is provided through reset winding 32 to automatically drive core 30 from its last to its firstsaturated state.

Finally, there is provided an alternate reset circuit comprising an NPN transistor 107 and a PNP transistor 115.

Transistors

107 and 115 are connected between terminal 20 and reset winding 32 so that a reset pulse at terminal 20 will provide coercive current through reset winding 32 to reset core 30 to is first saturated state.

For the following explanation of the operation of the circuit of the single figure of the drawing it will be assumed that strip 11 on board 10 has been plugged into a suitable connector in an operably electric circuit. The connections will be such that a source of energy has a positive terminal connected to terminal 12 and a negative terminal connected to terminal 19. For purposes of the following explanation it will be assumed that load 25 is connected between terminals 21 and 19, and that terminal 21 is connected to terminal 15.

Because the position on its hysteresis loop of core 30 is not known at the time of power turn-on, it is advisable to first provide a positive reset pulse at terminal 20. This reset pulse will be felt at junction 122 where it passes in two directions through resistor 123 and through resistor 124. The positive pulse felt through resistor 123 will be felt at base 108 of transistor to bias transistor 105 on. When transistor 105 is turned on, current will flow from terminal 12, through

resistor

119 and 111, then from collector 107 to emitter 106 of transistor 105, and then out to terminal 19. The voltage drop across resistor 119 will cause base 118 to be more negative than emitter 116, to thus bias on transistor 115. The turnon of transistor will cause a current flow from terminal 12, from emitter 116 to collector 117 of transistor 115, through diode 121, resistor 120, lead 70, reset winding 32, and on to terminal 19. This coercive current flow through reset winding 32 causes core 30 to be driven to its first stable state, which is the first saturated limit of its hysteresis loop. Note that the current flow at lead 70 would also pass through diode 71, resistor 72, diode 79, resistor 81, and out to terminal 19. The resulting voltage drop across resistor 81 would tend to bias on transistor 75 to turn on the latch circuit, if the latch inhibit circuit comprising transistor 95 was not also enabled. Therefore, as previously stated, the reset signal at terminal 20 also passes from junction 122 through resistor 124 to reach base 98 of transistor 95 to bias on transistor 95. When transistor 95 is on, junction 74 is shorted to terminal 19 through collector 97 and emitter 96. Therefore, current flowing to junction 74 passes directly out to terminal 19 rather than passing through diode 79 to the latch circuit.

Now that core 30 is reset, the count sequence can commence. Assume first that the count shift circuit comprising transistor 55 is not enabled, that is, there is no signal at terminal 16. Now when a positive pulse is felt at either of

terminals

17 or 18, it will pass through the respective resistors 53 or 52, to positively bias base 48 to switch on transistor 45. When transistor 45 is on, current will flow to charge capacitor 39 to the polarities shown. Because resistor 38 is chosen to be much larger than resistor 37, the current flow through it can be substantially neglected. Therefore, the charging paths for capacitor 39 are. from terminal 12, through resistor 37, through capacitor 39, from collector 47 to emitter 46 of transistor 45, and out to terminal 19; and from terminal 12, through resistor 36, through winding 31, and then again through capacitor 39 and transistor 45 to terminal 19. Capacitor 39 can be chosen such that the maximum charge is determined by the RC time constant of resistor 37 and capacitor 39, or by the pulse width of the input signal at

terminal

17 or 18. In either case, when the input signal at

terminal

17 or 18 ceases, transistor 45 will turn off and the charging path for capacitor 39 will be closed. Capacitor 39 will now discharge through two paths. A first path involves a serial combination of resistors 37 and 38. The second path involves a serial combination of count winding 31, resistor 36 and resistor 38.

The charge current flow through count winding 31 will move core from its first stable state to a second stable state along its hysteresis loop. A continuing number of such counting steps, including the input pulse, the charge of capacitor 39, and the discharge of capacitor 39, will each time move core 30 a predetermined portion of the way along its hysteresis loop to reach its last stable state, which is the second or last saturated limit of its hysteresis loop. Proper selection of

resistors

36, 37 and 38, as well as count winding 31 and capacitor 39, determines the number of counts or pulses necessary to drive core 30 into saturation.

During the last count sequence, when core 30 is driven into its last state of saturation, the impedance of count Winding 31 will drop sharply. The serial combination of resistor 36 and the impedance of count winding 31 now offers a total resistance less than that of resistor 37. Now when the next count signal appears at terminal 17 or 18 to switch on transistor 45, a much greater current will flow through resistor 36 and count Winding 31. The resulting higher voltage drop across resistor 36 biases base 68 more negative than emitter 66, to turn on transistor 65.

The turn-on of transistor 65 has three major effects. It will cause a reset current to flow to return to core 30 to its first saturated state, it will cause an output pulse to be felt on terminal 14, and it will cause a turn-on signal to be felt on the latch circuitry.

Describing first the reset current, it will flow from terminal 12, from emitter 66 to collector 67 of transistor 65, through lead 70, through reset winding 32, and out to terminal 19 to provide a coercive current which will drive core 30 back to its first saturated state automatically. At the same time, current will flow through lead 7 0, through diode 71, and through junction 73 out to terminal 14. This otuput pulse, which will be a pulse because of the automatic reset of core 30 that will raise the impedance of winding 31 to remove the bias which keeps on transistor 65, can be used if desired by connecting a load to terminal 14.

At the same time the reset and output currents above described flow, a current will flow from junction 73, through resistor 72 and junction 74, through diode 79, through resistor 81, and out to terminal 19. The resulting voltage drop across resistor 81 will make base 78 more positive than emitter 76 to turn on transistor 75. This will in turn cause a current flow from terminal 12, through

resistors

83 and 82, from collector 77 to emitter 76 of transistor 75, and out to terminal 19. The resulting voltage drop across resistor 83 will make base 88 more negative than emitter 86 to turn on transistor 85. Therefore, an output current will flow from terminal 12,

from emitter 86 to collector 87 of transistor 85, and out to terminal 21. Because terminal 21 has been described as being connected to terminal 15, the output current will flow continuously because a portion is fed back through terminal 15 and resistor 92 into junction 74, where it passes through diode 79 to keep transistors 75 and biased on continuously.

Assuming now that it is desired to remove the output current, the latch inhibit circuit is energized by providing a positive pulse at either of terminals 22 or 23. The positive pulse will pass through the

repsective resistor

101 or 102, to reach base 98 to bias on transistor 95. When the transistor 95 is on, junction 74 is substantially shorted to terminal 19 through collector 97 and emitter 96 of transistor 95. Thus the bias signal from junction 74 will fiow directly through transistor 95 and will not pass through diode 79 to reach base 78 of transistor 75, and the latch circuit will turn 011?. Note that this latch inhibit circuit, if energized during the count sequence, or the latter portion thereof would have completely prevented turn-on of the latch circuit by shorting junction 74 to terminal 19. This method can be used if it is desired to only have the pulse output at terminal 14 without the output through the latch circuit. Note also that even if the latch inhibit circuit was not energized, but if terminal 21 was not connected back to either of terminals 13 or 15, then the latch circuit would not receive a. continuous bias and the resulting output at terminal 21 would not be continuous, but merely an amplified pulse.

Assume now that for the next count sequence it is desired to shift the count to a higher number, so that more pulses are needed at

terminals

17 and 18 to provide an output pulse. To accomplish this purpose, a permanent positive signal is applied at count shift terminal 16. This signal causes a current flow through resistors 62 and 61, and out to terminal 19. The resulting voltage drop across resistor 61 causes base 58 to be more positive than emitter 56 to bias on transistor 55. Therefore, a continuous current will fiow from terminal 12, through resistor 38, junction 41, resistor 54, from collector 57 to emitter 56 of transistor 55, and out to terminal 19. This will cause a continuous voltage drop across resistor 38. Now, when the count sequence is initiated as described above, during the discharge of capacitor 39 its discharge current path is bucked by the voltage drop across resistor 38 to prevent complete discharge. This has the obvious effect of decreasing the coercive current flow through count winding 31 during the charge of capacitor 39 in the next count sequence. With the decreased coercive current for each count cycle, core 30 will he stepped a smaller amount each time along its hysteresis loop, and it will therefore take a greater number of count pulses before core 30 reaches its last state of saturation. The rest of the circuit operation is as described above, with the only difference being that a greater number of count pulses must appear at

terminals

17 and 18 before an output can be obtained.

In the preferred embodiment of the single figure of the drawing it should be noted that an output from the latch circuit can be directly obtained by providing an input pulse to either of terminals 13 or 15. The pulse will be felt through the

respective resistor

91 or 92, and cause a positive current flow through junction 74 and diode 79, to be felt on base 78 to turn on the latch circuit. If output terminal 21 is connected to either of terminals 13 or 15, the output will be continuous. If terminal 21 is not connected to one of terminals 13 or 15, the output will last as long as the pulse at terminal 13 or 15.

It is apparent that the above described circuit provides a novel shiftable counter capable of providing latched or pulsed outputs, and including the features of latch inhibit, and automatic and alternate reset.

It will also be apparent that the particular configuration of the single figure of the drawing is merely a preferred embodiment and that many other forms can be used without departing from the spirit of the invention.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Electrical control apparatus comprising:

a saturable magnetic core capable of multi-stable operation having a plurality of stable states wherein the first and last of said plurality of stable states are the saturated limits of a substantially rectangular hysteresis loop;

at least a count winding and a reset Winding wound on said core;

input means connected to said count winding whereby coercive current pulses are selectively provided to said count winding to sequentially drive said core through said plurality of stable states from said first to said last stable state;

count shift means connected to said input means and adapted to be selectively enabled to vary the number of coercive current pulses necessary to drive said core from said first to said last stable state;

output means connected to said core for providing a signal when said core is driven to said last stable state;

said input means comprising a source of energy, switch means, a capacitor, and at least first, second and third impedance means;

said switch means and said first impedance means serially connected across said source of energy;

said capacitor and said second impedance means serially connected across said first impedance means; and

said third impedance means and said count winding serially connected across said second impedance means, so that when said switch means is switched on said capacitor will charge and when said switch means is switched otf said capacitor will discharge through said count winding to provide a coercive current pulse for changing the stable state of said core.

2. The apparatus of claim 1 in which said count shift means comprises:

second switch means;

fourth impedance means; and

said second switch means and said fourth impedance means serially connected across said switch means, so that when said second switch means is switched on a bucking current is provided in the discharge path of said capacitor to decrease the coercive current flow through said count winding.

3. The apparatus of claim 2 in which:

said switch means comprises a first semiconductor switching means having first input, output and control electrodes;

said second switch means comprises a second semiconductor switching means having second input, output and control electrodes;

said first input and output electrodes in series circuit with said first impedance means;

said first control electrode connected to means for selectively providing a count signal;

said second input and output electrodes in series circuit with said fourth impedance means; and

said second control electrode connected to means for selectively providing a count shift signal.

4. The apparatus of claim 3 in which said output means comprises:

amplifier means having third input, output and control electrodes;

comprises:

means connecting said reset winding intermediate said third output electrode and a first terminal on said source of energy, so that when said output means comprising said amplifier means is enabled by said core being driven to said last stable state, the output signal from said output means will cause a coercive current flow through said reset winding to reset said core to said first stable state.

6. The apparatus of claim 4 including:

latch means including second amplifier means having fourth input, output and control electrodes;

said fourth input and output electrodes connected in series circuit across said source of energy;

said fourth output electrode adapted to be connected to a load;

said fourth control electrode connected to said third output electrode;

bias means adapted to be connected intermediate said fourth control electrode and said load for biasing said latch means to provide a continuous output signal;

latch inhibit means comprising a third semiconductor switching means having fifth input, output and control electrodes;

said fifth input and output electrodes connected in series circuit between said fourth input and output electrodes; and

said fifth control electrode connected to means for selectively providing a latch inhibit signal, so that when said third switching means is switched on said latch means is disabled.

7. The apparatus of claim 6 including alternate reset means comprising:

fourth semiconductor switching means having six input,

output and control electrodes;

means connecting said sixth input electrode to a second terminal on said source of energy;

means connecting said sixth output electrode to one end of said reset winding;

a reset input terminal adapted to receive a reset signal;

means connecting said sixth control electrode to said reset input terminal; and

means connecting said reset terminal to said fifth control electrode of said latch inhibit means, so that a reset signal on said reset terminal will simultaneously turn on said fourth switching means to provide a coercive current to said reset winding and turn on said third switching means to inhibit said latch means.

References Cited UNITED STATES PATENTS BERNARD KONICK, Primary Examiner K. E. KROSIN, Assistant Examiner US. Cl. X.R.