US3484764A - Symmetrical store array - Google Patents

Description

Dec. 16, 1969 T. R. FINCH ETAL 3,484,764 I SYMMETRICAL STORE ARRAY 3 Sheets-Sheet 1 Filed Nov. 1, 1966 SWITCHES SWITCHES READ TiMlNG men DRIVE THRESHOL CIRCUIT mew COUPLlNG 7. R. F/NCH 5. G'- WAABE'N 14 7'7 ORNE 5 lNl/ENTORS UTILIZATiON CIRCUIT Dec. 16, 1969 T. R. FINCH ETAL 3,484,764

SYMMETRICAL STORE ARRAY Filed Nov. 1, 1966 3 Sheets-Sheet 2 FIG. 4 ,f, I LOOIC INPUT TO I ADDREss DECODINO {Ito I CIRCUIT IIv F/G.5 II I I TIMING FOR WORD I CONTROL CIRCUIT I9 2 t 1:7 I I I i HOD I I I I I I I I k/I WORD LINE CURRENT t; I, I I I I I I SELECTED WORD l I I I -7517 I I I I N I RAIL VOLTAGE l I I l I tI IO l I l I II I I DIODE RAIL Flag I i I I vOLTAOE I I I I l I I I I I Flag II /\IAI I I I READOUT AT I LEAD 73 II!, I I I/I I I I, t t

l I I I F/G/O I I I I SENSE STROBE l 1 I 4 I76 '/I I I I DIGIT LINE DRIvE I I I I I /I TO WRITE II I I FIG. /2 I WORD RAIL CLAMP "I OUTPUT OF UTILIZATION CIRCUIT 74 United States Patent 3,484,764 SYMMETRICAL STORE ARRAY Tudor R. Finch, Basking Ridge, and Sigurd G. Waaben,

Princeton, N.J., assignors to Bell Telephone Laboratories Incorporated, Murray Hill, N.J., a corporation of New York Filed Nov. 1, 1966, Ser. No. 591,237 Int. Cl. Gllb 5/00 US. Cl. 340-174 25 Claims ABSTRACT OF THE DISCLOSURE A selection matrix is combined with a plated wire memory on a symmetrical selection-and-memory-drive basis with respect to the memory readout circuits. Corresponding equipotentially arranged parts of the matrix are coupled to corresponding symmetrically arranged parts of the memory, and the latter memory parts are differentially detected to offset spurious noise signals from both parts of the matrix and the memory against one another. Each of the readout circuits is operated as a folded transmission line in its one of the two symmetrical parts, and each such line has both its input and its output coupled to the same digit detecting circuit to provide an additional order of noise cancellation prior to detection. A dipulse digit writing technique is employed in which the second half-cycle of the digit drive signal occurs subsequent to the trailing edge of the word drive pulse and in the postwrite time guard interval of the memory cycle.

This invention relates to a store system employing a selection matrix to couple drive signals to selectable locations of a memory in the store. The invention is herein described in its application to a magnetic store system.

A store system, sometimes called a memory system, includes a memory per se and the associated memory electronics providing access to selectable memory addresses for reading and writing therein. A memory typically comprises an array of remanent devices such as capacitors, bistable electronic circuit packages, or magnetic devices. As mentioned above, the principles of the present invention are described in terms of a magnetic store system, and in that system the memory devices have substantially rectangular hysteresis characteristics defining two states of oppositely poles remanent magnetization.

Many magnetic store systems in commercial use at the present time employ some form of bistable magnetic device which is operable on a read-write cycle that is measured in microseconds. However, modern data processing systems which use such stores are typically capable of much faster operation. Many data processing systems, but for the limitation of memory operating time, could be readily operated in the submicrosecond range. Certain newer art magnetic devices, such as conductive wires located with magnetic thin film, are capable of operation in the nanosecond range in relatively small memory modules. However, when the memory module size is increased to a practical size many problems are encountered which reduce the signal-to-noise ratio of memory readout. Previous attempts to solve such noise problems have heretofore substantially increased store cycle time to levels which are much greater than one might at first expect from a consideration of the thin film devices alone or the devices in small arrays. Other attempts to solve such problems have increased store cost so much that little practical advantage remains in using such newer art devices.

It is, therefore, an object of the present invention to improve store systems.

It is another object to reduce the cost of store systems.

A still further object is to reduce the operating cycle time of store systems.

A further object isto facilitate the employment of magnetic thin films in store systems of practical size for modern data processing systems.

These and other objects of the invention are realized in an illustrative embodiment thereof wherein a selection matrix is combined with a memory on a symmetrical selection-and-memory-drive basis with respect to the memory readout circuits. Thus, corresponding equipotentially arranged parts of the matrix are coupled to corresponding symmetrically arranged parts of the memory, and the latter memory parts are differentially detected to offset spurious noise signals from both parts of the matrix and the memory against one another. Thus, the store is designed to reduce the generation of possibly signalmasking noise in the first instance; and it is further adapted to offset blocks of such noise against one another, the ,store being arranged so that such noise blocks are all of predictably similar characteristics.

It is one feature of the invention that the extension of the symmetrical concepts, both physical and electrical, of store organization through both the memory and its selection matrix in a cooperative sense permits substantial hardware economies in terms of circuit. elements required, and in terms of physical space occupied, without substantially sacrificing memory operating speed. I

Another feature is that the selection matrix is organized to have the electrical appearance of a substantially constant impedance, with a low capacitive component, to a drive pulse source, regardless of the memory address which is selected for actuation, so that drive pulse rise time is controlled by relatively simple circuits.

The memory includes first and second sets of coordinate drive lines, and it is a feature of the invention that those lines are cooperatively arranged to convert noise and information signals to different transmission modes, respectively, to facilitate discrimination therebetween. Such arrangement is cooperatively employed with the symmetrical design concepts mentioned to provide efficient coupling to drive lines of one of the sets for both drive and detection purposes.

A more complete understanding of the invention and the enumerated features and objects thereof, as well as other features and objects, may be obtained from a consideration of the following detailed description and the appended claims in connection with the attached drawings in which:

FIG. 1 is a diagram partly in schematic form and partly in block and line diagram form illustrating both the physical and the electrical schematic arrangements of a magnetic store in accordance with the present invention;

FIG. 2 is a diagram illustrating the manner of coupling between coordinate row and column circiuts of the memory in one embodiment of the invention;

FIG. 3 is a diagram partially in schematic form, partially in block and line diagram form of details of the selection matrix circuits of FIG. 1; and] FIGS. 4 through 13 are voltage and timing diagrams on a common time scale illustrating the operation of the store in accordance with the present invention.

FIG. 1 illustrates a magnetic store system in accordance with the invention and employing coated wire magnetic storage elements. Such elements are now known in the art and include, for example, an electrically conductive wire substrate with an anisotropic magnetic thin film deposited thereon by electroplating or other appropriate coating technique. The plated wire in the present state of the art may have a typical diameter of about 5 mils with plating thicknesses in the range of 3,000 to 10,000 angstroms. The film advantageously employed has an ice easy direction of magnetization, which is oriented approximately circumferentially around the wire, and which displays a substantially rectangular hysteresis characteristic having two oppositely poled remanent flux conditions around the wire. The hard direction of magnetization is oriented longitudinally with respect to the wire. Thus, the application of a magnetic field longitudinally along the wire drives the magnetization in the film portion affected thereby into its hard direction. The polarity of the signal thus induced in the wire indicates the polarity of the easy magnetization in the film portion affected thereby into its hard direction. The polarity of the signal thus induced in the wire indicates the polarity of the easy magnetization theretofore prevailing. Upon removal of such longitudinal field the magnetization relaxes to an easy direction polarity which is influenced by the direction of flow of any net current in the wire at the time of removal of the field.

The preferred embodiment of the invention includes a memory, to be described, which is word organized for operation in a 2-wire, i.e., linear select, mode in that drive signals applied to a selected word line only produce readout signals in digit lines coupled thereto. However, in order to write information into a selected word location of the memory it is necessary to apply tipping drive signals to digit wires during the time intervals when the word readout drive signal is being removed as hereinbefore mentioned. Individual memory elements of the plated wire type just described are known in the art to have switching times of a few nanoseconds, but when many of them are incorporated into a store system the store read-write cycle time runs much higher.

The store of FIG. 1 is assumed to be operated in a centrally controlled system, many types of which are known in the art. Such a system provides timing control signals for synchronizing a system processor (not shown) and the store, and it also supplies address signals to the store from a processor address information register for determining store locations that are to be activated. In FIG. 1 the timing and address interfaces between the processor and the store are a timing signal source '10 and address decoding circuits 11. The latter circuits are assumed here to include also the store address register. When activated by the timing source 10, the address decoding circuits 11 supply signals on a circuit pair each in two cables 12 and 13 to an address selection matrix 16. The signals on the selected circuit of cable 12 close a corresponding one of a group of diode rail switches 17, and ignals on the selected circuit of the cable 13 close a corresponding one of a group of word rail switches 18. Word rail switches and diode rail switches are so named because they are associated with correspondingly named selection matrix circuits connected to specified parts of the various matrix crosspoint circuits. Thus, it will be shown in connection with FIG. 3 that each crosspoint circuit includes in series a memory word drive line and a nonlinear conduction device, a diode in the presently preferred embodiment. A matrix word rail is a matrix coordinate conductor to which memory word drive lines of crosspoint circuits are connected, and a matrix diode rail is a matrix coordinate conductor to which crosspoint circuit diodes are connected. Electric circuit details of the selection matrix 16 will be subsequently discussed in connection with FIG. 3. It is sufficient to note here, however, that address signals to the decoding circuits 11 have the format shown in FIG. 4; and similar signals in cables 12 and 13 enable an electric circuit including the matrix 16, which defines a particular one of the crosspoint circuits of such matrix.

During the interval of activation of the address decoding circuits 11, the timing signal source supplies a timing signal, indicated in FIG. 5, to a word current control circuit 19 in the selection matrix 16. The control circuit 19 then produces an output pulse which is applied to a p i 9f term na s a d 2! 9f the E l :T Pl

is coupled to those terminals through a low inductance and low capacitance circuit such as the conductor pair of a short transmission line 22. For example, a line of the order of one-tenth of a wavelength for the dominant frequency in a memory word drive pulse rise time is advantageously employed. The one of the transmission line 22 conductors which is coupled to the terminal 20 for the diode rail switches 17 is also coupled through a winding 23 for supplying a readout timing signal for activating memory sensing amplifiers as will be described. Connections X schematically represent the circuit coupling coil 23 to a read timing circuit to be described. The word current control circuit 19 is adapted, as will be discussed in connection with FIG. 3, for controlling the shape of the word drive pulse produced by the selection matrix 16 regardless of the matrix or memory address selected. The terminal 21 is hereinafter considered to be access ground neutral, i.e., an internal ground for the word drive access circuits and not a common ground for the entire store.

The selection matrix is advantageously employed in the present invention because it is well known that the use of such a matrix can substantially reduce the store hardware costs for gaining access to randomly selectable memory addresses in large memories. The symmetricalmatrix-mernory array to be described permits the use of a selection matrix with a relatively large memory without serious disadvantage from various distributed capacitive effects, inductive variation effects (due to different circuit path lengths through the matrix), and current leakage effects which are known in the art to be generally characteristic of selection matrices. The symmetrical organization starts with the selection switches 17 and 18 of the matrix 16 and extends throughout that matrix and the magnetic memory associated therewith.

The matrix selection switches are advantageously transistor switches, and the word rail switches and diode rail switches are mounted on respective orthogonally arranged and intersecting mounting planes to form a three-dimensional cross as shown in FIG. 1. Thus, the single transmission line 22 couples signals from the word current control circuit 19, as a point source, to the terminals 20 and 21 as a point matrix impedance. Such impedance has been found to be substantially constant with a much lower capacitive portion than is generally found in prior art selection matrices since the capacitance between outgoing and return parts of the word drive circuit is electrically floating. Within the switch 18 block, leads fan out from terminal 21 to various ones of the word rail switches, and within the diode rail switch 17 block leads similarly fan out from the terminal 20 to the various diode rail switches mounted in the plane represented by that block.

Only a few transistor capsules are included in FIG. 1 for the word rail and diode rail switches, but in a presently preferred embodiment of the invention thirty-two word rail transistor switches are mounted on opposite faces of the switch 18 block, and a similar number of diode rail transistor switches are mounted on opposite faces of the switch 17 block. Such mounting of switches on opposite faces of a block helps to minimize the area enclosed by a word drive loop and thus minimizes loop inductance. Conductors from the cable 13 extend into the switch 18 block and fan out to the base and emitter electrodes of their respective word rail transistor switches which may be mounted on either the front or back surface of the block. Conductors in the cable 12 similarly extend to their respective diode rail switches 17. The three-dimensional cross arrangement just described for mounting matrix rail switches and coupling operating circuits thereto is utilized because it permits all such circuits for any one of the switches to be of substantially the same length as all other similar circuits. One lead from each switch extends to its corresponding diode rail or word rail of the matrix. Three such leads 26, 27, and 28 are shown in FIG. 1 for 1 co n c g ied? ail swi c es om th b ock 1 to diode rails of the matrix. Similarly two leads 29 and 30 extend from the word rail switches 18 to word rails of the matrix. Other connecting leads and their corresponding diode and word rails are similarly arranged but are omitted from the drawing to avoid unnecessarily complicating the drawing.

Two word rails 31 and 32 are shown in FIG. 1 and are coupled to the connecting leads 29 and 30, respectively. Each word rail has the configuration in the drawing of an upside-down tree with the base of its trunk connected to its corresponding word rail switch. Each such Word rail tree circuit has a plurality of symmetrically arranged branches spaced along the length thereof so that any voltage condition appearing at a branch point on the trunk of the word rail has the same effect upon two symmetrically op-posed rail branches.

Each of the word rails is advantageously deposited on a similarly configured substrate, not shown, in accordance with any of the techniques for such purpose which are well known in the art. Such substrates, bearing their associated word rail circuits, are stacked with such circuits in alignment along a stacking axis which is parallel to the plane of the word rail switches 18 and perpendicular to the plane of the diode rail switches 17. This latter orientation with respect to the word rail switches 18 permits the shortest possible coupling circuit lines therebetween. However, all of such coupling circuits are of similar length and are properly symmetrically dressed to take up the slack which is present in coupling circuits from word rail switches which are closer to the word rails than other ones of the word rail switches.

The matrix 16 includes as many diode rails as there are word rails and three such diode rails 33, 34, and 35 are shown in the drawing. The rail 33 is associated with the word rail branches on the far side of the word rail stack and the diode rails 34 and 35 are associated with word rail branches on the near side of the word rail stack as shown in FIG. 1. Each of the diode rails is advantageously manufactured in an integrated circuit format so that all of the diode elements of any one rail share a common cathode portion of the integrated circuit chip. Such an integrated circuit chip for multiple diodes is well known in the art and is schematically represented in the drawing by the illustration therein for interconnecting cathode elements of the diodes in a rail. The integrated diodes and diode rail are inexpensive to manufacture and permit a compact matrix with extraordinarily low distributed capacitance. The fact that the capacitance is low contributes to the relatively steep rise and fall time transitions of word line current as shown in FIG. 6.

The diode rails are interspersed in the word rail array so that each diode rail, or shelf, extends along a stack of corresponding branches of all of the word rails. The anode connection of each diode on such a diode shelf is then in close proximity to the tip of a different one of such corresponding word rail branches. These diode shelves may be supported by the word rail substrates or secured in position by any other suitable means. Each diode rail has its electric circuit drive point at the center thereof and receives at such drive point its corresponding connection from its diode rail switch in the group of switches 17. Thus, the connecting leads 26, 27, and 28 are coupled from different ones of the diode rail switches 17 to central drive points of the diode rails 33, 34, and 35, respectively. The diode rails necessarily extend in a direction which is perpendicular to the array of diode rail switches 17. Consequently, the coupling leads to the diode 'rail center points are conveniently extended to their respective diode rail switches 17 without interfering with the corresponding connections from word rails to the respective word rail switches 18. Furthermore, such connections to the diode rails are also symmetrically arranged with respect to the plane of the array of word rail switches 18. Thus, each distributed capacitive effect, which is present with respect to a diode rail switch and its diode rail on the near side of the matrix 16, as illustrated in FIG.

6 1, has counterpart on the far side of the matrix, as illustrated in FIG. 1.

In summary up to this point, within the matrix the elec tric circuit path from the word current control circuit 19, and its point source appearance at terminals 20 and 21, to the matrix output drive point, at the anode of a diode and its associated word rail branch tip, is essentially the same for any such drive point that may be selected in the matrix. Furthermore, each such path on the near side of the matrix has a symmetrical counterpart on the far side of the matrix. There are, of course, small differences in the electric path length such as, for example, the differences in electric circuit distance between the top branch pair and the bottom branch pair of the word rail 31. However, these differences are relatively minor. Insofar as the differences have an effect upon the memory, it is a symmetrical effect producing balanced signal wave fronts in the symmetrical parts of the store; and such effect is handled in a manner to be described. Such wavefronts in the symmetrical store permit the characterization of the matrix as being equipotentially arranged.

Turning now to the memory portion of the store of FIG. 1, each matrix crosspoint includes a diode and a load. The load is a memory word drive line which is coupled to the matrix. As previously noted, 1024 word lines were included in an embodiment of the memory which has been actually operated. Each of the word lines is an insulated electrical conductor. Only eleven of those word lines are illustrated in whole or in part in FIG. 1. Those illustrated are the lines 38 through 48. Couplings between matrix 16 and those lines are conductor pairs with the forward and return paths thereof adjacent to one another and symmetrical with respect to access neutral ground. Furthermore, the two paths are close to one another with path spacing being advantageously of the order of the transverse dimension of the conductor in one of the paths. Twisted lead pair couplings provide the necessary electrical and spacing characteristics and are employed in FIG. 1, but other coupling circuits such as strip transmission lines are also useful in this application. Such twisted pairs are illustrated in part only and are otherwise schematically represented by broken lines to indicate that the twisted pairs make certain electrical connections and are dressed in a certain manner to be described. Each of the word lines is directly coupled to its respective matrix crosspoint circuit without the necessity for intervening alternating current coupling elements or for access current switches in the drive lines at the memory. Any distributed capacitance between leads of a twisted pair is electrically floating.

The word lines 41, 42, and 43, including their respective twisted pair coupling leads, are adjacent to one another and are connected to the matrix crosspoints represented by the lower three branches on the near side of the word rail 31. These comprise a portion of a group G1 of adjacent memory word lines which are all connected to crosspoints including word rail branches on the near side of the word rail 31. Similarly, the word lines 44 and 45 are part of a group G2 of adjacent word lines connected to branches on the near side of a different word rail, and the word lines 46 through 48 comprise part of a group G3 of adjacent word lines that are coupled to branches on the near side of the word rail 32. In like manner, other groups of adjacent memory word lines have all of their respective word lines coupled to matrix word rail branches on the same side of a different common word rail for each group. Furthermore, the twisted lead pairs coupling the word lines of a group to their respective branches of their common word rail in the matrix are all dressed or cabled together as indicated by the grouping of twisted pair representations in FIG. 1.

It has been found that the aforementioned manner of associating word rail connections and memory word lines significantly reduces the distributed capacitive effect appearing at the matrix crosspoint. Such reduction in turn greatly reduces the adverse capacitive shunting effect and thereby increases the elfciency with which memory drive pulses are utilized. For example, capacitors 49 and 50 in FIG. 1 schematically represent distributed capacitance among word lines 41, 42, and 43 within a group and are typical of similar capacitance throughout the memory. The application of a word drive pulse to the word rail 31 for driving one single selected one of the word lines which are coupled to rail 31 causes all of the word lines on that rail to receive a voltage bounce at substantially the same time. However, since word lines associated with one side of a word rail are all grouped together in the memory, the opposite terminals of distributed capacitance 49, 50 among the word lines within such a group moving in substantially the same manner in a voltage waveform. sense. There is no change in the potential difference across such distributed capacitance, and it has no deleterious effect upon the drive pulse. This results from the fact that capacitances such as 49 and 50 are floating. Similar results are not available in prior art circuits employing a common ground return plane or lacking the indicated grouping.

The distributed capacitance from the word lines within a group to other store elements outside of the group is significant because its terminals move differently in a voltage sense. This latter type of distributed capacitance is schematically represented in FIG. 1 by the capacitor 51 which is connected by broken-line leads, between the word lines 43 and 44 which are on the edges of their respective word line groups G1 and G2. Such intergroup capacitance is, however, much smaller than the total interlead capacitance generally effective in prior art memories.

The use of twisted lead pairs to couple matrix crosspoints to corresponding word lines not only reduces coupling lead inductance, as is well known in the art for twisted pairs, but it also presents to the matrix drive point a substantially lower distributed capacitance than is the case in prior art matrix-memory systems which employ either widely separated outgoing and return leads or a common ground return plane for memory drive circuits. Also, the fact that twisted pairs for a ground of word lines are dressed, or cabled, together has a capacitance reducing effect which is similar to that just described for the grouping of the associated word lines. The described word line coupling and grouping help to hold down the capacitive effects presented to matrix word rails and thereby permit fast word rail preselection at time in FIG. 7.

The memory portion of the store in FIG. 1 is divided into two submodules which are driven by the two halves, respectively, of the selection matrix which are on opposite sides of a plane including the trunk portions of the word rail circuits 31- and 32. Each of the submodules includes a folded plane. On the right-hand side of FIG. 1 the folded submodule plane includes the plane portions 52 and 53, and on the left-hand side of the memory module the submodule includes plane portions 56 and 57. Each submodule has a plurality of digit circuits mounted thereon and coupled to and extending perpendicularly to the various word lines of a memory. A digit line 58 is coupled in the submodule planes 52, 53 and a similar digit line 59 is coupled in the submodule planes 56, 57. Both of the digit lines 58 and 59 are physically located in corresponding portions of their respective submodules and are coupled to the same digit coupling circuit 60. Other digit line pairs are, of course, included in the memory; and each pair of correspondingly located digit lines is coupled to its respective digit coupling circuit. Alternate ones of the pairs of digit lines are advantageously arranged to extend in opposite directions with respect to the intermediate pairs of digit lines, as indicated by a third digit line 61 and its digit coupling circuit 62. A digit line 61' (shown only in part) corresponds to line 61 but couples the circuit 62 to the submodule planes 52 and 53.

In FIG. 2 a part of each of digit line 58 and word line 43 are shown to illustrate the nature of coupling therebetween. Each digit line is made up of an electrically conducting wire 63 and a thin film magnetic coating 66 thereon, as indicated on one of the portions of the digit line 58. Each digit line is really a doubly folded line because it is folded to extend through the full length of its folded line submodule, as shown in FIG. 1; and it is also folded to form adjacent outgoing and return circuit portions which are both coupled to a digit coupling circuit, as shown for the digit line 58 and the coupling circuit in FIG. 1. Each digit line further forms with the surrounding world a folded transmission line by virtue of the distributed capacitance along the line to the surroundings in the memory. This distributed capacitance extends, of course, to all surroundings; but it is schematically represented in FIG. 2 by the capacitors 67, 68, 69, and 70, which are shown there between portions of digit line 58 and portions of the word line 43 which are coupled theret0.

FIG. 2 further illustrates details of the manner in which the word line and a digit line are coupled to one another with word line 43 wrapped around digit line 58 in the fashion of crossed hairpins. Each such double intersection of word and digit lines represents one information bit location and includes the two plating portions on line 58 enclosed by line 43. A bit is represented by oppositely oriented easy magnetization in such enclosed portions as represented by arrows 64 and 65 in FIG. 2. Strong magnetic coupling is achieved between the word line 43 and the magnetic coating 66 on the digit line 58. Each current pulse in the word line 43 drives the magnetization in digit lines coupled thereto into the hard direction of magnetization and thereby induces a current in the digit line 58. Because the enclosed portions have oppositely oriented easy magnetization as viewed in FIG. 2, and because line 58 is folded, such induced signals in the two parts of the digit line are in series-aiding relationship with respect to one another for activating a digit circuit detecting, i.e., sensing, amplifier, to be described. However, word line drive pulses are capacitively coupled as noise voltages from the word line 43 to the digit line 58 through the distributed capacitance 67-70 illustrated in FIG. 2. Such noise occurs as every word line coupled to a selected word rail receives voltage bounce; and it appears in the digit line 58, and other digit lines, as a longitudinal signal. Thus, within the digit line 58 the information signal induced in response to magnetic flux switching is in an unbalanced mode; and the principal noise signals are in a longitudinal, or balanced, mode so that the information may be more readily detected.

The outgoing and return portions of a digit line are spaced relatively closely to one another so that at each intersection of one of these portions with a word line the insulation interposed therebetween and, consequently, the capacitive coupling there-between is substantially the same as it is for the other portion of the same digit line with respect to the same word line. In one embodiment employing 5 mil plated wires for the digit lines the outgoing and return portions of a digit line are spaced approximately 25 mils apart on centers. Thus, the statistical probability of a substantial change in insulation thickness along a word line in such a memory spacing as 25 mils is quite small. This assures nearly perfect conversion of drive signals on a word line into longitudinal noise signals in the digit lines. There is, thus, a minimum of unbalanced noise signal component in any digit line to mask a desired information signal which is in the unbalanced mode. These longitudinal noise signals, which originate as word drive pulses in the selection matrix and take the form of voltage bounce on nonselected branches of a selected word rail, are coupled through the aforementioned distributed capacitances shown in FIG. 2 to all of the digit lines in the memory, and such longitudinal signals return to their common word drive pulse source in the selection matrlx by way of other store distributed capacitances, such as capacitances to word lines in nonselected groups.

Within each digit coupling circuit, such as circuit 60, the two digit lines from different submodules, which are accommodated by the digit coupling circuit, are applied in opposite phase to the input of a detecting amplifier; and they receive the output of a driver in opposite phase. In the illustrative embodiment of FIG. 1 a single coupling core 71 provides the indicated coupling functions in circuit 60 for the correspondingly located digit lines 58 and 59. Core 71 is operated primarily in a linear transformer coupling mode. Since the digit lines 58 and 59 are coupled to the core 71 in opposite phase, any imperfections in word line noise conversion to the longitudinal mode in the digit lines is similar in both of the lines 58 and 59. The resulting unbalanced noises in the two digit lines are offset against one another at core 71.

One might guess at first glance that within a digit line the net imperfection in the conversion of noise from the word lines into the longitudinal mode would have random size and polarity. However, all of the Word lines in any submodule which receive voltage bounce at any one time are grouped together and receive that voltage bounce from a common word line in the selection matrix 16. Furtherinore, such a group of word lines in one submodule has a counterpart group of word lines in the other submodule, which counterpart group also receives voltage bounce from the same matrix word rail at the same time. Each of these groups includes a substantial number of word lines, i.e., in one embodiment there are 16 such word lines in each such group. In view of the described symmetry of electrical connections and of physical location of memory word lines coupled to a matrix word rail, the statistical probabilit that any resulting unbalance from a word line group in one submodule will be of essentilly the same magnitude and polarity as the net unbalance from the counterpart group in the other submodule is high. EX- perience gained in the operation of a plated wire memory of the type described indicates that this is indeed the case. That is, the unbalanced signals produced in symmetrically paired digit lines as a result of word line noise are essentially the same and can be effectively offset against one another by the oppositely phased couplings of the two digit lines to their common coupling core 71. Furthermore, as one advances to larger memories, the number of word lines in each group is increased and the statistical probability of having similar groups in corresponding locations of the two submodules increases.

A detecting amplifier 72 is of the differential amplifier type and has its input coupled across a winding 73 that is substantially uniformly distributed over the core 71 to provide close coupling to all other circuits that are also coupled to the core 71. Thus, with respect to any given digit line, such as the line 58 which is coupled to core 71, unbalanced signals actuate the amplifier 72; but longitudinal signals, i.e., noise signals, have substantially no effect upon the amplifier. The differential amplifier and the manner of word-digit coupling provide the means for detecting information signals in the presence of noise.

The amplifier 72 is time gated by the output, shown in FIG. 10, of a read timing circuit 76. The latter circuit is controlled by word drive pulses coupled thereto from the monitor coil 23 adjacent to terminal in matrix 16 as indicated in FIG. 1. This type of gating arrangement, cooperating with the uniform word current distribution achieved by the symmetrical organization, minimizes the effect of any time jitter that may be present in the word drive pulses insofar as such jitter may affect the time at which the amplifier 72 digit coupling circuit is strobed. Other strobe pulse generating arrangements which are known in the art can, of course, be applied to take into account the time jitter problem and also to take into account differences in the phase of readout signals on digit lines depending upon the address location within the memory at which such signals were generated. The output of amplifier 72 is coupled to a threshold detecting circuit 77 for indicating whether the output signal represents a binary ONE or binary ZERO. A utilization circuit 74 re-- ceives the threshold circuit output and represents, for example, a processor memory access register.

Digit line drive signals of the type shown in FIG. 11 are provided by a digit drive circuit 78 under the control of timing from the timing signal source 10. Each drive pulse in one embodiment is unipolar as shown by the solid-line portion of FIG. 11. Drive circuit 78 also has the polarity of its unipolar output controlled in accordance with signals from a data information register, not shown, or any similar source of information signals, as is well known in the art. The output of digit drive circuit 78 is applied through two current limiting resistors 79 and 80 to the digit lines 58 and 59 in parallel. Since the latter digit lines are coupled to the core 71 in opposite phase, the flow of digit drive current therein produces only a moderate net eflfect upon the core 71. Such effect can be seen by comparing FIGS. 9 and 11 between times t and t It is a moderate effect comparable in amplitude to the information readout following time t so it does not drive the amplifier input so hard as to require a large time for amplifier recovery. The waves illustrated in FIG. 9 represent readout of a binary ONE between times t and t and a write-in of a ONE between times t and t Other waveforms would be produced for different information changes and for the two-pulse Write which will be subsequently discussed.

The signals on winding 73 during digit line drive are due to a combination of causes, but the dominant causes are lack of perfect impedance balance in the digit line pair, noise coupled from adjacent digit lines, and signals induced upon relaxation of flux to the: easy direction at the selected bit location. Signals on winding 73 during digit drive time produce no significant effect upon the detector amplifier 72. In addition, the amplifier is gated into operation for only a short time after time t, in FIG. 10. Consequently, it is necessary in the illustrated store system to provide only a short time guard space for the recovery of the detector amplifier before a readout operation as is common in certain prior art memory systems. Furthermore, digit lines of alternate pairs have their conductors transposed at the plane fold point as indicated at 102 for the digit line 61 in FIG. 1. This transportation reduces the effect at winding 73 of interactions between digit circuits.

FIG. 11 also shows a two-pulse, i.e., dipulse, drive signal when the positive solid-line (t -t and negative broken-line (t i portions thereof are considered together. It is known in the art to employ a two-pulse digit drive in thin film memories as a device for reducing sensitivity to creep, i.e., the destruction of information bits by repeated pulsing. However, such drive normally has required two word drive cycles, a true drive cycle and a dummy drive cycle. In the store described herein, the low diode rail circuit distributed capacitance permits the word current of FIG. 6 to have a relatively fast fall time so that the dipulse digit drive of FIG. 11 is employed to advantage on the trailing edge of a single word drive cycle for reducing creep sensitivity.

In FIG. 3 there is shown a more conventional schematic form of a 2 x 2 portion of the selection matrix 16. Circuit elements corresponding to elements in FIG. 1 have the same or similar reference characters. Thus, two word rails and two diode rails are shown. A word rail decoder 11, representing a part of the FIG. 1 decoding circuit 11, supplies selection signals to word rail switches 18' and 18" to close one of them in response to a timing signal from the source 10 shown in FIG. 1. Similarly, a diode rail decoder 11" represents another portion of the address decoder circuits 11 in FIG. 1 and controls a selectable one of the diode rail switches 17 and 17". Each of the rail switches is a simple transistor switch with p-n-p transistors being employed for the word rail switches and n-p-n transistors in the diode rail switches. A capacitor 75 is connected between base and collector electrodes of each of the switches 18 to moderate drive rise time because it was found in some applications that the invention produced such a fast rise that an excessive amount of noise was generated. A selection signal from each of the decoders 11' and 11" biases the transistors of the switches 18 and 17' into conduction thereby closing a path forcurrent flow from access neutral ground through the switch 18, word rail 31, word line 41, diode rail 35, switch 17, terminal 20, word current control circuit 19, and terminal 21 to ground. The ground indicated in FIG. 3 is, of course, there shown for schematic convenience in preparing the drawing and is access neutral ground point and not a common ground for the store system. As previously noted in connection with FIG. 1, no common ground plane, or bus, is employed in the store here presented.

A diode rail bias circuit 81 establishes a positive direct-current back bias potential for crosspoint diodes with respect to the access neutral ground, i.e., terminal 21. Such bias is applied continuously through current limiting resistors 82 and 83 to the diode rails shown in FIG. 3 and through. a branching point 86 and similar current limiting resistors, not shown, to oiher matrix diode rails which are not shown in FIG. 3. The bias from source 81 is at a low level, such as five volts, and reversely bi ses diodes of all nonselected matrix crosspoint circuits to prevent conduction therein when a word rail to which they are connected is grounded by the closing of a word rail switch 18.

A times voltage pulse is applied to all of the matrix word rai.s by a word rail clamp circuit 87 in response to timing signals from the timing signal source as indicated by the timing block 10 in FIG. 3. Such word rail clamp timing signal is illustrated in FIG. 12 and overlaps the end of the drive pulze on the digit line after a write-in operation. The signals from clamp circuit 87 have two components. A negative bias with respect to ground is continuously applied to all word rai's through resistors 88 to hold nonselected crosspoint diodes nonconducting even though they may be connected to a selected diode rail. However, during the time interval r 4 the cathode of diode 89 is clamped to the same negative potential to charge distributed capacitance along a selected word rail and its word lines to the negative bias level as rapid y as possible. Similar connections to other word rails not shown in FIG. 3 are indicated by the branching points 90 in that figure.

Within the word current control circuit 19 the word drive potential source and switching control thereof are provided. The word control circuit timing provided from the circuit 10 in FIG. 1 is schematically represented by the block 10 in FIG. 3. This timing signal is applied between the base and emilter electrodes of a common emitter connected driving transistor 95. The output from that transistor is coupled through a transformer 91 and through conventional coupling impedances to control conduction in a switch transistor 92. The latter transistor is arranged in a floating switch configuration to switch the output of a battery 93 across the terminals and 21 through the coupling conductors of the short transmission line 22. A damping resistor 94 is shunted across terminals 20 and 21 to reduce ringing effects when transistor 92 ceases to conduct.

When transistor 92 is in a nonconducting state, in the absence of timing pulses from the source 10", the battery 93 supplies current in series through a resistor 96, a sored charge diode 97, and a pair of parallel-connected resistors 98 and 99. During this time diode 97 stores current carriers, in the fashion of a stored charge, that are later available to support reverse conduction for a limited time as is known in the art for such diodes. A capacitor 100 simply provides aternating current bypass for the battery 93. During the time when the transistor 92 is nonconducting a capacitor 101, which is connected in parallel with the resistor 96, charges to the potential difference appearing across the resistor. In a typical embodiment which has been operated the resistance of the resisor 96 is approximately one and onehalf orders of magnitude larger than the parallel resistance of the resistors 98 and 99. Consequently, the steady state potential developed across capacitor 101 between pulses from the timing source 10" is approximately the same as the terminal potential of battery 93. The latter potential is assigned a magnitude which is only adequate when driving through resistors 98 and 99 to maintain the desired steady state word drive pulse amplitude shown in FIG. 6 when transistor 92 is conducting. Control of the word drive pulse rise time is exercised by the circuits of diode 97 as will be described. The emitter electrode of transistor 92 is cinnected to the cathode of the stored charge diode 97 and the collector eleclrode of the same transistor is connected through the transmission line 22 to the terminal 20.

Now, in response to a timing pulse from the source 10" between times t and f as indicated in FIG. 5, transistor 92 is driven into conduction. Initialy the operating potential for such conduction is supplied by the capacitor 101 and current flows through the transistor 92 collector emitter path in the forward direction, through diode 97 in the reverse direction, and through capacitor 101. The remainder of the closed loop for current flow includes the path though the matrix 16 which was previously outlined and the etfective impedance of which appears across the terminals 20 and 21. Conduction in this fashion is maintained through the diode 97 as long as the previously stored current carriers in that diode are available. Diode 97 and capacitor 101 present a very low impedance current path, as compared to the conduction path through the resistors 98 and 99 and the battery 93, and they make a substantialy uniform level of voltage available to the selected matrix crosspoint load for as long as such carriers are available. The diode 97 and capacitor 101 operates as a self-timed short circuit which is operative for such a short interval that there is only a minor change in the voltage across capacitor 101.

The time that the diode 97 will conduct in the reverse direction as just described is determined by the amount of precharge stored therein, and that is determined by both the individual and the relative magnitudes of the resistors 96, 98, and 99. Since the matrix is arranged as described in connection with FIG. 1 to have substantially uniform electrical characterisics in all of its selectable paths, there are only minor variation in the point impedance at terminals 20 and 21 for different memory address selections. Thus, the drive pulse supplied at those terminals has a substantially uniform rate of rise for all addresses, unhampered by stray capacitances; and the time at which the drive pulse knees over to its maximum level is accurately and consistently fixed by diode 97. There is, then, no need to provide an excessively large potential source to maintain an essentially constant rate of drive pulse rise for the maximum time that might be needed to realize flux switching at any memory location under any information conditions. The use of such oversize sources requires some timing to limit voltage excursions, but there is always the risk of damage to store circuit elements which might result if some malfunction of timing should leave that voltage on too long.

When the supply of carriers from the charge storage diode 97 is exhausted, the circuit branch including that diode is effectively removed from the drive circuit as the diode reverts to a high impedance substantially nonconducting condition. After that time the drive current is maintained for the remainder of the drive interval by current supplied by the battery 93 through a circuit including the transistor 92 and the resistors 98 and 99. Thus, the stored charge diode word current control circuit makes it possible to supply word drive from a potential source which is substantially smaller than is normally required in prior art circuits. Furthermore, the lower voltage eX- posure of the circuits in FIG. 3 means improved margins against voltage breakdown and thus reduces materials and manufacturing costs as is known in the art.

In FIG. 3 it can be seen that each diode rail circuit is controlled by two switches, one of the diode rail switches 17'and the switch of transistor 92 and its associated circuits. It is well known that each transistor has an inherent capacitance between its collector and emitter electrodes which is effective during high speed operation such as that required for nanosecond-type memory operation here under consideration. However, the presence of two switches to initiate turn-off in each diode rail circuit at time i reduces the effect of switch capacitance for the selected circuit. Thus, the much smaller capacitance represented by switch 17 and circuit 19, as well as the small diode rail distributed capacitance, are all that remain so there is little turn-off ringing.

It has been found that a store organized as described herein has an access time of about 75 nanoseconds measuring from the 50 percent point in the rise time of a processor address information register output pulse to the store address register in decoding circuits 11 until the 50 percent point in the rise time of the regenerated output pulse from utilization circuit 74 in the memory output. such access time in the drawings is the interval from a time t in FIG. 4 to a time t, in FIG. 13. That access time includes operating times for commercially available registers and decoders that have not been opiimized and comprise no part of the present invention. Of somewhat more importance is the fact that the word rail voltage of FIG. 7 is driven fro-m -20 volts to its zero voltage maximum value in about 20 nanoseconds in an embodiment of the type described herein during the interval t t In FIG. 3 a plurality of diodes 103 are provided and each is connected in series in the emitter circuit path of a different one of the transistor switches 17. The anode of each diode is connected through a different current limiting resistor to the negative terminal of a battery 106 which has its positive terminal connected to access neutral ground. The battery 106 has a terminal voltage of sufficient magnitude to hold those diodes 103 which are in nonselected diode rail circuits in a no-nconducting condition in spite of the presence of a negative voltage at terminal 20 as a result of operatic-n of Word control circuit 19 as aforesaid. In the selected diode rail circuit, the diode 103 conducts as a result of the negative voltage at terminal 20. The diodes 103 have a much lower interelectrode capacitance than do transistors such as those in switches 17, and the diodes, thus, greatly reduce the capacitive loading effects of nonselected diode rail switches 17 on the drive pulse in the selected circuit. The loading effect is advantageously still further reduced by having each diode 103 serve in common for a group of diode rail circuits.

Although the present invention has been described in connection with a particular embodiment thereof, it is to be understood that other embodiments and modifications which will be apparent to those skilled in the art are included within the spirit and scope of the invention.

What is claimed is:'

1. A store system comprising a memory having first and second sets of drive circuits coupled thereto, said memory being divided into first and second submodules wherein the location of eachof said drive circuits in said first submodule corresponds to the location of another of said drive circuits in the second submodule,

first means applying drive signals to a selectable drive circuit of said first set,

second means applying drive signals to corresponding pairs of drive circuits of said second set,

detection means for each of said pairs of drive circuits,

means coupling the drive circuits of each of said pairs to its detection means in opposite phase whereby effects of signals from said second applying means and of similarly poled signals on the circuits of such pair are substantially reduced, and

each of said circuits of said second set is formed in a folded transmission line having both its input and its output coupled to said coupling means.

2. The store system in accordance with claim 1 in which magnetic means provide inductive coupling between cir- ;cuits of said first and second sets for storing information and for producing unbalanced signals in circuits of said second set in response to signals from said first applying means, and

means further coupling said circuits of said first and second sets together at predetermined locatons for producing balanced signals in circuits of said second set in response to signals from said first applying means.

3. The store system in accordance with claim 1 in which magnetic means provide inductive coupling between circuits of said first and second sets for storing information and for producing unbalanced signals in circuits of said second set in response to signals from said first applying means, and

means including distributed capacitance further coupling said circuits of said first and second sets together at predetermined locations for producing balanced signals in circuits of said second set in response to signals from said first applying means.

4. The store system in accordance with claim 1 in which each of said drive signals from said second applying means includes a dipulse including a positive-going pulse and an adjacent negative-going pulse,

each of said drive signals from said first applying means comprises a pulse having leading and trailing edges, and

timing means synchronize said first and second ap plying means to cause a first pulse, in point of time of, of each said dipulse to overlap said trailing edge of a second applying means pulse.

5. A store system comprising a source of pulses,

a memory including a plurality of information storage addresses, said memory having its addresses divided into two symmetrically arranged parts with each address in one of such parts having a corresponding address in the other of such parts,

an access matrix coupling said source to a selectable one of said addresses, said matrix. having first and second sets of circuits orthogonally arranged so that each circuit of either set intersects all circuits of the other set and a different crosspoint circuit is electrically connetced between first and second set circuits at each intersection, each of said crosspoint circuits being coupled to a different one of said addresses, each of said circuits of said first set being divided into two equipotentially arranged parts,

for each of said first set circuits, all crosspoint circuits connected to a first of said two parts thereof are coupled to memory addresses in a first of said two address parts and crosspoint circuits connected to a second of the two parts of such first set circuit are coupled to memory addresses in a second of said two address parts,

means supplying address signals to said matrix for controlling address selection thereby, and

means differentially detecting corresponding addresses in said two memory parts.

6. The store system in accordance with claim 5 in which a different drive circuit couples each of said crosspoint circuits to a different one of said addresses, and

all of said drive circuits that are coupled to crosspoints on one of said parts of a first set circuit extend to a group of said addresses which are adjacent to one another in one of said address parts.

7. The store system in accordance with claim 5 in which 15 all of said drive circuits are of substantially the same length, and all of said drive circuits extending to the same group of adjacent addresses are dressed together separately from drive circuits to other groups but in similar configuration. 8. The store system in accordance with claim 6 in which each of said drive circuits comprises outgoing and return circuit paths between its corresponding crosspoint circuit and memory address, said paths being in close proximity to one another in relation to their respective transverse path dimensions and being sym metrical with respect to a terminal of said pulse source. 9. The store system in accordance with claim 6 in which each of said drive circuits is a twisted lead pair providing outgoing and return circuit paths between its corresponding crosspoint circuit and memory address. 10. The store system in accordance with claim 6 in which said drive circuits extending to corresponding addresses in different ones of said address parts are coupled in a pair of said crosspoint circuits that are symmetrically arranged with respect to one another in different ones of said parts of the same first set circuit. 11. The store system in accordance with claim in which exclusively direct current circuit means are included in each of said crosspoint circuits. 12. The store system in accordance with claim 5 in which each of said pulses has an essentially flat-topped portion, and said source includes a potential source having a terminal voltage of only sufiicient magnitude to maintain said fiat-topped portion of said pulses through a first circuit path, switching means in said path and recurrently coupling said potential source to said matrix, and a second circuit path connected in parallel with said first path and including in series a stored charge diode and a capacitor, said diode being poled for forward conduction of current from said potential source when said switch is open and reverse conduction of current from said matrix when said switch is closed. 13. A store system comprising an access matrix including first and second sets of orthogonally arranged rail circuits in which each of the circuits of the first set is perpendicular to and intersects all of the circuits of the second set, each of said rail circuits having an electric circuit drive point on an axis of symmetry thereof and being electrically interconnected to all rail circuits of the other set by a crosspoint circuit at each intersection, each of said crosspoint circuits including a nonlinear conduction device and a load connected in series all of said crosspoint circuits which are electrically connected to any one of said rail circuits being physically located in said matrix so that each of said crosspoint circiuts is arranged in symmetrical relation to another one of said crosspoints connected to the same rail circuit and with respect to said symmetrical drive point of said rail circuit, each of said devices has a first terminal connected to a rail of said first set and a second terminal connected to its corresponding load, said second terminal being physically arranged in close proximity to the connection point of such load to its associated rail of said second set, a source of drive pulses, selecting means coupling said pulses to a circuit including in series therein one of said rail circuits from each of said sets and the crosspoint circuit defined thereby,

16 memory means comprising at least two memory submodules, each including a coordinate array of row and column circuits defining at the intersection thereof memory storage locations, each of said storage locations in one of said modules corresponding to a similarly defined location in the other of said submodules, each of said column circuits being connected in a different one of said crosspoint load circuits as said load therein, the crosspoint ones of said crosspoint load column circuits in said two submodules comprising a symmetrically arranged pair of crosspoint circuits on a common rail circuit of said first set, and differential detection means coupled between corresponding row circuits of said submodules. 14. The store system in accordance with claim 13 in which each of said nonlinear conduction devices is a diode,

and all of said diodes are poled in the same direction with respect to said rail circuits. 15. The store system in accordance with claim 13 in which each of said matrix crosspoint circuits is directly connected to its memory column load circuit terminals by a twisted pair of leads, and all of the twisted lead pairs are of the same length. 16. The store system in accordance with claim 13 in which row circuit drive means are provided for said memory, each of said memory row circuits is formed in a loop with the ends thereof coupled to different terminals of said row drive means, and corresponding row circuits of said two submodules are coupled to the same row drive means terminals so that such corresponding row circuits are in an electrically parallel connection across the output of said row drive means. 17. The store system in accordance with claim 13 in which each of said memory row circuits is formed in a loop with the ends thereof coupled to said differential detection means, an inherent capacitance is present between each of said row circuits and each of said column circuits which are coupled thereto whereby signals in said column circuits are capacitively coupled to said row circuits in the longitudinal mode in the latter circuits, and corresponding ones of said row circuits of said two submodules are coupled to the same detection means but in opposite phase whereby similarly poled unbalanced signals in such row circuits are offset against one another at the input to such detection means. 18. The store system in accordance with claim 17 in which a single magnetic core couples each pair of corresponding ones of said row circuits of said memory to said detecting means. 19. The store system in accordance with claim 13 in which said source of drive pulses comprises means selecting one of said rail circuits of each of said sets for actuation, switch means connected in series with said selected rail circuits, and said switch means comprising in series therein a first current path including a stored charge diode and a capacitor in parallel branch circuits, a second current path connected in parallel with said first path and including a source of operating potential in series with resistance means for supplying operating potential to said diode, said diode being poled for forward conduction of current from said potential source and reverse conduction of current through said switching means.

17 20. The store system in accordance with claim 19 in which magnetic means are coupled to said row and column circuits at said intersection thereof, and

said potential source and the impedance of said first and second current paths being proportioned with respect to the impedance of said matrix during one of said drive pulses so that said diode attains sufficient stored charge between drive pulses to supply the matrix current during drive pulse rise time.

21. The store system in accordance with claim 14 in which each of said rails of said first set comprises a plurality of integrated circuit diodes having a common electrode member for a first electrode of all of such diodes,

each of said rails of said second set comprises a central conductor including said drive point and a plurality of symmetrically arranged branch conductors thereon, and

said integrated circuit diode rails being interspersed in said branch conductors so that each diode rail is in close proximity to one of said branch circuits of a second set rail and in close proximity to all corresponding branch circuits of the remainder of said rails of said second set. 22. The store system in accordance with claim 21 in which.

means apply a dipulse signal to each of said row circuits to overlap in a time sense a trailing edge of each pulse from said drive pulse source, and each of said dipulse signals comprises adjacent to one another a negative-going pulse and a positive-going pulse. 23. The store system in accordance with claim 21 in which said selecting means includes a plurality of transistor switches, each connected in series between said drive pulse source and a different one of said rail circuits,

coextensive with a plane including said second set rail central conductors, and

all of said switches of a second of said types being mounted in a planar array substantially perpendicular to and symmetrically intersecting the first-mentioned array.

24. The store system in accordance with claim 13 in which each of said memory row circuits intersecting a memory column circuit has magnetic rneans disposed at each such intersection for electromagnetically coupling such row and column circuits in response to current in such column circuit, and

the sense of said coupling on the two sides of said row circuit loop being such as to induce signals in such loop in series aiding relationship in response to said column circuit current.

25. The store system in accordance with claim 24 in which each of said row circuits is an electric conductor with a coating of magnetic material of substantially rectangular hysteresis characteristics thereon for providing said magnetic means, and

said coating has an anisotropic magnetic characteristic with the hard axis thereof oriented parallel to the longitudinal axis of the corresponding one of said conductors and the easy axis thereof oriented substantially circumferentially around said conductor.

Magnetic Film Memory Having Increased Disturb Margins, by Beam, Elfant, Jutzi, IBM Technical Disclosure Bulletin, vol. 9, No. 1, June 1966, pp. 73-74.

BERNARD KONICK, Primary Examiner KENNETH E. KROSIN, Assistant Examiner US. Cl. X.R. 340-173

Images