US3478633A

US3478633A - Counter resetting arrangement for rhythm accompaniment starting

Info

Publication number: US3478633A
Application number: US538527A
Authority: US
Inventors: Alfred L Mallett
Original assignee: Seeburg Corp
Current assignee: Bank of America Illinois; Seeburg Corp
Priority date: 1966-02-07
Filing date: 1966-02-07
Publication date: 1969-11-18
Anticipated expiration: 1986-11-18

Description

Nov. 18, 1969 A, 1.. MALLETT COUNTER RESETTING ARRANGEMENT FOR RHYTHM ACCOMPANIMENT STARTING Filed Feb. 7, 1966 4 Sheets-Sheet l u u ll 5 \I\ "9 m IIII II v 2 w. w n 2 W n w n 5 5 a 5 X wywv dlr a VC 7 4 IL; M 5 a n w z IILIL m m /wm IIIAI us a P lNVENTOR. ALFRED L. MALLETT Nov. 18, 1969 A. L. MALLETT COUNTER RESETTING ARRANGEMENT FOR RHYTHM ACCOMPANIMENT STARTING Filed Feb. '7, 1966 4 Sheets-Sheet 2 I/VI/ENTOR. ALFRED L. MALLE'TT NOV. 18, A, L. MALLETT COUNTER RESETTING ARRANGEMENT FOR RHYTHM ACCOMPANIMENT STARTING Filed Feb. 7, 1966 4 Sheets-Sheet 5 //vl E/V7'0R. I ALFREDL. MALLETT BY fuzz a A. L. MALLETT 3,478,633

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COUNTER RESETTING ARRANGEMENT FOR RHYTHM ACCOMPANIMENT STARTING Filed Feb. 7, 1966 Nov. 18, 1969 United States Patent 3,478,633 COUNTER RESETTING ARRANGEMENT FOR RHYTHM ACCOMPANIMENT STARTING Alfred L. Mallett, Pittsfield, N.H.. assignor to The Seeburg Corporation, Chicago, 111., a corporation of Delaware Filed Feb. 7, 1966, Ser. No. 538,527 Int. Cl. Gf 1/00; H031: 23/08, 21/00 US. Cl. 841.03 16 Claims ABSTRACT OF THE DISCLOSURE This invention relates generally to the resetting of a binary counter and, more particularly, to the resetting of a counter to provide an electronically produced rhythm accompaniment starting on the first downbeat of an instrumentalists play.

The advent of electronic musical instruments, such as an electronic guitar or an electronic organ, has permitted an individual instrumentalist to obtain a much greater range of musical effects. One' such additional effect is the electronic production of a rhythm accompaniment, such as that produced by drums, cymbals, brushes, etc. The various electronic devices producing these individual rhythm effects are controlled to produce the desired sounds at the proper beat.

One method of accomplishing rhythm accompaniment control is to utilize a multistage binary counter and a logic matrix to produce control signals. These control signals are then applied to the proper audio production circuits to provide a rhythm accompaniment program that is cyclically repeated. In such an arrangement, it is desirable to have the rhythm accompaniment cycle begin precisely upon the playing of the initial downbeat by the instrumentalist, so that the previously arranged program of rhythm accompaniment properly coincides with the music played by the instrumentalist. Such a synchronism between the music of the instrumentalist and the rhythm accompaniment may be achieved by the instrumentalist listening to the playing of the rhythm accompaniment until it is about to begin a new cycle, and then playing his downbeat. Besides producing an undesired solo rendition of the rhythm accompaniment prior to play of the instrumentalist, this method of synchronism has the disadvantage of forcing the instrumentalist to adjust his opening downbeat to the electronic rhythm accompaniment. Further, if the previous play terminated near the beginning of the cycle of the rhythm accompaniment, the instrumentalist may have to wait for nearly the entire rhythm accompaniment cycle before he may begin to play in synchronism with the rhythm accompaniment. To obviate the disadvantages that exist in this manner of synchronizing the play of the instrumentalist and of the rhythm accompaniment, the present invention was evolved to provide resetting of the counter so that the rhythm accompaniment will be conditioned to' the beginning of its cycle whenever the instrumentalist wishes to begin play. 7

Briefly, in the preferred embodiments described herein, the subject invention involves a binary pulse counter having a plurality of counter stages. A driving pulse generator, such as a unijunction transistor (UJT) relaxation oscillator, produces input pulses for the counter stages. Each of the stages comprises a pair of transistors connected in a flip-flop arrangement. The collector of a preselected transistor in each of the flip-flop circuits is connected to a common, or reset, line through a unidirectional conducting device, such as a diode. The reset lineis connected to a reset transistor located in a reset circuit. Selectively operable reset actuating means initiate resetting of the counter circuit. A control circuit places the transistor in a conducting state when the reset circuit sets' the counter to a reset state.

one of the embodiments disclosed herein, the reset transistor has its collector-emitter circuit connected from the reset line to ground. The reset actuating means comprises a pedal operated push-push switch which, when actuated to the reset position, mutes the rhythm accompaniment audio output and causes the reset transistor to be placed in a saturated conducting state. Conduction of the reset transistor grounds the reset line and causes the pre=selected transistors in the flip-flop stages to be set to a reset state corresponding to one time sequence increment prior to the beginning of the rhythm accompaniment cycle. Thus, the next succeeding beat (which will correspond to the instrumentalists downbeat) will also be :th-e beginning of the rhythm accompaniment cycle. In a variation of this embodiment, the reset actuating means comprises a reset pulse signal, rather than a push-push switch. To obtain simultaneous muting of the audio output, an additional transistor, which is responsive to the reset pulse signal, is needed in this variation.

Another specific embodiment of the subject invention involves a resetting of the counter by racing the counter through its successive states until the desired reset state is achieved. A second unijunction transistor (UJT) relaxation oscillator, which produces race pulses having a frequency much greater than the frequency of the normal input pulses to the counter is utilized to achieve the racing by driving the counter at a much greater rate than normal. During normal operation the control capacitor of the UJT relaxation oscillator is shorted to ground through a diode. When reset is desired, a reset pulse signal is applied to backbias the diode and permit the race pulse generator to begin operation. Simultaneously with the counter reset, the reset pulse signal causes the audio output to be muted and resets the driving pulse generator. The emitter of the reset transistor is connected to the reset line, while the collector of the reset transistor is connected to the charged side of the control capacitor in the U] T race pulse generator circuit. When the counter has progressed to the desired reset state, i.e., a state correspending to one time sequence increment prior to the beginning of the rhythm accompaniment cycle, no positive voltage will appear on the reset line, and the reset transistor will be placed in a conducting state. While the reset transistor is conducting, the control capacitor in the UJT race pulse generator circuit is discharged through the reset transistor, and thus the race pulse generator circuit is disabled when the counter circuit is set to the reset state.

Accordingly, a primary object of the present invention is to provide for the synchronization of the beginning of a rhythm accompaniment cycle with the downbeat of music played by an instrumentalist.

Another object of this invention is to provide a reset arrangement for a rhythm accompaniment counter circuit in order to permit an instrumentalist to begin the playing of a rhythm accompaniment cycle in synchronism with his initial downbeat.

A further object of this invention is to provide for the muting of a rhythm accompaniment audio output while the rhythm accompaniment counter circuit is being reset in order to have the rhythm accompaniment begin its cycle in synchronism with the downbeat of an instrumentalist.

These and other objects, advantages, and features of the subject invention will hereintafter appear, and, for purposes of illustration, but not of limitation, exemplary embodiments of the subject invention are shown in the appended drawings in which:

FIGURE 1 is a schematic circuit diagram of one embodiment of the present invention;

FIGURE 2 is a detailed schematic circuit diagram of the circuit illustrated in FIGURE 1;

FIGURE 3 is a schematic circuit diagram illustrating the operation of one portion of the circuit illustrated in FIGURE 2;

FIGURE 4 is a schematic circuit diagram similar to FIGURE 1, but illustrating a second embodiment of the present invention;

FIGURE 5 is a schematic circuit diagram which illustrates one of the advantages of the FIGURE 4 circuit;

FIGURE 6 is a schematic circuit diagram similar to FIGURE 1, but showing yet another embodiment of the present invention;

FIGURE 7 is a timing chart useful in explaining the operation of the counter circuit utilized in the present invention; and

FIGURE 8 is a timing chart which is of additional help in explaining the operation of the counter circuit utilized in the present invention.

With reference to the embodiment illustrated in FIG- URE 1, a binary counter 1 is shown in block diagram form. Binary counter 1 comprises a plurality of counter stages U, V, W, X, Y and Z (shown only in block form in this figure). A driving pulse generator 3 (shown only in block form in this figure) supplies driving pulses for the binary counter 1. Each of the stages U, V, W, X, Y and Z is connected to a common, or reset, line 5 through a

diode

7, 9, 11, 13, and 17, respectively. Pulse generator 3 is also connected to reset line 5 through a resistor 19 and a diode 21. Reset line 5 is connected to a bias potential V through a resistor 23.

Binary counter 1 is connected to a reset circuit 33, as follows. A reset transistor 25 connects reset line 5 to ground. Transistor 25 has an emitter 27 connected to ground, a collector 29 connected to reset line 5, and a base 31. Reset circuit 33 further includes a selectively operable reset actuation means, which takes the form of a pedal operated push-push switch 35 in this particular embodiment. Switch 35 has a movable contact element 37 and

stationary contacts

39 and 41. Also included in reset circuit 33 is a control means for reset transistor 25 comprising: a capacitor 43 connected between a junction 53 and ground; a charging resistor 45 connected between a bias potential V and junction 53; a discharging resistor 47 connected between contact 41 and junction 53; and a base resistor 49 connected between the base 31 of transistor 25 and junction 53. A signal from control capacitor 43 is transmitted to base 31 of transistor 25 through a resistor 49, and the audio output of the rhythm accompaniment circuit appears on line 51, which terminates in contact'39.

During the time that the rhythm accompaniment is being audibly transmitted, movable contact 37 of switch 35 is positioned in abutment with stationary contact 41. With switch 35 in this position, current flows from V through

resistors

45 and 47 to ground. Resistor 45 is chosen at a considerably larger value than resistor 47, so that the voltage potential at point 53 is relatively close to ground, in order to maintain reset transistor 25 in a relatively low conducting state (preferably, a non-conducting or cutoff state). In this low conducting state, the impedance of transistor 25 is correspondingly high, and accordingly the potential on reset line 5 is essentially V This potential back-biases diodes 7-17, and the counter operation remains unafifected by the voltage condition on line 5.

When the electronic musical instrument is first turned on, or when the instrumentalist is desirous of starting a new tune, the counter will be reset to synchronize the instrumentalists downbeat and the beginning of the cycle of operation of the rhythm accompaniment. Resetting of the counter 1 is achieved by transferring movable contact 37 from stationary contact 41 to stationary contact 39. In the 37-39 position of switch 35, line 51 is grounded so that the audio output on line 51 is muted. Also, with the switch 35 in this position, the relatively low impedance resistor 47 that normally shunts capacitor 43 is open-circuited, and the charge on capacitor 43 begins to increase. This increased potential across capacitor 43 is transmitted to base 31 of transistor 25 through resistor 49 to drive the reset transistor 25 into a saturated conducting state. With transistor 25 in a saturated condition, reset line 5 approaches ground potential. The ground potential appearing on reset line 5 biases diodes 7-17 to drive each of the counter stages U-Z into a pre-selected reset state corresponding to one time sequence increment prior to the beginning of the rhythm accompaniment cycle. Also, the ground potential on reset line 5 biases diode 21 to reset pulse generator 3 and thereby insure that the pulses produced by generator 3 will occur at the proper time to provide synchronization between the downbeat of the instrumentalist and the beginning of the rhythm accompaniment cycle. Upon the downbeat of the instrumentalist, movable contact 37 of switch 35 is moved back to contact 41, and binary counter 1 resumes operation with the desired synchronization.

To aid in further comprehending the exact operation of the embodiment illustrated in FIGURE 1, reference may be made to FIGURE 2. In this figure, the W and X stages have been omitted for simplicity, as they are identical to the U and V stages. It may be seen that each of the stages comprises a pair of

transistors

55 and 57 connected in a flip-flop configuration. Transistor 55 has an emitter 59, a collector 61, and a base 63, while transistor 57 has an emitter 65, a collector 67, and a base 69. Both of the

emitters

59 and 65 are connected to ground. Collector 67 of transistor 57 is connected to reset line 5 through a respective one of the diodes 7-17 (e.g.,

diodes

15 and 17 for stages Y and Z, respectively, in FIGURE 2), and collector 61 of transistor 55 is connected to the next succeeding stage in the counter. The flip-flop circuit in each of the counter stages also includes a circuit arrangement 71, illustrated in block form. Seven terminals labeled A-G are shown in each circuit 71. Terminals A-G may be compared to the similarly lettered terminals in FIGURE 3, wherein the details of circuit 71 are illustrated.

In FIGURE 3, a circuit 71 is shown in conjunction with a pair of flip-

flop transistors

55 and 57. Terminals A and B of circuit 71 are connected to a resistor 73 and a capacitor 75, respectively. Resistor 73 and capacitor 75 are also connected to a line 77.

Resistors

79 and 81 are connected between line 77 and terminals C and G, respectively. A parallel arrangement of a capacitor 83 and a resistor 85 is connected between terminals C and D, while a similar parallel arrangement of a capacitor 87 and a resistor 89 is connected between terminals G and F. A resistor 89 is connected between terminals D and E, and a resistor 91 is connected between terminals E and F. A capacitor 93 is connected between terminals D and F to form a parallel circuit with resistors 8'9 and 91.

Besides the internal arrangement of circuit 71, FIG- URE 3 also illustrates the external connections of terminals A-G to the flip-

flop transistors

55 and 57. Terminal C is connected to the collector 67 of transistor 57, while collector '61 of transistor 55 is connected to terminal G. Terminal D is connected to base 63 of transistor 55, and terminal F is connected to base 69 of transistor 57. Terminal B is connected to

emitters

59 and 65, and to ground. The external connections of terminals A and B are shown in FIGURE 2. Terminal A is connected to a source of, bias potential V while terminal B is connected to a collector 117 of a transistor 114 in the case of stage Z and to the terminal G (and thus the collector 61) of the next preceding stage in the case of the remaining stages (i.e., from left to right in the drawings, so that terminal B of stageY is connected to terminal G of stage Z).

With reference again to FIGURE 2, it may be seen that the pulse generator 3 comprises a unijunction transistor (UJT) 93. UJT 93 has an emitter 95, a base-one 97 and a base-two 99. Base-two 99 is connected to the source of potential V through a resistor 101, while base-one 97 is connected to ground through a resistor 103. A storage capacitor 105 is connected between emitter 95 and ground. Emitter 95 is also connected to reset line 5 througli'previously mentioned resistor 19 and diode 21. A source of positive potential V is applied to a potentiometer 107, and the potential from potentiometer 107 is then applied toa potentiometer 109, which serves as a tempo control for the rhythm accompaniment. The potential from tempo control, potentiometer 109 is then applied to emitter 95 and capacitor 105 through a resistor 111.

Driving pulse generator 3 is a conventional type of unijunction transistor relaxation oscillator. When the source potential V is applied to potentiometer 107, capacitor 105 is charged through potentiometer 107, tempo control potentiometer 109, and resistor 111. When capacitor 105 has charged sufficiently to cause the voltage on emitter 95 to exceed the breakdown potential between emitter 95 and base-one 97, capacitor 105 will be discharged through emitter 95, base-one 97, and resistor 103 to ground until capacitor 105 is discharged below the reverse bias condition of emitter 95, after which the cycle of operation'will berepeated. The current flow through resistor 103: produces an output pulse at terminal 112. Tempo control potentiometer 109 performs the desired tempo control function by varying the time constant for the charging of capacitor 105.

The output pulses produced at terminal 112 are transmitted to base 113 of transistor amplifier 114 through a capacitor 115 and a resistor 116. A by-pass resistor 116 is connected to ground from a junction 112' between capacitor 115 and resistor 116. Collector 117 of transistor 114 is connected to the source of potential V through resistor 118, while emitter 119 of transistor 114 is connected to ground. Upon the appearance of a pulse from pulse generator'3, transistor 114 is biased to a heavily conducting state, so that the voltage drop across resistor 118 produces a negative-going pulse on terminal B of circuit 71. Again, it should be noted that terminal A of circuit 71 is connected to the source of potential V With reference to FIGURE 3, the actual operation of an individual counter stage flip-flop may now be described. When the counter circuit is initially energized, one or the other of the

transistors

55 and 57 in each stage U-Z will begin to conduct. Which of the transistor is put into a conducting state will depend upon the particular circuit imbalances that exist. For purposes of this description, it will be assumed that transistor 55 initially is placed in a conducting state. When transistor 55 is conducting, terminal G is essentially at ground potential, and terminal C is at a relatively high potential, but less than the potential V at terminal A due to the potential drops across

resistors

73 and 79, resulting from the current flow through resistor 73 and the parallel paths comprising resistor 81 and transistor 55, and resistors 79, resistor 85 and resistor 89 to ground. With these circuit conditions, terminal D, which is connected to base 63 of transistor 55, rises toward a potential of half that appearing on terminal C, but limited to the potential drop across the base-emitter diode junction of transistor 55. On the other hand, terminal F, which is connected to the base 69 of transistor 57, is essentially at ground potential, so that transistor 57 remains in a non-conducting state.

Upon the application of a negative-going pulse to terminal B from the collector 117 of transistor 114 (or from the collector 61 of a transistor 55 in a preceding stage), the conducting state of

transistors

55 and 57 will be reversed. During the conduction of transistor 55, capacitor 83 is charged to approximately one-half the potential appearing on terminal C, with the polarity shown in FIG- URE 3. When the negative pulse is applied to terminal B, capacitor 83 will discharge with a current path from ground through resistor 89, capacitor 83, and resistor 79 to capacitor 75. This direction of current flow will cause a negative pulse to be formed at terminal D and thus transmitted to base 63 of transistor 55. This negative pulse will back-bias the emitter-base junction of transistor 55 and cause transistor 55 to assume a non-conducting state. During the time that transistor 55 is shutting off, the initial rush of charging current gives capacitor a charge with the polarity shown, so that the potential V on terminal A is no longer shorted across capacitor 75, as it was upon initial application of the negative-going pulse. Thus, there is a potential drop across resistor 91, due to the current flow therethrough, and terminal F is at some voltage value above ground potential. This potential is enough to forward-bias the emitter-base junction of transistor 57. Also, the discharge of capacitor 83 through resistor 79 raises the voltage at terminal C above the potential on line 77, so that the collector-base junction of transistor 57 is also forward biased. With both of these junctions forward biased, transistor 57 will begin to conduct current. As the current flow through transistor 57 increases, the potential drop across resistor 79 also increases, so that the potential of line 77 is increased, and the voltage appearing at terminal F is increased. This increased potential at terminal F will continue to drive transistor 57 into a higher conducting state until transistor 57 reaches a saturated conducting condition. At the same time, terminal C is brought essentially to ground potential, and thus terminal D is maintained at ground potential to hold transistor 55 in non-conducting state. Upon the application of another negative-going pulse to terminal B, the reverse operation will occur and transistor 55 will be placed in a conducting state.

In each of the counter stages UY, the flip-flop type of action described above will occur. However, a slightly different type of action is achieved in stage Z by the provision of a feedback circuit. By reference to FIGURE 2, it may be seen that the feedback circuit comprises a capacitor 121 and a resistor 123, connected in series between collector 67 of transistor 57 in stage Y and base 69 of transistor 57 in stage Z. By utilizing this feedback circuit, the counter is given a 36-122448 counting progression, rather than the normal binary sequence of 4816-32-64. To understand how this i achieved, assume that transistor 57 in both stages Y and Z is conducting. When a negative pulse is applied to terminal B in stage Z, transistor 55 will be placed in a conducting state so that a negative pulse is applied to terminal B in stage Y. The negative pulse appearing at terminal B in stage Y causes transistor 57 in stage Y to cease conducting so that a positive-going pulse appears on collector 67 of transistor 57. This positive-going pulse is fed back through capacitor 121 and resistor 123 to base 69 of transistor 57 in stage Z. The positive pulse appearing on the base of transistor 57 in stage Z causes transistor 57 to begin conduction and to return transistor 55 to a non-conducting state. Thus, this conducting state of transistor 55 is essentially eliminated, and a base of 3 is established for the counter.

A variation of the FIGURE 1 embodiment is shown in FIGURE 6. In the FIGURE 6 embodiment, a counter circuit identical with that shown in FIGURE 1 is utilized. Each of the stages U-Z is connected to a reset line 5 through a corresponding diode 7-17. Similarly, pulse generator 3 is connected to reset line 5 through resistor 19 and diode 21, while a source of potential V is connected to reset line through resistor 23. In the reset circuit 33 of FIGURE 6, a transistor 25 has its collector 29 connected to reset line 5 and its emitter connected to ground, as in the FIGURE 1 embodiment. However, instead of a push-push switch 35, the selectively operable reset actuating means in the FIGURE 6 embodiment comprises a reset pulse 125 (schematically illustrated in FIG- URE 6). Reset pulse 125 is produced, in response to the instrumentalists desire to reset the counter circuit, by conventional pulse production means (not shown) controlled by the instrumentalist. Reset pulse 125 is connected to the reset circuit by a coupling capacitor 127, and appears across a grounded control resistor 129. A pulse produced across resistor 129 is applied to base 31 of reset transistor 25 through a resistor 131. When a reset pulse appears at base 31 of transistor 25, the transistor is placed in a highly conducting state, so that reset line 5 approaches ground potential and the counter is reset, as explained in connection with the FIGURE 1 embodiment.

Since the FIGURE 6 embodiment does not have a switch for its reset actuating device, it is necessary to provide some other arrangement for muting the audio output of the rhythm accompaniment audio generators. This is accomplished by utilizing an additional transistor 133. When a reset pulse appears across resistor 129 and is applied to transistor 25, it is also applied to a base 135 of a trnasistor 133 through a resistor 137. Emitter 139 of transistor 133 is connected to ground, while collector 141 is connected to a source of potential V through a resistor 143. The rhythm accompaniment audio output appears on line 145 and is connected to collector 141 of transistor 133 through a diode 147. Application of a reset pulse to transistor 133 places transistor 133 in a highly conducting state, and the audio output is muted by grounding line 145 through diode 147 and transistor 133. During normal operation of the counter, diode 147 is back-biased by the potential V appearing at the juncture of resistor 143 and collector 141 of transistor 133, and the audio output on line 145 is not affected.

Another embodiment of the present invention is illustrated in FIGURE 4. In this embodiment, the counter is essentially the same as that used in the embodiments of FIGURES 1 and 6, with each stage U-Z being connected to a reset line 5' through a respective diode 717'. However, pulse generator 3 is not connected to the reset line 5', as in the other embodiments. A reset circuit 149 is shown in conjunction with the counter circuit of this embodiment. A reset transistor 151 in reset circuit 149 is connected to reset line 15. Reset transistor 151 has an emitter 153, a base 155, and a collector 157. Emitter 153 is connected directly to reset line 5' and also to ground through a control resistor 159. Base 155 of transistor 151 is connected to the midpoint of a voltage divider comprising resistors 161 and 163. Resistors 161 and 163 are connected in series between a source of potential V and ground. Thus, this voltage divider provides the base bias for transistor 151 and serves, with resistor 159, as a control circuit to establish the state of conduction of transistor 151. Collector 1-57 of transistor 151 is connected to one side of a capacitor 165 through a line167.

Capacitor 165 is the storage element in a unijunction transistor (UJT) relaxation oscillator comprising a unijunction transistor 169;

resistors

171, 173, and 175; and capacitor 165. This UJT oscillator serves as a race pulse generator to provide pulses having a frequency much greater than the frequencies of the pulses produced by pulse generator 3', in order to drive the counter through its counting cycle at a much greater rate than the normal counting rate.

Emitter 177 of UJT 169 is connected to line 167. Basetwo 179 of U] T 169 is connected to a source of potential V through a resistor 171, while base-one 181 is connected to ground through a resistor 173. Base-one 181 of UJT 169 is also connected to the first counter stage by a lead 183. A charging voltage for capacitor is provided by a source of potential V through a resistor 175.

During normal operation, capacitor 165 remains in an uncharged state because of a current path through a diode 185 and a resistor 187 to ground. If the instrumentalist desires to reset the counter, and the rhythm accompaniment, he actuates the mechanism under his control (by conventional means, not shown) to produce a reset pulse 189 on line 190 (shown schematically in FIGURE 4). In order to insure proper resetting of the counter 1 regardless of the counter state at the time of resetting, reset pulse 189 should have a time duration at least as long as the time that it takes the race pulse generator to drive the counter through 47/48 of one cycle. Reset pulse 189 back-biases diode 185 and permits capacitor 165 to charge until the emitter breakdown voltage of UJT 169 is reached, at which time capacitor 165 will discharge through emitter 177, base-one 181, and resistor 173 to ground. The indicated current flow through resistor 173 produces a voltage pulse on line 1 83 which is applied to the first stage of the counter. The values of capacitor 165 and of resistors 175 and 173 are chosen to make the race pulse generator produce pulses at a rate several magnitudes greater than the rate of the pulse generator 3'. Thus, the counter will be raced through its cycle to the reset state, which corresponds to one time sequence increment prior to the beginning of the rhythm accompaniment cycle. When the reset state is reached, it is the only condition in which no positive pulse appears on reset line 5 (as will be explained in greater detail below). Thus, the voltage on reset line 5' will go in a negative direction to cause transistor 151 to begin conduction. As transistor 151 begins conduction, capacitor 165 is by-passed to ground (through conducting transistor 151), and no charge accumulates on capacitor 165, so that the race pulse generator is disabled. In

this manner, transistor 151 is placed in a highly conducting state upon reset to terminate the race operation once the reset state is reached.

There are two other functions that must be accomplished during this reset action. One of these is to mute the audio output of the rhythm accompaniment, while the other is to reset pulse generator 3' so that the pulses to the counter will occur at the right times after reset. Both of these functions are accomplished by a transistor 191 which has an emitter 193, a base 195, and a collector 197. Emitter 193 is connected directly to ground, while collector 197 is connected to a source of potential V through a resistor 199. Collector 197 is also connected to a junction 200, to which a pair of

diodes

201 and 203 are also connected. Diode 201 is connected'to a line 205 upon which the audio output of the rhythm accompaniment appears, while diode 203 is connected to a line 207 connected to the input of pulse generator 3'. Base 195 of transistor 191 is connected through a resistor 208 to the point between diode 185 and resistor 187, to which the line 190, on which the reset pulse 189 appears, is connected. The presence of a reset pulse 189 at the base 195 of transistor 191, forces transistor 191 into a highly conducting state so that line 205 is grounded to mute the audio output, and line 207 is grounded to reset pulse generator 3'.

The embodiment shown in FIGURE 4 is particularly useful because it permits the use of a flashing tempo indi cator lamp, a circuit for which is shown in FIGURE 5, even during muting of the audio output. An output from a pre-selected one of the counter stages is applied to the tempo indicating lamp circuit of FIGURE 5 at a terminal 209. This counter stage output is fed to the base of a transistor 211 through a capacitor 213 and a resistor 215 in series. The base of transistor 211 is also connected to ground through a resistor 217. The emitter-collector circuit of transistor 211" is connected in the base-collector circuit of a transistor 219. By this arrangement, the con-' duction of transistor 211, as a result of a counter stage output applied at terminal 209, will cause transistor 219 to be placed in a highly conducting state. The collectors of both

transistors

211 and 219 are connected to one side of a lamp 221, and the other side of lamp 221 is connected to a source of potential V through a resistor 223. A storage capacitor 225 is connected to ground from the common connection of resistor 223 and lamp 221.

When an output pulse from the pre-selected counter stage is received at terminal 209, transistor 219 will begin to conduct, and capacitor 225 will discharge through lamp 221 and transistor 219. This discharge through lamp 221 will cause lamp 221 to light and thus to indicate the existence of the predetermined counter output on terminal 209. Since lamp 221 will light in a flashing manner at the same point in every cycle of the counter operation, it serves as an indication of the rhythm accompaniment tempo.

By reference to the timing charts of FIGURES 7 and 8, the operation of the counter circuit andthe reset circuit of the subject invention may be more fully comprehended. In both of these figures, the output pulses of the driving pulse generator have been sequentially numbered. In FIGURE 7 the complete operation of the counter for 48 pulse generator pulses (i.e., -47) is illustrated. Each of the primed and unprirned letters indicates a negative pulse appearing on the terminal of that designation (the terminal designation being illustrated in FIGURE 2).

In the charts, a particular outputcontinues as originally designated unless a change is expressly shown.

With transistors 55 originally conducting (in all stages except stage Z where transistor 57 is in a conducting state), the unprirned terminals U-Y are essentially grounded, and the output would be that as indicated at zero in FIGURE 7. Actually, there is no unprirned output indicated for the Z stage (since that particular quantity This state of transistor 55 causes a negative pulse to be applied to terminal B in circuit 71 in stage Y, which causes transistor 57 in stage Y to assume a conducting state and produce a Y output as shown under 1 in FIG- URE 7. A second pulse from pulse generator 3 will cause transistor 57 in stage Z to conduct and produce the Z output shown under 2 in FIGURES 7 and 8. This second pulse also causes transistor 55 in stage Z to be transferred to a non-conducting state and thus to produce a positive output at terminal B in stage Y. However, the counter responds only to negative driving pulses, so that stage Y is not affected by the application of the positive pulse on terminal B.

Upon the application of the third input pulse from the pulse generator, stage Z is transferred from the Z to the Z stage. This in turn causes a negative pulse to be applied to terminal B in circuit 71 of stage Y so that stage Y is transferred from the Y to the Y state.- This transferal of stage Y from the Y to the Y state'also produces a negative pulseat terminal B in stage X, so that stage X is transferred from the X to the X state. In a normal binary counter, this is all that would occur. However, in this particular arrangement, the feedback circuit comprising capacitor 121 and resistor 123 causes the positive voltage appearing on the collector of transistor 57 in stage Y to be applied to the base of transistor 57 in stage Z. This feedback'signal causes transistor 57; in stage Z to begin to conduct and, thus, shut off transistor in that stage. This means that stage Z of the counter has been returned to theZ state as indicatedunder 3 in FIGURE 8. Therefore, every third and fourth step in the operation of counter stage Z are in effect combined, so that counter stage Y has a base of} rather: than of 4.

The above-described type of operation will continue until at the 47th input pulse from the unijunction oscillator pulse generator, each of the stages will be in the primed state. This point in the counter circuit cycle, which is one time sequence increment prior to the beginning of the rhythm accompaniment cycle, is defined as the reset state. With the next incoming pulse the counter will be caused to begin its normal cycle and, since the next pulse will represent the instrumentalists downbeat, the rhythm accompaniment will be synchronized with the play of the instrumentalist. Since the reset state corresponds to a negative signal on the collectors of transistors 57, it may be seen that reset line 5 in the FIGURE 4 embodiment will not have a positive signal applied to it during the reset state, so that transistor 151 will be transferred to a conducting state. Also, it may be seen that the application of a negative or ground signal to reset line 5 in the FIG- URE 1 and FIGURE 6 embodiments will drive all of the stages to a primed output state, so that the counter is in the reset state.

While this description has been primarily directed to the counter and counter reset circuits, it should be realized that the counter output signals are conveyed to a known type of logic matrix (not shown). The logic matrix produces control signals that are arranged in 'a predetermined pattern or program to activate individual audio producing devices. As the audio producing devices are activated, a desired rhythm accompaniment cycle is produced. The rhythm accompaniment cycle adds a new dimension to the music played by an individual instrumentalist, and, by utilizing the present invention, the instrumentalist may be assured of having the rhythm accompaniment cycle start in synchronism with his initial downbeat.

It should be understood that the embodiments described are merely exemplary of the preferred practices of the present invention and that various changes, modifications, and variations may be made in the arrangements,

operations, and details of construction of the elements the scope of the present invention, pended claims.

What is claimed is:

1. A binary counter comprising:

a driving pulse generator comprising a unijunction transistor relaxation oscillator circuit;

a plurality of counter stages, said driving pulse generator being connected to the first of said counter stages, and each of said counter stages comprising a pair of transistors connected in a flip-flop configuration;

a common line, each of said counter stages having the collector of a pre-selected one of said pair of transistors therein connected to said common line through an associated unidirectional conducting device;

a reset circuit for setting the counter to a predetermined reset state and for setting said driving pulse generator to a reset condition simultaneously with the setting of said counter to said reset state, said reset circuit including a reset transistor connected to said common line and said common line having a negative-going voltage thereon when said reset circuit sets the counter to said reset state;

selectively operable reset actuating means for causing saictll reset circuit to set the counter to said reset state; an

control means included in said reset circuit for placing said reset transistor in a saturated conducting state when said reset circuit sets the counter to said reset state through operation of said reset actuating means.

2. A counter as claimed in claim 1 wherein:

the emitter of the unijunction transistor in said unijunction transistor relaxation oscillator circuit is connected to said common line through a unidirectional conducting device;

said reset transistor has its collector connected to said as defined in the ap- 00131111011 line and its emitter connected to ground; an

said reset circuit includes circuit means for applying a positive reset voltage to the base of said reset transistor when said counter is to be reset,

whereby said reset transistor is placed in a saturated conducting state, thereby connecting said common line to ground to set said counter in said reset state which corresponds to a low voltage condition on each of the transistor collectors connected to said common line, and to set said driving pulse generator to a reset condition corresponding to a low voltage on said emitter of the unijunction transistor in said unijunction transistor relaxation oscillator circuit.

3. A counter as claimed in claim 2 wherein:

said reset actuating means comprises a selectively operable push-push switch; and

said control means comprises a capacitor which charges to a potential high enough to place said reset transistor in a saturated conducting state when said switch is located in a reset position.

4. A counter as claimed in claim 2 wherein:

said reset actuating means comprises a positive-going reset pulse signal; and

a said control means comprises a resistor connected to the base of said reset transistor to raise said base above ground potential and place said reset transistor in a saturated conducting state when said reset pulse is applied to said reset circuit.

5. A counter as claimed in claim 1 wherein:

said reset transistor has its emitter connected to said common line;

said control means comprises a resistor connected from the emitter of said reset transistor to ground and a biasing arrangement for the base of said reset transistor;

said reset circuit further comprises a race pulse generator connected to the first stage of said counter to drive said counter at a much greater rate than the driving rate attributable to said driving pulse generator; and

said reset actuating means comprises a reset pulse signal,

whereby application of said reset pulse signal to said reset circuit causes said counter to be raced to said reset state, at which time said reset transistor will be placed in a saturated conducting state to disable said race pulse generator.

6. A counter as claimed in claim *5 wherein:

said race pulse generator comprises a unijunction transistor relaxation oscillator including a frequency controlling capacitor connected to the emitter of the unijunction transistor in said unijunction transistor relaxation oscillator, the emitter of said unijunction transistor being connected to ground through a diode to normally discharge said capacitor;

said reset pulse signal back-biases said diode to permit said capacitor to charge and initiate operation of said race pulse generator upon application of said reset pulse signal to said reset circuit; and

the collector of said reset transistor is connected to the emitter of the unijunction transistor in said race pulse generator to discharge said capacitor When said reset transistor is in a saturated conducting state.

7. A counter as claimed in claim 6 wherein said reset circuit further comprises a driving pulse generator resetting transistor which is placed in a saturated conducting state by said reset pulse signal to ground the emitter of the unijunction transistor in said driving pulse generator and set said driving pulse generator to a reset condition upon application 0t said reset pulse signal to said reset circuit.

8. An arrangement for synchronizing the beginning of play of an electronically produced rhythm accompaniment cycle with the beginning of play by an instrumentalist comprising:

a binary counter having a plurality of stages for controlling the production of a rhythm accompaniment audio signal, each of said counter stages comprising a pair of transistors connected in a flip-flop configuration;

driving pulse generator;

a common line, each of said counter stages having the collector of a pre-selected one of said pair of transistors thereon connected to said common line through an associated unidirectional conducting device;

a reset circuit comprising a transistor connected to said common line, said reset circuit being operatively connected to said counters for setting said counters to a reset state corresponding to one time sequence increment prior to the beginning of the rhythm accompani ment cycle and for setting said driving pulse generator to a reset condition simultaneously with the setting of said counter to said reset state;

selectively operable reset actuating means for causing said reset circuit to set said binary counter to said reset state;

control means included in said reset circuit for placing said reset transistor in a saturated conducting state when said reset circuit sets said counter to said reset state through operation of reset actuating means; and

audio muting means for muting the rhythm accompaniment audio signal during the resetting of said binary counter.

9. An arrangement as claimed in claim 8 wherein: said driving pulse generator comprises a unijunction transistor relaxation oscillator circuit;

said reset transistor has its collector connected to said common line and its emitter connected to ground; and

whereby said reset transistor is placed in a saturated conducting state, thereby connecting said common line to ground to set said counter in said reset state which is equivalent to a low voltage condition on each of the transistor collectors connected to said common line and to set said driving pulse generator to a reset condition corresponding to a low voltage on said emitter of the unijunction transistor in said unijunction transistor relaxation oscillator circuit.

10. A circuit as claimed in claim 9 wherein:

said reset actuating means comprises a selectively operable push-push switch;

said control means comprises a capacitor which charges to a potential high enough to place said reset transistor in a saturated conducting state when said switch is located in a reset position; and

the setting of said switch to said reset position connects said line on which said rhythm accompaniment audio output signal appears to ground.

11. A circuit as claimed in claim 10 wherein:

said reset actuating means comprises a positive-going reset pulse signal;

said control means comprises a resistor connected to the base of said reset transistor to raise said base above ground potential and place said reset transistor in a saturated conducting state when said reset pulse is applied to said reset circuit; and

said audio muting means comprises an audio muting transistor which is placed in a saturated conducting state by said reset pulse signal in order to connect to ground said line on which said rhythm accompaniment audio output signal appears.

12. An arrangement as claimed in claim 8 wherein:

said reset transistor has its emitter connected to said common line;

said reset circuit further comprises a race pulse generator connected to the first stage of said counter to drive said counter at a much greater rate than the driving rate attribtuable to said driving pulse generator; and

said reset actuating means comprises a reset pulse signal,

13. An arrangement as claimed in claim 12 wherein:

14. An arrangement as claimed in claim 13 wherein:

said driving pulse generator comprises a unijunction transistor relaxation oscillator circuit;

said reset circuit further comprises a driving pulse generator resetting transistor which is placed in a saturated conducting state by said reset pulse signal to ground the emitter of the unijunction transistor in said driving pulse generator and set said driving pulse generator to a reset condition upon application of said reset pulse signal to said reset circuit; and

said driving pulse generator resetting transistor further serves to connect to ground a line upon which said rhythm accompaniment audio output signal appears in order to mute said rhythm accompaniment audio output when said driving pulse generator resetting transistor is placed in a saturated conducting state by said reset pulse signal.

15. An arrangement for synchronizing the beginning of play of an electronically produced rhythm accompaniment cycle with the beginning of play by an instrumentalist comprising:

a binary counter having a plurality of stages for controlling the production of a rhythm accompaniment audio signal;

a driving pulse generator connected to the first of said counter stages;

a race pulse generator connected to the first stage of said binary counter to drive said counter at a much greater rate than the driving rate attributable to said driving pulse generator;

selectively operable reset actuating means for initiating operation of said race pulse generator upon operation thereof;

a reset transistor for disabling said race pulse generator when said binary counter circuit has been placed in a desired reset state; and

16. An arrangement as claimed in claim 15 and further comprising a driving pulse generator resetting transistor for setting said driving pulse generator to a reset condition and for muting the rhythm accompaniment audio signal upon initiation of operation of said race pulse generator.

References Cited UNITED STATES PATENTS 3,168,675 11/1962 Somlyody 328-48 3,183,367 3/1967 Berkel 32848 3,312,835 4/ 1967 Grasmiick 307-225 3,358,068 12/1967 Campbell 841.24

HERMAN KARL SAALBACH, Primary Examiner F. PRINCE BUTLER, Assistant Examiner US. Cl. X.R. 307220, 225