US3467945A - Electrically controlled matrix - Google Patents

Electrically controlled matrix Download PDF

Info

Publication number
US3467945A
US3467945A US541426A US3467945DA US3467945A US 3467945 A US3467945 A US 3467945A US 541426 A US541426 A US 541426A US 3467945D A US3467945D A US 3467945DA US 3467945 A US3467945 A US 3467945A
Authority
US
United States
Prior art keywords
conductors
matrix
signals
devices
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US541426A
Inventor
Oscar Myers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Application granted granted Critical
Publication of US3467945A publication Critical patent/US3467945A/en
Assigned to ITT CORPORATION reassignment ITT CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002Switching arrangements with several input- or output terminals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements

Definitions

  • matrices have been used in translators and in radix converters, i.e. in devices for receiving intelligence encoded in one code, or in one radix, and transmitting it in another code, or to another radix, without changes in substance, except for the possible deletion of some information.
  • translators made of a matrix of conductors, certain of which have been connected together through diodes at points where they cross each other. The diodes have been biased selectively to conduct when signals of the proper polarity and amplitude are applied to them over receiving connections.
  • Similar arrays of magnetic cores connecting input signals to se lected outputs have been used as information storage devices.
  • translator or speech matrices composed of electrical conductors.
  • the conductors are coupled at their cross-points by con nectors having variable values of resistance.
  • the variations in resistance of the resistors in turn are controlled by the application of certain setting potentials which are applied independently of any signals to be routed.
  • FIG. 1 is a diagram of a matrix of conductors arranged in accordance with one aspect of the invention
  • FIG. 2 is a diagram illustrating another embodiment of the invention.
  • FIG. 3 is a block diagram illustrating yet another embodiment of the invention.
  • FIG. 1 for a detailed showing of an embodiment of the invention.
  • a connection is made through a resistor Rla, Rlb, R2a, R2b, etc. and a corresponding diode Dla, Dlb, D2a, D2b, etc.
  • Fixed biasing potentials may be applied as priming potentials on terminals 1, 2, 3 N, or on terminals a, b z, so that the application of additional potentials on selected ones of terminals a, b z or terminals 1, 2, 3 N, respectively, tends to prepare the way for conduction between corresponding horizontal wires 1, 2 N and output leads A, B Z.
  • FIG. 1 embodies a third set of terminals at Tla, T2a, Tlb TNz upon which potentials may be applied to control the electrically settable variable resistors, which may be of the Pearson type (see Patent No. 3,117,013 to Northover and Pearson), at Rla, Rlb, RZa, R212, etc.
  • variable resistors are Pearson devices they can be made conductive or nonconductive in accordance with a third set of signals, which may represent a selective code.
  • output signals will be controlled as a result of potentials applied to three sets of conductors, instead of by potentials applied to the usual two sets to determine which of the terminals A, B Z will be graced by output signals.
  • the embodiment of the invention shown in FIG. 1 may be used as a translator which can accept signals in one code, such as a binary code, and translate them to another code, such as the well known Gray code.
  • the presence of the variable resistors makes possible the introduction of a third set of variables in the form of a third set of input signals so that the translator can be modified by elecrical means to translate different codes or to change from one radix conversion to another.
  • This embodiment of the invention may be used to translate called signals, such as telephone numbers, from one form to another in order to route telephone calls in a desired way. It can also be used to control the path of any data supplied in the form of electrical signals in parallel or to extend the speech paths of a switching system.
  • the embodiment of the invention shown in FIG. 1 may also serve as a memory matrix with Pearson devices at Rla, Rlb, R2a1, etc. serving as memory elements.
  • the multistable character of Pearson devices is employed by switching the Pearson devices between high and low resistance stages by the application of voltage pulses on terminals Tl a, Tlb, T2a, T2b
  • FIG. 1 can function without diodes providing might be represented by terminals Tla, Tlb Tlz or only that quality control of the variable resistor devices by terminal 1 of FIG. 1, can be used to stimulate a readis held at a high level.
  • An embodiment of another aspect of the invention B Z, where the verticals may previously have been is shown in FIG. 2 where a matrix of conductors is conset over terminals a, b z.
  • FIG. 2 shows an embodinected at crossover points through variable resistors Rla, merit of the invention which can also function as a mem- Rlb, R2a RNz and diodes Dla, Dlb, D2a ory device. If the equipment of FIG.
  • FIG. 2 is used as amem- DNz. It is apparent immediately that FIG. 2 may be disory device, the variable resistors can be set to have a tinguished from FIG. 1 by the absence of a third set of certain memory by the register or by coincidence of signal sources as well as by the presence of a register M signals from the register and over terminals a, b, c z. and a scanning switch 8. The scanning switch and the The verticals can then be systematically scanned over register in combination may have a sufficient voltage apterminals A, B, C Z by the scanning switch S.
  • a register Rlb, R2a etc. to switch to a low resistance state. such as is shown at M in FIG. 2, set by say, binary or This capability can cause the matrix to be set so that it decimal information could select a single horizontal on can function either as a translator for signals which are the basis of the registered information, and then energize then supplied from the register or couse it to perform the verticals as in the case of the memory.
  • the function of a simi-perrnanent storage or memory de As a matching translator, each horizontal may be previce.
  • a register 36 is also connected tials, to high or low resistance states, and to the stepping switch 34 through corresponding termimeans connected to receive said potentials for setting nals A, B Z.
  • a coded signal may be applied from each of said variable means to a desired state.
  • a terminal 38 t0 the regisief- The pp g switch 34 can 2.
  • An electrically settable switching device substantially then be caused to wipe corresponding terminals such as as lai ed in lai 1, in whi h; B and d a parison can be made of the resultunidirectional devices are connected in series with each ing signals in a coincidence circuit or an AND gate 40. of aid vari ble i t r means With this arrangement, an Output Signal Will be ppli 3.
  • An electrically settable switching device substantially at a terminal 42 only when a signal received from 32 as claimed in claim 1, in which: ponds to that t r i the register each variable resistor means is connected by two sep- Besides providing for additional functions, an arrangearate t rminal t t crgsspoints, d mam such as that Shown in 3 Provides greater fiexsaid means to receive said potentials for setting each ibility and speed than is possible with circuits correspondof said variable means includes a third terminal ing to the diagrams of FIG. 1 0r FIG. 2 alone.
  • the block coupled to each variable means. 32 for example, represents a complete translator or mem- 7 4.
  • a coordinate switching system comprising: ory which may be set or reset independently of the stepa plurality of conductors crossing one another, ping switch 34 or the regist r 36.
  • t is P ss le t interconnecting means interconnecting said conductors, change the conductivity of various resistors represented id int ti means i l i a bidi i by block 32 without interfering with the operation of the variable resistor controlled to two different resistance remainder of the circuit. levels by the direct application of potentials, and
  • a coordinate switching system substantially as claimed in claim 4, in which:
  • said interconnecting means includes a unidirectional device in series with said bidirectional variable resistor.
  • a coordinate switching system comprising: a plurality of conductors arrayed in a matrix to cross one another at crossover points, interconnecting means for interconnecting said conductors betweeen terminals at said crossover points, said interconnecting means including bidirectional resistor devices responsive to the direct application of potentials to switch their degree of resistance between two states, and means connected to selectively receive potentials to activate selected ones of said bidirectional devices.
  • said interconnecting means includes a unidirectional device in series with each of said bidirectional resistor devices.
  • An electrically settable switching device comprising:
  • variable resistor means interconnecting each of said crosspoints
  • variable resistor means being settable by the application of voltage to semi-permanent conductive or non-conductive states
  • a coordinate switching system comprising:
  • interconnecting means coupled to interconnect said conductors
  • each of said interconnecting means including a voltage controlled bidirectional resistor and a unidirectional device connected in series, and
  • said means for receiving and applying a voltage includes a register and switching means.
  • gating means for comparing said signals received by said switching means to enable determination of coincidence between the signals.

Landscapes

  • Push-Button Switches (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Description

Sept. 16, 1969 MYERS ELECTRICALLY CONTROLLED MATRIX 2 Sheets-Sheet 1 Filed March 8, 1966 ll'ln'ulll INVENTOR. 4.704.? Wynn.
Afraen/FY Sept 16, 196% o. MYERS 3,467,945
' ELECTRICALLY CONTROLLED MATRIX Filed March 8, 1966 2 SheetsSheet 2 United States Patent 3,467,945 ELECTRICALLY CONTROLLED MATRIX Oscar Myers, New York, N.Y., assignor to International Telephone and Telegraph Corporation, a corporation of Delaware Filed Mar. 8, 1966, Ser. No. 541,426 Int. Cl. H04q 1/18 US. Cl. 340-166 13 Claims ABSTRACT OF THE DISCLOSURE This invention relates to the control of switching systems comprising conductor matrices interconnected at crossing points and particularly to the control of such switching systems and matrices through the use of electrically controlled variable resistance devices interconnecting the crossing points. More particularly, the invention has application to electrically settable translator and storage matrices.
In the prior art, matrices have been used in translators and in radix converters, i.e. in devices for receiving intelligence encoded in one code, or in one radix, and transmitting it in another code, or to another radix, without changes in substance, except for the possible deletion of some information. Among the more successful of these prior art devices have been translators made of a matrix of conductors, certain of which have been connected together through diodes at points where they cross each other. The diodes have been biased selectively to conduct when signals of the proper polarity and amplitude are applied to them over receiving connections. Similar arrays of magnetic cores connecting input signals to se lected outputs have been used as information storage devices.
These prior art translating devices share a common limitation, i.e. they are all relatively inflexible in the sense that they can be made to vary their properties only by making mechanical changes in their connections. As an example of this inflexibility, in order to change the connections between one line and another, as determined by a diode, it has been necessary to remove the diode or replace it with another diode. Similarly, with cores used in a matrix to form a memory, if it is desired to alter the character of the memory device itself, either the nature, the position, or the number of cores must be altered.
It is a primary object, therefore, of the present invention to provide means for electrically changing connections between the cross-points of a matrix made up of electrical conductors.
It is a second object of this invention to provide a matrix of electrical conductors coupled at cross-points through couplings, the electrical characteristics of which may be varied by electric signals.
The foregoing objects and others ancilary thereto are accomplished according to preferred embodiments of this invention by use of translator or speech matrices composed of electrical conductors. In preferred examples, the conductors are coupled at their cross-points by con nectors having variable values of resistance. The variations in resistance of the resistors in turn are controlled by the application of certain setting potentials which are applied independently of any signals to be routed.
c CC
The novel features characteristic of this invention are set forth with particularity in the appended claims. The invention itself, however, both as to its organization and its method of operation, together with additional objects and advantages thereof, will best be understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:
FIG. 1 is a diagram of a matrix of conductors arranged in accordance with one aspect of the invention,
FIG. 2 is a diagram illustrating another embodiment of the invention, and
FIG. 3 is a block diagram illustrating yet another embodiment of the invention.
Turn now to FIG. 1 for a detailed showing of an embodiment of the invention. The horizontal conductors 1, 2 Nand vertical conductors a, b zcross each other to form arrays in a well known manner. At each crossing point such as are found at 1a, 1b, 2a, 2b, etc., a connection is made through a resistor Rla, Rlb, R2a, R2b, etc. and a corresponding diode Dla, Dlb, D2a, D2b, etc. Fixed biasing potentials may be applied as priming potentials on terminals 1, 2, 3 N, or on terminals a, b z, so that the application of additional potentials on selected ones of terminals a, b z or terminals 1, 2, 3 N, respectively, tends to prepare the way for conduction between corresponding horizontal wires 1, 2 N and output leads A, B Z.
Thus far, the description of the operation of the matrix of FIG. 1 is like that of a conventional matrix in which output signals may be supplied on the simultaneous occurrence of signals on a row of conductors and a column of conductors connected through diodes at selected crossings points. However, the circuit of FIG. 1 offers additional possibilities which have not been described previously, since it includes electrically settable variable resis tors. FIG. 1 embodies a third set of terminals at Tla, T2a, Tlb TNz upon which potentials may be applied to control the electrically settable variable resistors, which may be of the Pearson type (see Patent No. 3,117,013 to Northover and Pearson), at Rla, Rlb, RZa, R212, etc. These additional elements make it possible to introduce wholly new conditions and make possible much more flexible devices. For example, if the variable resistors are Pearson devices they can be made conductive or nonconductive in accordance with a third set of signals, which may represent a selective code. Thus, output signals will be controlled as a result of potentials applied to three sets of conductors, instead of by potentials applied to the usual two sets to determine which of the terminals A, B Z will be graced by output signals.
The embodiment of the invention shown in FIG. 1 may be used as a translator which can accept signals in one code, such as a binary code, and translate them to another code, such as the well known Gray code. The presence of the variable resistors makes possible the introduction of a third set of variables in the form of a third set of input signals so that the translator can be modified by elecrical means to translate different codes or to change from one radix conversion to another. This embodiment of the invention may be used to translate called signals, such as telephone numbers, from one form to another in order to route telephone calls in a desired way. It can also be used to control the path of any data supplied in the form of electrical signals in parallel or to extend the speech paths of a switching system.
The embodiment of the invention shown in FIG. 1 may also serve as a memory matrix with Pearson devices at Rla, Rlb, R2a1, etc. serving as memory elements. In this connection, the multistable character of Pearson devices is employed by switching the Pearson devices between high and low resistance stages by the application of voltage pulses on terminals Tl a, Tlb, T2a, T2b
3 4 etc. in excess of certain values. Since Pearson de- For purposes of illustration, simple blocks have been vices exhibit a symmetrical relationship, as indicated by employed to represent well known circuits which may be diagrams showing their current-voltage characteristics used in embodiments of the present invention. For ex- (see Patent 3,117,013), it is possible to drive them in opample, an electro-mechanical device has been shown to posite directions so that they function as bistable mem- 5 represent a stepping switch, and a simalar device might ory devices with different values of resistance depending be used as the scanning switch S, but it will be recogupon the polarity and magnitude of the most recent drivnized that an all-electronic circuit of conventional logic ing signal. In the embodiment of FIG. 1 it is clear, of circuits could be used to take advantage of the speed course, that the diodes Dla, Dlb etc. will tend to inherent in components such as are shown in FIG. 1 and prevent conduction in any but one direction. The use of FIG. 2. diodes for this purpose appears desirable in many cases It will be recognized from the foregoing that the variin order to reduce the requirements placed on the various embodiments of this invention may function as a able resistor devices Rla, Rlb etc. It will be apmemory, as a translator or as a matching translator. parent, however, that a matrix of conductors like that As a memory, a signal applied on a horizontal such as shown in FIG. 1 can function without diodes providing might be represented by terminals Tla, Tlb Tlz or only that quality control of the variable resistor devices by terminal 1 of FIG. 1, can be used to stimulate a readis held at a high level. out from any previously set verticals over terminals A, An embodiment of another aspect of the invention B Z, where the verticals may previously have been is shown in FIG. 2 where a matrix of conductors is conset over terminals a, b z. FIG. 2 shows an embodinected at crossover points through variable resistors Rla, merit of the invention which can also function as a mem- Rlb, R2a RNz and diodes Dla, Dlb, D2a ory device. If the equipment of FIG. 2 is used as amem- DNz. It is apparent immediately that FIG. 2 may be disory device, the variable resistors can be set to have a tinguished from FIG. 1 by the absence of a third set of certain memory by the register or by coincidence of signal sources as well as by the presence of a register M signals from the register and over terminals a, b, c z. and a scanning switch 8. The scanning switch and the The verticals can then be systematically scanned over register in combination may have a sufficient voltage apterminals A, B, C Z by the scanning switch S. plied betwee them and over successive crossing points to Considering the operation of embodiments of the incause predetermined ones of the Pearson devices Rla, vention as a translator, it may be noted that a register Rlb, R2a etc. to switch to a low resistance state. such as is shown at M in FIG. 2, set by say, binary or This capability can cause the matrix to be set so that it decimal information could select a single horizontal on can function either as a translator for signals which are the basis of the registered information, and then energize then supplied from the register or couse it to perform the verticals as in the case of the memory. the function of a simi-perrnanent storage or memory de As a matching translator, each horizontal may be previce. set to have an input combination (binary, decimal or any Once a particular group of resistors from among Rla, other form) and a corresponding output combination. To R112, RZa, etc. has been made conductive, or less resisstart a translation, the horizontals are energized one after tive, by actions of the register and the scanning switch, another by a scanning circuit, but only the verticals on the circuit of FIG. 2 can be used as a matching device to the input section are read and matched against the informatch memories or to function as a semi-permanent mation for which a translation is desired. When a match translator. When it functions as a matching device, a occurs, the output information on the matched horizontal readout from the scanning switch at a terminal 22 will is permitted to be read out. occur whenever a signal supplied by the register to a par- While the principles of the invention have been deticular horizontal, such as horizontal 3, coincides with a scribed above in connection with specific apparatus and low resistance in a resistor, such as R3a, R31), etc. and applications, it is to be understood that this description also coincides with a setting of the scanning switch to a is made only by way of example and not as a limitation particular vertical. on the scope of the invention.
The embodiments of the invention disclosed thus far What is claimed is: an e u d m effec ively n some Cases With t h lp 1. An electrically settable switching device comprisof additional components to perform various functions. ing: For p the embodiment ShOWn n F 2 a be a matrix composed of conductors crossing each other used as illustrated in the block diagram of FIG. 3 to form at a plurality of crosspoints, matching yp Store. In the memory 01 tra variable resistor means interconnecting each of said lating function of FIG. 2 (FIG. 1 would appear to funccrosspoints, tion equally well) is illustrated in block 352 with the versaid ariable re i to ea bei ttabl i reiicai lines terminating at B, Z eXtended to a sponse to the direct application of electrical potenstepping switch at 34. A register 36 is also connected tials, to high or low resistance states, and to the stepping switch 34 through corresponding termimeans connected to receive said potentials for setting nals A, B Z. A coded signal may be applied from each of said variable means to a desired state. a terminal 38 t0 the regisief- The pp g switch 34 can 2. An electrically settable switching device substantially then be caused to wipe corresponding terminals such as as lai ed in lai 1, in whi h; B and d a parison can be made of the resultunidirectional devices are connected in series with each ing signals in a coincidence circuit or an AND gate 40. of aid vari ble i t r means With this arrangement, an Output Signal Will be ppli 3. An electrically settable switching device substantially at a terminal 42 only when a signal received from 32 as claimed in claim 1, in which: ponds to that t r i the register each variable resistor means is connected by two sep- Besides providing for additional functions, an arrangearate t rminal t t crgsspoints, d mam such as that Shown in 3 Provides greater fiexsaid means to receive said potentials for setting each ibility and speed than is possible with circuits correspondof said variable means includes a third terminal ing to the diagrams of FIG. 1 0r FIG. 2 alone. The block coupled to each variable means. 32, for example, represents a complete translator or mem- 7 4. A coordinate switching system comprising: ory which may be set or reset independently of the stepa plurality of conductors crossing one another, ping switch 34 or the regist r 36. Thus t is P ss le t interconnecting means interconnecting said conductors, change the conductivity of various resistors represented id int ti means i l i a bidi i by block 32 without interfering with the operation of the variable resistor controlled to two different resistance remainder of the circuit. levels by the direct application of potentials, and
means connected to said bidirectional variable resistor to receive said potentials. 5. A coordinate switching system substantially as claimed in claim 4, in which:
said interconnecting means includes a unidirectional device in series with said bidirectional variable resistor. 6. A coordinate switching system substantially as claimed in claim 4, in which:
said means connected to said bidirectional variable resistor to receive said potentials constitutes a separate terminal, and said interconnecting means includes two additional terminals connecting to separate conductors. 7. A coordinate switching system comprising: a plurality of conductors arrayed in a matrix to cross one another at crossover points, interconnecting means for interconnecting said conductors betweeen terminals at said crossover points, said interconnecting means including bidirectional resistor devices responsive to the direct application of potentials to switch their degree of resistance between two states, and means connected to selectively receive potentials to activate selected ones of said bidirectional devices. 8. A coordinate switching system substantially as claimed in claim 7, in which:
said interconnecting means includes a unidirectional device in series with each of said bidirectional resistor devices. 9. A coordinate switching system substantially as claimed in claim 7, in which:
said means to selectively receive potentials to activate selected ones of said bidirectional resistor devices include terminals distinct from said terminals at said crossover points. 10. An electrically settable switching device comprising:
a plurality of crosspoints, variable resistor means interconnecting each of said crosspoints,
said variable resistor means being settable by the application of voltage to semi-permanent conductive or non-conductive states, and
means connected to receive voltages for setting each of said variable means to a desired state.
11. A coordinate switching system comprising:
a matrix composed of a plurality of conductors crossing one another,
interconnecting means coupled to interconnect said conductors,
each of said interconnecting means including a voltage controlled bidirectional resistor and a unidirectional device connected in series, and
means for receiving a voltage and applying it to said bidirectional resistor to control the bidirectional device.
12. A coordinate switching system substantially as claimed in claim 11, in which:
said means for receiving and applying a voltage includes a register and switching means.
13. A coordinate switching system substantially as claimed in claim 11, and including matching means for comparing signals received through said bidirectional resistor with signals from another source, said matching means including:
switching means for simultaneous reception of signals from said bidirectional resistor and said another source, and
gating means for comparing said signals received by said switching means to enable determination of coincidence between the signals.
References Cited UNITED STATES PATENTS 2,965,767 12/1960 Wanlass 340-176 XR 2,976,520 3/1961 Reenstra 340-176 3,107,345 10/1963 Gruodis 340-166 XR DONALD J. YUSKO, Primary Examiner
US541426A 1966-03-08 1966-03-08 Electrically controlled matrix Expired - Lifetime US3467945A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54142666A 1966-03-08 1966-03-08

Publications (1)

Publication Number Publication Date
US3467945A true US3467945A (en) 1969-09-16

Family

ID=24159551

Family Applications (1)

Application Number Title Priority Date Filing Date
US541426A Expired - Lifetime US3467945A (en) 1966-03-08 1966-03-08 Electrically controlled matrix

Country Status (3)

Country Link
US (1) US3467945A (en)
ES (1) ES337750A1 (en)
NL (1) NL6703612A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573757A (en) * 1968-11-04 1971-04-06 Energy Conversion Devices Inc Memory matrix having serially connected threshold and memory switch devices at each cross-over point
US3721838A (en) * 1970-12-21 1973-03-20 Ibm Repairable semiconductor circuit element and method of manufacture
DE2303409A1 (en) * 1972-04-18 1973-10-31 Ibm MONOLITHICALLY INTEGRATED STORAGE ARRANGEMENT
US5883827A (en) * 1996-08-26 1999-03-16 Micron Technology, Inc. Method and apparatus for reading/writing data in a memory system including programmable resistors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2965767A (en) * 1955-07-15 1960-12-20 Thompson Ramo Wooldridge Inc Input circuits and matrices employing zener diodes as voltage breakdown gating elements
US2976520A (en) * 1955-09-20 1961-03-21 Bell Telephone Labor Inc Matrix selecting network
US3107345A (en) * 1960-10-05 1963-10-15 Ibm Esaki diode memory with diode coupled readout

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2965767A (en) * 1955-07-15 1960-12-20 Thompson Ramo Wooldridge Inc Input circuits and matrices employing zener diodes as voltage breakdown gating elements
US2976520A (en) * 1955-09-20 1961-03-21 Bell Telephone Labor Inc Matrix selecting network
US3107345A (en) * 1960-10-05 1963-10-15 Ibm Esaki diode memory with diode coupled readout

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573757A (en) * 1968-11-04 1971-04-06 Energy Conversion Devices Inc Memory matrix having serially connected threshold and memory switch devices at each cross-over point
US3721838A (en) * 1970-12-21 1973-03-20 Ibm Repairable semiconductor circuit element and method of manufacture
DE2303409A1 (en) * 1972-04-18 1973-10-31 Ibm MONOLITHICALLY INTEGRATED STORAGE ARRANGEMENT
US5883827A (en) * 1996-08-26 1999-03-16 Micron Technology, Inc. Method and apparatus for reading/writing data in a memory system including programmable resistors

Also Published As

Publication number Publication date
ES337750A1 (en) 1968-03-01
NL6703612A (en) 1967-09-11

Similar Documents

Publication Publication Date Title
US3041469A (en) Translating circuit producing output only when input is between predetermined levels utilizing different breakdown diodes
US3145377A (en) Digital gray code to analog converter utilizing stage transfer characteristic-techniques
US4620188A (en) Multi-level logic circuit
US3387298A (en) Combined binary decoder-encoder employing tunnel diode pyramidorganized switching matrix
US2920317A (en) Code translators
US3107341A (en) Circuit arrangement for marking the points of intersection of a resistancediode matrix
US3179883A (en) Point matrix display unit for testing logic circuit
US3467945A (en) Electrically controlled matrix
US3456084A (en) Switching network employing latching type semiconductors
US3609661A (en) Matrix having mos cross-points controlled by mos multivibrators
US2959775A (en) Bi-directional diode translator
US2976520A (en) Matrix selecting network
US3213294A (en) Signal level discriminator circuit with zener diode interrogated by bipolar pulses and biased by ternary input
US3506810A (en) Digital controlled function generator including a plurality of diode segment generators connected in parallel
US2965887A (en) Multiple input diode scanner
US3135948A (en) Electronic memory driving
US3470535A (en) Electrically controlled matrix
US3119985A (en) Tunnel diode switch circuits for memories
US3508224A (en) Solid-state selection matrix for computer memory applications
US3873978A (en) Keyboard circuit
US3215782A (en) Switching systems employing co-ordinate switching arrangements of the cross-point type
US3392376A (en) Resistance type binary storage matrix
US3380038A (en) Electronic switching circuits
US3653033A (en) Non-linear decoder with linear and non-linear ladder attenuators
US3014211A (en) Digital-to-analog converter

Legal Events

Date Code Title Description
AS Assignment

Owner name: ITT CORPORATION

Free format text: CHANGE OF NAME;ASSIGNOR:INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION;REEL/FRAME:004389/0606

Effective date: 19831122