US3441857A - Method for determining transistor voltage capability by decay time evaluation - Google Patents

Description

Aprll 29, 1969 w VAHLE G TRANSISTOR VOLTAGE CAPABILITY TIME EVALUATION Filed April 5. 1967 BY DECAY METHOD FOR DETERMININ DlFFERENTlATQR 1 /Z VARIABLE D.C. SOURCE LOAD LINE INVENTOR BY Rona/a Z l/arln e. 2

A. OR/V r B A T C S O E E OMS T ll United States Patent US. 'Cl. 324-158 3 Claims ABSTRACT OF THE DISCLOSURE A transistor is rated for maximum applied voltage capability under predetermined current conditions by saturating and then cutting the transistor off at various increasing output voltage values determined by a variable clamp, monitoring transistor current decay time and rating the transistor at an output voltage which produces a predetermined percent decay time increase.

Brief summary of invention This invention relates to a method for nondestructively determining the applied voltage capability of a transistor as a. function of the increase in the output current decay time produced by saturating and open circuiting the transistor at gradually increasing values of output voltage.

A complete system for rating transistors in accordance with the present invention is described in the following specification with reference to the accompanying drawings of which:

FIGURE 1 is a schematic diagram of a circuit which may be used in carrying out the invention;

FIGURE 2 is a plot of collector current vs. output voltage for a transistor under test;

FIGURE 3 is a plot of output current vs. time for a transistor under first applied voltage conditions; and

FIGURE 4 is a plot of output current vs. time for the same transistor under output voltage conditions.

Referring to FIGURE 1 a junction transistor having collector, emitter and base electrodes is shown connected into a test circuit. Transistor 10 is a PNP type and is connected in a common emitter configuration. A series combination of fixed resistor 12, variable resistor 14, inductor 16 and DC source 18 is connected between the collector and emitter electrodes of transistor 10. The polarity of source 18 is arranged to produce a current flow from the emitter to the collector of transistor 10 when the transistor is conductive.

To render transistor 10 conductive, the negative terminal of source 18 is connected to the base electrode through the series combination of a mercury relay switch 20 and a resistor 22. In addition, a resistor 23 is connected between the base and emitter electrodes to produce a reverse bias on the transistor when switch 20 is opened by means of a relay coil 24.

Closing switch 20 forward biases transistor 10 into saturation to produce a current flow through resistor 12 and the series combination of resistor 14 and inductor 16. The inductor 16 establishes a substantially square load line as shown in FIGURE 2. The transistor output voltage V is, however, determined by a variable clamp circuit which is connected across the combination of resistor 14 and inductor 16. The clamp circuit includes the parallel combination of a resistor 26 and a variable DC source 28. This parallel combination is connected in series with a diode 30. By varying the source 28 from zero to 120 volts, for example, the maximum voltage drop across the collector and emitter electrodes of transistor 10 may be limited to any desired value within the range of 3,44'l ,85 Patented Apr. 29, 1 969 sources 18 and 28. This value may be determined by means of a voltmeter 32 which is connected between the cathode of diode 30 and the negative terminal of source 28.

It has been determined that the energy absorption capability of any transistor is dependent upon the relationship of the applied voltage to the avalanche voltage of the transistor with energy absorption capability decreasing as the applied voltage approaches the avalanche volt-age. Previous experience with a particular type of transistor may establish a nominal avalanche area as defined by line 40 in FIGURE 2. To ensure reliable operation it is desirable to maintain the operation of the transistor within the area to the left of line 40 as seen in FIGURE 2.

The avalanche region of any given transistor may vary from line 40, and a test which operates the transistor close to the nominal location of line 40 may destroy the transistor. It is, thus, desirable to determine the permissible range of transistor operation in a test which remains within this range. The transistor may be accurately rated for maximum recommended applied voltage without risking destruction in test.

Such a determination may be accomplished by connecting the transistor into the circuit shown in FIGURE 1. As previously mentioned the inductor 16 establishes a substantially square load line as shown in FIGURE 2. Knowing the approximate location of the avalanche area 40 and the saturated current of the transistor 10, the variable clamp circuit 26, 28, 30 may be set to a first low output voltage value. This is illustrated by the curve marked TEST A in FIGURE 2. By relatively low voltage it is meant that the V is well to the left of the nominal avalanche curve 40; for example, if nominal maximum voltage is 120 volts, the first test setting may be 40 volts.

So connected, the relay coil 24 is operated to close switch 20 driving transistor 10 into saturation. As switch 20 is opened, the transistor is cut off and the output current begins to decay as indicated in FIGURE 3. The current may decay from an initial value of 15 amperes, for example, to a minimum value in approximately microseconds. This value may be determined by means of a difi'erentiator circuit 34 which is connected across the sampling resistor 12 shown in FIGURE 1. The output of the diiferentiator may be in turn connected to a voltmeter 36 which, if desired, can be calibrated in terms of decay time. It will be appreciated that as the decay time of current across resistor 12 increases, the output of the ditr'erentiator circuit 34 decreases.

After recording the initial reading on voltmeter 36 the variable DC source 28 may be adjusted to increase the clamp voltage V across the transistor output. The new value of output voltage may, for example, correspond with that indicated by B in FIGURE 2. Switch 20 is again closed saturating transistor 10. The switch 20 is opened and the decay time of current through sampling resistor 12 is again monitored. It has been found that the decay time of a transistor when operated within the avalanche voltage limits is relatively constant; that is, it will vary within :10%. Therefore it may be expected that the decay time for TEST B will be approximately the same as that for TEST A. The consistency of readings A and B indicates that line 40 has not been approached and thus, the maximum rating of transistor 10 has not been established.

The above described operation is repeated with increasing increments of V as many times as are believed to be necessary. Finally, at TEST C in FIGURE 2 a voltage setting V is reached which is very near the avalanche curve 40. The current decay time of the transistor 10 under these operating conditions may increase to approximately 180 microseconds as shown in FIGURE 4. The 100% increase in decay time is an indication that the maximum transistor voltage has been approached and the operation in a voltage range which is higher than that established by TEST C may damage the transistor. Accordingly, for a reliable operation, transistor 10 should be rated at the voltage determined by TEST C.

The 100% increase figure has been found to be reliable for a particular type of transistor. However, it is to be understood that this figure may vary for different types of transistors and should be empirically preestablished for the particular type of transistor in question.

I claim:

1. A method for nondestructively determining the applied voltage capability of a transistor comprising the steps of inductively loading the output electrodes of the transistor to establish a substantially square load line at any given applied voltage, connecting a variable voltage clamp circuit across the inductive load to establish maximum transistor output voltage levels, setting the clamp circuit at a first low output level relative to the nominal capability of the transistor, saturating and open circuiting the transistor, measuring the decay time of the transistor output current, gradually increasing the output voltage levels by varying the clamp circuit voltage, saturating and open circuiting the transistor at each value, monitoring declay times of the transistor output currents and terminating the test when the decay time has increased a pre-established percent.

2. The method defined in claim 1 wherein the preestablished percent is 100.

3. A method for nondestructively determining the applied voltage capability of a transistor comprising the steps of connecting the series combination of a resistive impedance, an inductive impedance and a direct voltage source across the output electrodes of the transistor to establish a square load line, connecting a variable voltage clamp circuit across the inductive impedance to establish maximum transistor output voltage levels, setting the clamping circuit at a first low output level relative to the nominal capability of the transistor, saturating and open circuiting the transistor, measuring the decaly time of current through the resistive impedance, gradually increasing the output voltage levels by varying the clamp circuit voltage, saturating and open circuiting the transistor at each value, monitoring decay times of current through the resistive impedance and terminating the test when the decay time has increased approximately 100% over the first value.

References Cited Electronic Engineering (Cooper), July 1958, pp. 440, 441.

Semiconductor Products (Paterson), vol. 2, #10, October 1959, pp. 35-36.

RUDOLPH V. ROLINEC, Primary Examiner.

E. L. STOLARUN, Assistant Examiner.

U.S. Cl. X.R. 32457

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