US3408582A

US3408582A - Wide dynamic range square-law detector with logarithmic read-out

Info

Publication number: US3408582A
Application number: US558091A
Authority: US
Inventors: Jr Ralph H Britton
Original assignee: ALFRED ELECTRONICS
Current assignee: ALFRED ELECTRONICS
Priority date: 1966-06-16
Filing date: 1966-06-16
Publication date: 1968-10-29
Anticipated expiration: 1985-10-29

Description

R. H. BRITTON, JR 3,4 8,582 WIDE DYNAMIC RANGE SQUARE LAW DETECTOR WITH LOGARITHMIC READ-OUT Filed June 16, 1966 Oct. 29, 19 68 /0 ,I3 /5 LOGARITHMIC STEPPED DETECTOR GAIN GAIN +9 INPuT AMPLIFIER AMPLIFIER OUTPUT TERMINAL TERMINAL Fig-1 PRoM LOGARITHMIC AMPLIFIER 2; I P E? 2 J a; 2 53 ii I: Q I E E" I I -I s I 005 I I l VOLTS voLTs o b c o O a b c LOG [RF VOLTAGE] 3 L06 [RF VOLTAGE voLTs VOLTS 7. 75 70 5 2A -73 (9 w 72 74 o"- 8 E A- 7/ I I Fl g- 5 I: I I I ,IL 33 a I I I I g a: E I I I 5 I I I I- VOLTS E 0 G S t b C 2,: LOG [RF VOLTAGE] %;5 INVENTOR.

A PH H. BRITTON JR 8 fi' v0LTS R L I 1 b c BY LOG [RF VOLTAGE] I m L L A TTORNE Y United States Patent Ofice 3,408,582 WIDE DYNAMIC RANGE SQUARE-LAW DETEC- TOR WITH LOGARITHMIC READ-OUT Ralph H. Britton, Jr., Palo Alto, Caliii, assignor to Alfred Electronics, Palo Alto, Calif., a corporation of California Filed June 16, 1966, Ser. No. 558,091 Claims. (Cl. 329-192) from square-law to linear.

This non-linearity of the crystal detector characteristic has given rise to a number of problems when it is desired reliability, due to its complexity, left something to be desired.

It is therefore a primary object of this invention to provide a detection system capable of providing significant values of the detected range of a crystal detector.

It is a further object of this invention to provide a square-law detection system which has a logarithmic read-out over a dynamic range which is wider than was possible heretofore.

It is still another actenstic, as seen at the output, range of a crystal detector, that is, a range extending from small signals up to the reverse crystal diode breakdown voltage.

It is still another object of this invention to provide a 3,408,582 Patented Oct. 29, 1968 Will become apparent to those skilled in the art to which the invention pertains as the ensuing description proceeds.

The features of novelty that are tic of this invention are set forth with particularity in with the accompanying drawings in which:

FIGURE 1 is a schematic block diagram of the wide dynamic square-law detector with logarithmic read-out of this invention;

FIGURE 2 is a schematic diagram, partially in block form and partially in circuit form, of one embodiment of the step gain amplifier illustrated in FIGURE 1;

FIGURE 3 is a typical graph of the detected voltage a graph of the amplification versus of voltage characteristic of the stepped gain amplifier FIGURE 2; and FIGURE 6 is voltage versus this invention.

Referring now to FIGURE 1 of the drawing, the detection system thereshown a graph of the RF voltage of logarithm of the detected the detector system of output terminal 16.

Detector means 10 may wellknown crystal diodes 3 Stepped gain amplifier means is an amplifier whose amplification increases step-wise with increase in the amplitude of the applied signal on lead 14 from an amplification of A to an amplification of 2A. Referring now to FIGURE 2, there is shown one embodiment of step-wise variable gain amplifier means 15. Amplifier means 15, as thereshown, comprises a differential, highgain amplifier having one of its input terminals connected to lead 14 to receive the output signal from logarithmic amplifier means 13. There is also provided a feedback network, generaly designated by reference character 21, between the output lead of amplifier 20 and the other of its input terminal. Feedback network 21 includes a voltage divider, formed by resistors 22 and 23, which determines the amount of feedback signal which is fed back network, generaly designated by reference characback to amplifier 20 and, thereby, the amplification of stepped gain amplifier means 15 for small signals applied to input lead 14. This amplification will be arbitrarily designated as A.

Feedback circuit 21 is also provided with means for step-wise increasing the feedback signal with preselected increases in the amplitude of the amplifier output signal and thereby the feedback signal and amplification. More particularly, a plurality of resistive branch arms are connected in parallel to feedback circuit 21 through individual switches. FIGURE 2 illustrates four branch arms connected to feedback circuit 21 through diodes 24, 25, back biased to operate as voltage diodes are connected respectively, through resistors 28, 29, and 31 to a voltage divider network formed by the series connected

resistors

32, 33, 34, 35 and 36. This voltage divider has a pair of

terminals

37 and 38 which are respectively connected to the negative and positive output terminal of a source of reference voltage for back biasing the diodes.

Resistors 28 to 36 are selected in such a manner that switch diodes 24 to 27 are normally back biased when the voltage across resistor 22 is small and become forward biased when the voltage across resistor 22 is large. Further, the resistive values of the various resistors are selected so that when the feedback voltage is large, the amplification of stepped gain amplifier means becomes 24 or twice the amplification for the small feedback voltage. Still further, the resistive values of the various resistors is selected so that the first step-wise increase of amplification occurs when the signal applied to amplifier means 15 has an amplitude corresponding to a detected signal at the very beginning of the transition region of the crystal diode, and that the last step-wise increase occurs when the signal applied to amplifier means 15 has an amplitude corresponding to a detected signal at the very end of the transition region. The intermediate step-wise increases in the amplification are selected to provide a smooth transition as will become better understood in connection with the description of the operation of this invention.

The operation of the detector system of this invention is best understood by reference to FIGURES 3-6. FIG- URE 3 depicts a curve 50 which is thetypical detected voltage versus RF voltage (voltage-current) characteristic of a crystal detector, such as, for example, detector means 10. Curve 50 is typical in that it shows that for small signals the rectified output voltage increases rapidly with increase of RF voltage as shown by portion 51, then less rapidly for intermediate signals as shown by portion 52, and then even less rapidly for large signals as shown by portion 53. Portion 51 shows the rectified output voltage as proportional to the square of the RF input voltage, portion 53 shows the rectified output voltage as directly proportional to the RF input voltage, and portion 52 is the transition region through which the rectified output voltage changes from being proportional to the square of the RF input voltage to being proportional directly to the RF input voltage. Portion 51 is known as the squarelaw region, portion 52 is known as the transition region, and portion 53 is known as the linear region.

While crystal rectifiers differ in their characteristic with the type of crystal used, and to a smaller extent from crystal to crystal, the square-law region usually ranges from a rectified output voltage between Zero and 50 millivolts, the transition region extends usually from a rectified output voltage between 50 millivolts and 1 volt and the linear region extends from a rectified output voltage of 1 volt to the remainder of the useful range of the crystal rectifier as determined by the reverse breakdown voltage and/or the burn-out current which is typically 3 volts, but may be as high as 6 volts for certain crystals,

Accordingly, if rectified output voltage is y and the RF voltage is x, the following equations describe the crystal diode:

y K c when 0 x X, y=f( when 1 z y=K x when X x where X is the square-law region limit and X is the linear region limit. Taking the logarithms of these equations shows the existence of two linear regions, one below X and the other above X having a slope differing by a factor of two.

The effect of passing the rectified voltage through logarithmic gain amplifier means 13 is shown by curve 60 of FIGURE 4 which is also the graphical presentation of the equations. The logarithm of the rectified output voltage for RF voltages between 0 and A is linear and depicted by portion 61 of curve 60. The logarithm for the rectified output voltage for RF voltage between b and c is also linear as depicted by portion 63 of curve 60 but has a slope which is only one-half of the slope of portion 61. Portion 62 of curve 60 depicts the transition region which is non-linear and along which the slope decreases by a factor of 2 as the RF voltage changes from a to 12.

Referring now to FIGURE 5, there is shown a curve 70 which depicts the amplification of stepped gain amplifier means 15 as a function of the applied RF input voltage (suitably scaled). Curve 70 has the number of steps which are designated by reference characters 71 through 75. Amplifier means 15 is constructed so that for a rectified input voltage corresponding to an RF voltage up to a volts the amplification is equal to A as shown by step 71. Furthermore, when applied rectified input voltage corresponds to an RF voltage in excess of b volts, amplifier means 15 provides an amplification equal to 2A as shown by step 75. In the transition region between a and b volts of the applied RF voltage, amplifier means 15 provides a number of intermediate steps of amplification as shown by steps 72, 73 and 74 corresponding, respectively, to an RF voltage range in volts extending from a to s, s to t and tto b.

When the signal shown by curve 60 of FIGURE 4 is passed through stepped amplifier means 15 and thereby subjected to the different amplifications as shown by curve 70 of FIGURE 5, an output signal corresponding to curve of FIGURE 6 is obtained which represents a graph of the rectified output voltage of the system of FIGURE 1 versus the applied RF input voltage. More particularly, the signal corresponding to portion 61 of curve 60 is subjected to an amplification A and the signal corresponding to portion 63 of curve 60 is subjected to an amplification of 2A whereby its slope is increased by a factor of 2. This is shown by portions 81 and of curve 80. The portions of curve 60 corresponding to rectified signals of RF input voltages between a and s, s and t, and t and b, are amplified in steps as shown by portions 72, 73 and 74 to provide an amplified output signal corresponding to

portions

82, 83 and 84 of curve 80. In this manner the transition portion is linearized in steps to form a straight line with portions 81 and 85.

Referring now to the operation of amplifier means 15 shown in FIGURE 2, amplification A is obtained through the proper selection of resistors 22 and 23 with switches to 36 are selected such that the stepwise increasing amplification corresponds to

steps

72, 73, 74 and 75 of curve 70.

Even though amplifier means branch arms.

There has been described a wide dynamic range squarelaw detector with logarithmic read-out which provides a linear output While the above detailed description has shown, described and pointed out the fundamental novel features of the invention as applied to various embodiments, it will be understood that various omissions and substitutions and changes in the form and details of the device 1. A detector system for recovering a signal modulated upon a carrier, comprising in combination:

crystal detector means to which the modulated carrier is applied and which provides a detected signal, said region for intermediate amplitude detected signals;

a logarithmic gain amplifier responsive to said detected signal and operative to provide a first signal, said logarithmic gain amplifier having gain which varies as the logarithm of the amplitude of said detected signal; and

variable gain amplifier rneans responsive to said first signal and operative to provide a second signal, said variable gain amplifier means having a gain which varies with the amplitude of said first signal.

2. A detector system in accordance with claim 1 in said first gain for all first signals corresponding to small amplitude detected signals, and said second gain for all first signals corresponding to large amplitude detected signals.

increases with the signal corresponding to intermediate signals.

6. A detector system in accordance WlllCh the gam variation of said variable gain amplifier to small amplitude detected signals and in which the number of stepwise increases exceeds three steps.

8. A detector system for recovering a signal modulated upon a carrier, comprising in combination:

crystal detector means responsive to the modulated carstepped gain amplifier means responsive to said amplified signal and which corresponds to an intermediate amplitude sig nal.

signal and increasing stepwise from a minimum gain to a maximum gain of 2A with an increase in the amplitude of said amplified signal from a signal corresponding to the square-law detection region to a signal corresponding to the linear detection region of said crystal detector.

10. A detector system in accordance with claim 9 in which the gain of said stepped gain amplifier remains constant at a gain A for all amplified signals developed with the square-law detection region and remains constant at a gain 2A for all amplified signals developed with the linear detection region, and stepwise increases in at least three steps from a gain equal to A to a gain equal to 2A with increase of the amplitude of said amplified signal developed with the transition region.

8 References Cited UNITED STATES PATENTS 3,061,789 10/ 1962 Mace 3,092,779 6/ 1963 DeNiet 3,241,079 3/1966 Snell 3,373,294 3/ 1968 Fujinami ALFRED L. BRODY, Primary Examiner.

329-192 X 328-145 X 328-444 X 328-445 X

Claims

1. A DETECTOR SYSTEM FOR RECOVERING A SIGNAL MODULATED UPON A CARRIER, COMPRISING IN COMBINATION: CRYSTAL DETECTOR MEANS TO WHICH THE MODULATED CARRIER IS APPLIED AND WHICH PROVIDES A DETECTED SIGNAL, SAID CRYSTAL DETECTOR MEANS HAVING A SQUARE-LAW REGION FOR SMALL AMPLITUDE DETECTED SIGNALS, A LINEAR REGION FOR LARGE AMPLITUDE DETECTED SIGNALS AND A TRANSITION REGION FOR INTERMEDIATE AMPLITUDE DETECTED SIGNALS; A LOGARITHMIC GAIN AMPLITUDE RESPONSIVE TO SAID DETECTED SIGNAL AND OPERATIVE TO PROVIDE A FIRST SIGNAL, SAID LOGARITHMIC GAIN AMPLIFIER HAVING GAIN WHICH VARIES AS THE LOGARITHM OF THE AMPLITUDE OF SAID DETECTED SIGNAL; AND VARIABLE GAIN AMPLIFIER MEANS RESPONSIVE TO SAID FIRST SIGNAL AND OPERATIVE TO PROVIDE A SECOND SIGNAL, SAID VARIABLE GAIN AMPLIFIER MEANS HAVING A GAIN WHICH VARIES WITH THE AMPLITUDE OF SAID FIRST SIGNAL.