US3406381A

US3406381A - Print hammer energizing arrangement

Info

Publication number: US3406381A
Application number: US548720A
Authority: US
Inventors: Robert C Peyton
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1966-05-09
Filing date: 1966-05-09
Publication date: 1968-10-15
Anticipated expiration: 1985-10-15

Description

2 Sheets-Sheet l R. C. PEYTON Oct. 15, 1968 -PRINT HAMMER ENERGIZING ARRANGEMBNT Filed May 9, 1966 COMPU T52 Oct. 15, 1968 R. c. PEYTON PRINT HAMMER ENERGIZING ARRANGEMENT 2 Sheets-Sheet 2 Filed May 9. 1966 Sc 332mm E United States Patent O 3,406,381 PRINT HAMMER ENERGIZING ARRANGEMENT Robert C. Peyton, North Palm Beach, Fla., assignor to Radio Corporation of America, a corporation of Delaware Filed May 9, 1966, Ser. No. 548,720 20 Claims. (Cl. S40-172.5)

This invention relates generally to a logic arrangement for setting selected ones of a series of bistable devices in sequence, and for resetting the set devices in the same time sequence after a predetermined period of time. In particular, this invention relates to an improved logic arrangement for selectively actuating the print hammers in a serial printer.

The duration of the energizing pulse applied to a print hammer solenoid must be carefully controlled in order to produce proper printing at high speed. In a parallel printer, all like characters in a `print line are printed concurrently. The selected print hammers may be actuated by individual gates or individual ip-ops. When gates are employed, there usually is no problem in supplying pulses of uniform duration to the selected solenoids since a gating pulse of the proper duration may be applied to all of the gates concurrently. The same is true in the case of flip-Hops, since the flip-hops for the selected solenoids may be set concurrently and then reset concurrently after a given period of time.

In a serial printer, on the other hand, successive selected print hammers are red in sequence. Thus, a common gating pulse cannot be used to assure uniformity of pulse duration. One approach to the problem is to employ a separate one-shot or monostable multivibrator for each hammer solenoid. In that event, however, extremely close tolerances must be maintained in the several oneshots, and even then frequent readjustment of the oneshots may be necessary.

Accordingly, it is one object of this invention to provide an improved arrangement for controlling the operation of the printing transducers.

It is another object of this invention to provide a printing transducer control arrangement which includes a separate bistable device for each transducer, and circuitry for resetting each bistable device a given time after it becomes set.

It is still another object of this invention to provide an arrangement, of the type immediately aforementioned, for a system in which a bistable device, once set, must remain set for a duration which is greater than the shortest time it takes to print an entire line of characters.

In more general terms, it is an object of this invention to provi-de an arrangement for setting selected ones of a plurality of bistable devices in succession, in a given time sequence, and for resetting the devices in succession, in the same time sequence, after a predetermined period of time.

Apparatus embodying the invention includes N bistable circuits, and first and second counters each capable of counting to N. Each count designates a different one of the bistable circuits. A first series of pulses is applied to the tirst counter and a second series of pulses, later in time, is applied to the second counter. In response to an applied input signal, a signal is applied at the set input of that one of the bistable circuits designated by the count in the tirst counter. Signals are applied at the reset inputs of the bistable circuits under control of the second counter.

In one embodiment, the reset signals are applied unconditionally to the bistable circuits in ordered sequence. In another embodiment, reset signals are applied only to those bistable circuits which were set earlier, and in the same sequence in which they were set.

3,406,381 Patented Oct. 15, 1968 ICC In the accompanying drawing:

FIGURE 1 is a block diagram of a printer system in which the invention may be practiced;

FIGURE 2 is a block diagram of control logic embodying the invention;

FIGURE 3 is a block diagram of a modified resetting arrangement for use in the control logic;

FIGURE 4 is a block diagram of one form of input control for the modified resetting arrangement;

FIGURE 5 is a diagram of a second form of input control for the modified resetting arrangement; and

FIGURE 6 is a timing pulse generator output timing diagram.

In the illustrative printer system of FIGURE l, a print drum or cylinder 10 is mounted on a shaft 12 and rotated by a drive means 14, c g., a synchronous motor or a motor with speed maintained within tight tolerance. Drum 10 has a large plurality of raised type characters thereon arranged in M rows and N columns. All of the type characters of a column are arranged in spaced relation in a peripheral ring on the drum normal to the axis 12. In general, all of the M characters in a column are different. The N type characters in a row are identical, and are equally spaced along the row to provide columns of equal width. As may be seen in FIGURE, l, the rows of type characters are skewed relative to the print columns and to the axis 12. Each of the rows is identically skewed, and the distance between adjacent rows is a constant. The angle of skew and the distance between adjacent rows is chosen so that the type characters of a row are presented to a row of printing transducers in sequence, beginning with the type character in column 1 and ending with the type character in column N, and with the type character in column N being presented to its transducer before the type character in column 1 of the next row is presented to its transducer.

Transducer assembly 18 includes N printing transducers, e.g., print hammers and associated solenoids, there being one hammer for each column of type characters. The hammers (not shown) are aligned in a row parallel to the axis 12 of the drum and disposed opposite their respective columns of type characters. In the deenergized state of the hammer solenoids, the hammers are spaced a slight distance from the drum l0 to define an area for receiving a recording medium to be printed.

Information or data in the form of binary characters corresponding to the characters to be printed on a line of the recording medium are stored in a data store or memory 20, and may be supplied to the memory from a computer 22 or other source. By way of example only, data store 20 may take the form of a bank of shift registers of N stages each, there being one shift register for each bit of a character. The shift registers may be connected as a recirculating memory by connecting the outputs of the several banks of shift registers to the inputs thereof by way of gates 24, there being one gate for each shift register. The outputs of the gates 24 and the data input from the computer 22 may be supplied to the inputs of the shift registers through OR gates (not shown).

Mounted on the axis 12 of the print drum, at the right end thereof, is a timing disk 28 which may take the form of an opaque disk having transparent areas or slots therein arranged in a ring concentric with the axis. There is one slot for each row of type characters on the drum 10. A light source 30 is located on one side of the disk adjacent the ring of slots, and a photo-pickup device 32 is located on the opposite side of the disk. As the axis 12 turns, the various slots pass sequentially between the light source 30 and the pickup device 32 to generate a sequence of pulses, there being one pulse for each row of type on the drum. The slots are so located on the disk 28 that the slot for any row of characters on the drum passes between the light source and the photo-pickup device as the type character in the first column (column 1) of that row is moving into printing position opposite its respective printing transducer.

The output of the photo-pickup device 32 is applied to the input of a counter 36. The output of the counter is the binary character equivalent of the type character then in printing position. This output may be considered to be a Search character, since it is desired to search for that binary character in the memory 20. The output of counter 36 is applied to a comparator 38. Alternatively, a coded disk could be employed to supply binary characters directly to the comparator 38 without the need for counter 36. The characters in the data store 20 are supplied to the comparator 38 charactdn-by-character for comparison with the output of counter 36. For each identity, comparator 38 sends an input signal to the block 40 labeled control and timing logic. This unit 40 also receives each output of the photo-pickup device 32.

In genera-l terms, the printer system may operate as follows. Computer 22 sends to the memory 20 a series of binary characters corresponding to the characters which it is desired to print on a line of the recording medium. The computer 22 also may send a signal to the advance (A) input of the memory with each character to step the information along in the shift registers. When the memory is filled and the recording medium has been shifted to the proper position, etc., the memory sends a signal to the control and timing logic on line 42 to signify that printing may begin.

As the next timing signal is generated by the disk 28 (at the beginning of a row of type characters), the control and timing logic supplies a series of pulses to the advance terminal of the memory 20 to read out the memory a character at a time to the comparator. Gates 24 in the recirculation loop are open at this time to allow the contents of the memory to recirculate. The pulses applied to the advance terminal of the memory are equally spaced timewise, so that the successive characters applied to the comparator occur in successive equal time periods. Drum l rotates at such a speed that the successive type characters of a row are presented to their respective transducers during successive ones of the time periods.

As mentioned previously, the comparator 3B sends an input signal to the control logic 40 each time the memory output corresponds to the output of the counter 36. It is the function of the control and timing logic to energize the appropriate hammer solenoid in response to an output from the comparator and to thereafter de-energize that solenoid after a fixed time period. In addition, after the entire line of characters has been printed on the recording medium, the control and timing logic signals the computer 22 via line 44 that the system is ready to receive information for the next print line. Also, the control and timing logic disables the gates 24 in the recirculation loop at the end of a line of printing to prevent the memory contents from recirculating `as the next line of information is being sent from the computer 22 to the memory 20.

Inasmuch as the rows of type on drum are skewed, the same character is presented to the hammers in columns l-N in sequence. Consequently, the control logic 40 must supply energizing signals to the solenoids of selected hammers in the proper sequence timewise. The durations of these energizing signals, as mentioned previously, must be carefully controlled. In some systems, the required duration of an energizing signal is longer than the time between the arrival of successive type characters at a printing location. In that event, if the solenoids are controlled by bistable circuits, reset pulses must not be applied unconditionally to the circuits, but must be applied only to the circuits which were previously switched to the set state. Otherwise, the reset pulses applied following the printing of a given row of type would reset the bistable circuits which were set to effect printing with the next row of type characters.

FIGURE 2 is a block diagram of a control and logic network 40 embodying the invention which may be used in a system of the type mentioned immediately hereinabove. This network comprises N bistable circuits 50-1, SO-Z-Sf-N, which may be flip-flops, each having a SET input, a RESET input, and corresponding (1) and (0) outputs. The (1) outputs of the several iiip-liops 50-1- SI1-N are coupled via amplifiers 52-1-52-N to the solenoids 54-1-54-N, respectively, for the hammers associated with columns l-N, respectively, of print drum 10.

A first counter 60 controls the selective setting of these Hip-flops via a first logic arrangement 56, and second counter 62 controls the selective resetting of set flip-Hops via a second logic arrangement 58. The counters which are capable of counting at least to N, may be ring counters, binary counters, etc. When the counters are ring counters, the outputs of first counter 60 which are energized sequentially for counts of l-N are applied through coincidence gates 66-1-66-N, respectively, to the set inputs of tiip-ops 50-1-50-N, respectively, as illustrated. A second input to each of the gates is connected to a line 68. When this line is energized, that one of the ip-ops designated by the count in first counter 60 is switched to the set state.

ln a like manner, the outputs of second counter 62 which are energized for stored counts of l-N are applied through coincidence gates 70-1-70-N, respectively, to the reset inputs of hips-flops 50-1-50-N, respectively. When the second input of each of these gates is energized via line 72, that one of the hip-hops designated by the count stored in second counter 62 receives a signal at its reset input.

It will be understood that other types of counters could be employed with suitable change in logic. For example, binary counters could be used, with decoders at the outputs thereof. Each

counter

60, 62 is initially cleared to a reference state, e.g., a count of zero, when power is first turned on in the system.

A timing pulse generator 78, such as a crystal controlled oscillator and supporting circuitry, generates continuous, successive sets or sequences of timing pulses, wherein each sequence has four timing pulses TPA, TPB, TPC and TPD, The timing relationship of successive sequences and individual timing pulses is illustrated in the diagram of FIGURE 6. As shown there, the timing period for each set of timing pulses is T. Since each of the several pulses of a set occurs only once each timing period, the frequency of the pulses TPA (or TPB, etc.) is f: l/ T.

Drum 10 is rotated at such a speed that each type character in a row is in printing position for a period T. Thus, a first set of timing pulses TPA-TPD is generated as the type character in column l of a drum row passes through printing position, a second set of timing pulses is generated as the type character in column 2 of that row passes through printing position, etc. As will be described, one pulse of each timing pulse set is used to advance the memory 20, one pulse of a set is used to advance or trigger the

counters

60, 62, etc., whereby synchronism is maintained throughout the system.

Computer 22 (FIGURE l) sends a signal to the control unit when data store 20 has been filled, etc., to signify that printing can begin. This signal sets a START flip-Hop to energize the 1) output thereof. This output opens the gates 24 in the recirculation loop of data store 20, and also primes one input of a first coincidence gate 84 and one input of a second coincidence gate 86. A start signal (output of photodetector 32, FIGURE 1) primes a second input to first gate 84 during the time period T next prior to the timing period when a type character in column 1 of the drum is in printing position. At TPD, first gate 84 becomes fully enabled and sets a SET iiipflop 88. The output of gate 84 also is applied through an OR gate 90 to the input of a delay means 92, which may be, for example, a magnetostrictive delay line.

When SET flip-flop 88 is in the set condition, its (1) output primes an input of a third coincidence gate 96 and allows the TPA pulses to be applied to the ADVANCE input terminal of first counter 60, Since only one TPA pulse is generated during each timing period, and since the first TPA pulse applied to the counter 60 occurs during the period when a type character in column 1 of the drum is in printing position, it may be seen that the count in counter 60 always corresponds to the hammer associated with the drum column whose type character is in printing position during a printing operation.

The binary character designating the character to be printed in column 1 is presented by the data store 20 (FIGURE 1) to the comparator 38 when a type character in column l of the drum is in printing position opposite its transducer. If that type character corresponds to the binary character, the output of counter 36 will match the output of the data store 20, and the comparator 38 will send a signal to the second coincidence gate 86 (FIG- URE 2). At TPB of the first timing period, gate 86 then will become fully enabled. The output pulse thereof is passed through OR gate 90 to the delay means 92, and also sets a PRINT Hip-flop 98. The (l) output thereof primes one input of each of the coincidence gates in first logic arrangement S6. Since counter 60 is storing a count of l at this time, gate 66-1 becomes fully enabled and sets iiip-fiop 50-1 to energize the solenoid 54-1 for the hammer associated with the first column of the drum.

The following TPC pulse (of the same pulse set) resets PRINT flip-flop 98. This TPC pulse also is applied to an input of a fourth coincidence gate 100. During a line of printing, the second input of gate 100 remains primed by the (l) output of SET flip-flop 88. Therefore, the TPC pulse passes through gate 100 and advances the data in the memory 20. The memory is advanced during each timing period by a TPC pulse, whereby the output of the memory 20 always is a binary character designating the character to be printed in the column whose type character is in printing position.

At the end of the TPC pulse of the Nth set of timing pulses, measured from the time SET flip-flop 88 became set, the entire contents of the data store 20 has been read out to the comparator 38 (FIGURE l) and recirculated. Also, first counter 60 stores a count of N. The output of counter 60 then primes one input of a fifth coincidence gate 104, which becomes fully enabled at TPD to clear the counter 60 to a count of zero, to reset the SET flipflop 88 and to trigger a counter 106. When fiip-flop 38 resets, gates 96 and 100 are disabled, and no further pulses are applied to the first counter 60 or the memory 20 advance input.

The system now is ready to begin printing in selected columns of the print line when the type characters in the next row of the drum are presented to their respective transducers. As the type character in the first column of that next row approaches print position, photo-detector 32 (FIGURE 1) triggers counter 36 to supply a new search character corresponding to the new row of type, and also supplies a START input to the first coincidence gate 84 to begin the second print cycle. At the end of this print cycle, which is similar to the first print cycle, counter 106 is triggered to a count of two. At the end of the M*h print cycle (assuming M rows of type characters on drum 10), counter 106 reaches a count of M. Its output then resets the START flip-flop 80 to terminate the printing operation. In particular, the (0) output signals the computer 22 that the entire line of data has been printed; the (1) output blocks the first and

second coincidence gates

84 and 86 and the gates 24 (FIGURE 1) in the recirculation loop.

The logic for resetting the flip-flops 50-1-50-N is similar generally to that for setting the flip-flops and, therefore, will be discussed only in connection with the resetting operation. Let it be assumed that the START flip-flop has just been switched to the set state, and that a type character in column 1 of drum 10 is moving into printing position. At TPD, first coincidence gate 84 sets the SET flip-hop 88 and applies a pulse through OR gate 90 to the delay means. The first counter 60 then begins counting TPA pulses immediately, but second counter 62 does not.

After a predetermined delay, the START pulse emerges at the output of the delay means 92 and is applied at one input of a sixth coincidence gate and one input of a seventh coincidence gate 122. Let it be assumed that the delay provided by delay means 92 is an integral number of timing periods. In that event, the delayed start pulse emerges at the output end of the delay means 92 coincident with the generation of a TPD pulse by generator 78. In that event, also, the TPD pulse are chosen for application to the sixth coincidence gate 120. RESET flip-flop 124 then becomes set and its (1) output primes an input to an eighth coincidence gate 126 to allow the TPA pulses to be applied to the RESET counter 62.

It is thus seen that the first TPA pulse applied to second counter 62 commences at a time D after the application of the first TPA pulse to first counter 60, where D is the delay provided by the delay means 92. For ease of illustration only, let it be assumed that the delay D is equal to two time periods. Let it also be assumed that the output of the data store 20 (FIGURE l) matches the output of counter 36 during the third and Nth timing periods.

The TPA pulse of the third timing period advances first counter 60 to a count of three and advances second counter 62 to a count of one. At TPB of the third timing period, second coincidence gate 86 produces an output pulse which sets PRINT flip-flop v98. The (1) output thereof fully enables gate 66-3 to set the hammer ipflop 50-3. The pulse output of second coincidence gate 86 also is applied through OR gate 90 to the delay means 92. This delayed pulse emerges at the output of delay means 92 two timing periods later, i.e., coincident with the TPB pulse of the fifth timing period. Seventh coincidence gate 122 then is fully enabled and sets a flip-flop 130. First counter 60 stores a count of five at this time, but second counter 62 is storing a count of three. Therefore gate 70-3 becomes fully enabled, and the output thereof resets the third hammer flip-flop 50-3. At TPC, flip-flop 130 becomes reset.

The TPB pulse of the Nth timing period fully enables second coincidence gate 86 to set the PRINT flip-flop 98. First counter 60 then is storing a count of N, and second counter 62 is storing a count of N-2. Gate 66-N becomes fully enabled to set the Nth hammer flip-Hop SO-N. At TPC, the PRINT flip-flop 98 becomes reset. Two timing periods later, the delayed output of second coincidence gate 86 emerges at the output of the delay means 92 and sets flip-flop 130 via seventh coincidence gate 122. Second counter 62 now is storing a count of N. Consequently, gate 70-N becomes fully enabled and resets the Nth hammer Hip-flop 50-N.

The Nth output of second counter 62 also enables one input of a ninth coincidence gate 132. The next TPD pulse fully enables this gate to reset the RESET flip-flop 124 and to clear the second counter 62 to a reference count, e.g., zero. No further advancing of second counter 62 takes place until the next delayed start pulse sets RESET tlipop 62.

In the example given, the delay D was chosen to be an integral number of timing periods. This should not be construed to be a limitation of the invention. For other than an integral number of timing period delays, it is only necessary to properly select the particular timing pulses that are applied to the

gates

120, 122, 126, 132 and the liip-op 130.

It should be noted that second counter 62 applies reset pulses through second logic 58 only to those hammer flipflops that were previously set by rst counter 60. This fact is of great importance in those systems wherein the duration of a signal applied to a hammer solenoid must be greater than a print cycle, i.e., greater than N timing periods. For example, the required solenoid energization period may be so long that a solenoid, energized during the printing of one row of drum 10 characters, must remain energized until after selective printing of the next row of drum characters commences, and may even be longer. In that event, reset pulses cannot be applied to all hammer flip-flops indiscriminately without interfering with the printing operation. In the present system, reset pulses are applied only to those hammer flip-flops which were set previously. Thus, the solenoid energization period, determined by delay means 92, can be chosen to have any desired duration.

The control logic of FIGURE 2 also can be used in its illustrated form in those systems in which the required solenoid energization period is less than a full print cycle. When so employed, reset pulses are applied, in the proper sequence, only to those flip-flops -1--50-N which were previously set. In systems of the latter type, however, it is not necessary to limit the reset pulses only to the previously set flip-flops. Stated in another way, reset signals could be applied unconditionally to all of the flip-hops in sequence. The manner in which the FIGURE 2 network can be modified for this latter type of operation, and the resulting savings in hardware, will now be discussed.

FIGURE 3 is a modified version of the resetting circuitry that may be employed in the control network of FIGURE 2. As shown in FIGURE 3, the various outputs of second counter 62 are applied directly to the reset inputs of the flip-Hops 50-1-50-N. This change eliminates the second logic 58, Le., gates -1-70-N and Hip-Hop 130 of FIGURE 2 which, in turn, makes unnecessary the seventh coincidence gate 122. With these components omitted, there no longer is a need or use for the delayed input signals which were supplied by second gate 86 to the delay means 92 via OR gate 90. Consequently, the 0R gate is omitted and, as shown in FIGURE 4, the output of first gate 84 is applied directly to the delay means 92 as the only input thereto. The output of the delay means 92 (FIGURE 4) is applied at the input terminal 140 of the sixth gate 120 (FIGURE 3).

In the operation of the control network as thus modified, the selected ones of the flip-Hops 50-1-50-N are set in the same manner as previously described in connection with FIGURE 2. A print cycle commences with the application of a START signal to first gate 84. Assuming that START flip-Hop is in the set state, gate 84 becomes fully enabled and produces an output pulse when the next TPD pulse is applied thereto. This output pulse sets the SET flip-flop 88 to allow the TPA pulses to advance or trigger rst counter 60.

In addition, the output pulse from first gate 84 is applied at the input of delay means 92 and, after a delay D, emerges at the output thereof and is applied to sixth gate (FIGURE 3). Assuming D=XT, where X is an integer, the delayed pulse emerges at the output of delay means 92 concurrently with the generation of a TPD pulse by generator 78 (FIGURE 2). In that case, the TPD pulse is selected for application to a second input of sixth gate 120. The output of this gate sets the RESET fiip-flop 124 to allow the TPA pulses to advance the count in second counter 62.

Thus, the advancing or triggering of second counter 62 is delayed relative to the advancing of first counter 60 by a time D, determined by the delay means 92. Second counter 62 then applies reset pulses to the flp-flop 50-1- 50-N unconditionally and in sequence, successive fiipflops receiving reset pulses during successive time periods T. As in the case of the FIGURE 2 network previously discussed, the delay D need not be an integral number of time periods. Other time delays are possible, provided that the proper timing pulses TPA, TPB, TPC or TPD are selected for application to the sixth gate 12|) and the eighth gate 126.

From the operation just described, it will be apparent that the sole function of delay means 92 (FIGURE 4) in the modified arrangement is to delay the start of triggering of second counter 62 relative to the start of triggering of first counter 60. According to a further modification, this delay function is accomplished by coupling a selected output of first counter 60 (FIGURE 5) to the input terminal of the sixth gate 120 (FIGURE 3). Delay means 92 then can be eliminated from the network. In the operation of this modified arrangement, RESET fiip-op 124 (FIG- URE 3) rernains in the reset state until first counter 60 reaches a predetermined count. The selected output of first counter 60 then is energized and enables one input to sixth gate 120 (FIGURE 3). At TPD, the other input to the gate becomes energized, RESET ip-op 124 becomes set, and its (l) output then enables the application of TPA pulses to the advance input of second counter 62.

Although the control and timing network has been described, by way of illustration, as controlling the selective energization of hammer solenoids in a skewed print drum system, it should be mentioned that the network also may be used for control purposes in some types of so-called chain printers. lt should be appreciated, however, that the system has 'wide general applications, and its use is in no way limited to printer systems.

What is claimed is: 1. The combination comprising: first and second counter means each having an input and at least N different operating states representing N different counts;

N bistable circuits each related to a different one of the N counts and each having a set input and a reset in- Put;

means for applying a first series of pulses at the input of the first counter means;

input signal means;

logic means responsive to an input signal and to the operating state of the first counter means for applying a signal at the set input of the related bistable circuit;

means for applying a second series of input pulses at the input of the second counter means, the first pulse of the second series commencing at a later time than the rst pulse of the first series; and

means responsive to the operating state of the second counter means for applying a signal at the reset input of the related bistable circuit.

2. The combination as claimed in claim l, wherein the last-mentioned means applies a signal unconditionally at the reset input of the related bistable circuit.

3. The combination as claimed in claim l, wherein the last-mentioned means is operative only upon receipt of a delayed input signal, and including means for delaying each input signal and applying same to said last-mentioned means.

4. The combination as claimed in claim l, including means responsive to a count of N in said rst counter means for resetting said rst counter means to a reference state, and means responsive to a count of N in the second counter means for resetting the second counter means to a reference state.

5. The combination as claimed in claim 1, wherein each input signal occurs during a different selected one of a succession of time periods of duration T each, and wherein the pulses of both the first series and the second series have a frequency f: 1/ T.

6. The combination as claimed in claim 5, wherein the means for applying the first series of pulses to the first counter means includes a first multiple input gate having one of its inputs coupled to receive pulses of said frequency f and having an output coupled to the input of said first counter means, and wherein the means for applying the second series of pulses to the second counter means includes a second multiple input gate having one of its inputs coupled to receive pulses of said frequency f and having an output coupled to the input of the second counter means.

7. The combination as claimed in claim 6, including: a first bistable means having a set input, a reset input, and an output coupled to a second input of the first gate; a second bistable means having a set input, a reset input, and an output coupled to a second input of the second gate; first setting means for `applying a signal at the set input of the first bistable means at the start of an operating cycle; second setting means for applying a signal at the set input of the second bistable means a given time after a signal is applied at the set input of the first bistable means; means responsive to a given count in the first counter means for applying a signal at the reset input of the first bistable means and for resetting the first counter means to a reference count; and means responsive to a given count in the second counter means for applying a signal at the reset input of the second bistable means and for resetting the second counter means to a reference count.

8. The combination as claimed in claim 7, wherein said second setting means is operative in response to a predetermined count in said first counter means for setting said second bistable means.

9. The combination as claimed in claim 7, wherein said second setting means includes a delay means having its input coupled to the output of the first setting means and having its output coupled to the set input of the second bistable means.

10. The combination as claimed in claim 9, wherein each said input signal also is applied at the input of said delay means and wherein the means responsive to the operating state of the second counter means for applying a signal at the reset input of the related bistable circuit is operative only in response to a delayed input signal received at the output of said delay means.

11. The combination comprising: N bistable circuits each having a set state, a reset state,

'and an output;

first counter means having an input and being capable of counting to N, each diierent count corresponding to a different one of said N bistable circuits;

second counter means having an input and being capable of counting to N, each different count corresponding to a different one of said N bistable circuits;

means providing a series of input signals each occurring during a different selected one of a succession of time periods T;

means for applying a series of pulses of frequency f=l/T at the input of each of the first and second counter means;

first logic means responsive to an input signal and to the count stored in said first counter means for setting the corresponding one of said bistable circuits;

delay means connected to receive and delay each input signal; and

second logic means responsive to an output from said delay means and to the count stored in said second counter means for resetting the corresponding one of said bistable circuits.

12. The combination as claimed in claim 11, including means responsive to a count of N in said first counter means for resetting said first counter means to a reference state, means responsive to a count of N in said second counter means for resetting said second counter means to a reference state; and N printing transducers each coupled to the output of a different one of said bistable circuits.

13. The combination as claimed in claim 11, wherein there are N time periods in an operating cycle, wherein each of the series of pulses applied at the input of said first counter means is applied during a different one of said N time periods, and wherein the series of pulses applied at the input of said second counting means commences at a later time D, where D is the time delay provided by said delay means.

14. The combination as claimed in claim 1l, wherein said input signal means includes: a data store having a capacity for storing a group of at least N binary data characters; a character comparator; means supplying a search character to said comparator for comparison with said data characters; means for reading out a different data character from said store to said comparator during each different one of said time periods; and wherein an input signal is generated when the two characters being compared during a time period are identical.

1S. The combination as claimed in claim 14, and including:

N printing transducers aligned in a row and each being coupled to the output of a different one of said bistable circuits;

a member disposed opposite said transducers and being spaced therefrom to define an area for receiving a recording medium;

said member having type characters thereon arranged in N columns `and M rows, each of said columns being opposite a different one of said transducers;

the type characters in any given row being identical;

and

means for moving said columns of type characters past the respective printing transducers.

16. The combination as claimed in claim 15, wherein said member is a cylinder rotatable about an axis parallel to said row of transducers, said N columns of type characters are N peripheral rings of type characters on said cylinder normal to said axis, yand said M rows are identically skewed relative to said peripheral rings with the distance between adjacent ones of said rows being a con- Stam.

17. The combination as claimed in claim 16, wherein the angle of skew and the distance between adjacent ones of said M rows is such that the Nth type character of any row moves into printing position opposite its respective transducer before the first type character of the next row moves into printing position opposite its transducer as said cylinder is rotated.

18. The combination as claimed in claim 17, wherein said means supplying a search character to said comparator is operated in synchronism with the rotation of said cylinder, the output of said character supplying means is a binary character corresponding to the type character then in printing position, and the character output of said supplying means is changed each time a new type character in the first column of said cylinder approaches close to printing position.

19. The combination as claimed in claim 18, wherein cach of the N type characters in a row of said cylinder is in printing position opposite its respective printing transducer during a different one of said time periods, and wherein the pulse applying means for said first counter means includes: `a p-fiop having `a set input, a reset input, and an output; a coincidence gate having a first input coupled to the output of said flip-liep, a second input, and an output coupled to the input of said first counter means; means for applying 'a control signal at the set input of said Hip-flop each time a new character in the first column of said cylinder nears printing position during a printing operation; means for applying a pulse 'at the second input of said gate once during each of said time periods; and means for applying a signal at the reset input of said fiip-op when the count in said first counter means reaches N.

20. The combination as claimed in claim 19, wherein the pulse applying means for said second counter means comprises: a second fiip-flop having a set input coupled to the output of said delay means, a reset input and an output; a second coincidence gate having a first input coupled to the output of said second flip-nop, a second input, and an output coupled to the input of said second counter means; means for applying said control signal to said delay means; means for applying a pulse at the sec ond input of said second coincidence gate once during each of said time periods; 'and mean for applying a signal at the reset input of said second ip-liop when the count in said second counter means reaches N.

References Cited UNITED STATES PATENTS 6/1953 Hartley lOl-93 6/1962 Deerfield S40-172.5

Claims

1. THE COMBINATION COMPRISING: FIRST AND SECOND COUNTER MEANS EACH HAVING AN INPUT AND AT LEAST N DIFFERENT OPERATING STATES REPRESENTING N DIFFERENT COUNTS; N BISTABLE CIRCUITS EACH RELATED TO A DIFFERENT ONE OF THE N COUNTS AND EACH HAVING A SET INPUT AND A RESET INPUT; MEANS FOR APPLYING A FIRST SERIES OF PULSES AT THE INPUT OF THE FIRST COUNTER MEANS; INPUT SIGNAL MEANS; LOGIC MEANS RESPONSIVE TO AN INPUT SIGNAL AND TO THE OPERATING STATE OF THE FIRST COUNTER MEANS FOR APPLYING A SIGNAL AT THE SET INPUT OF THE RELATED BISTABLE CIRCUIT; MEANS FOR APPLYING A SECOND SERIES OF INPUT PULSES AT THE INPUT OF THE SECOND COUNTER MEANS, THE FIRST PULSE OF THE SECOND SERIES COMMENCING AT A LATER TIME THAN THE FIRST PULSE OF THE FIRST SERIES; AND MEANS RESPONSIVE TO THE OPERATING STATE OF THE SECOND COUNTER MEANS FOR APPLYING A SIGNAL AT THE RESET INPUT OF THE RELATED BISTABLE CIRCUIT.