US3390254A - Incompatible modulus counting device - Google Patents

Description

June 25, 1968 Filed Feb. 3. 1964 SOLENOID R. S. LUNDIN 2 Sheets-Sheet 1 SH 94E I l l I I l I l SOLE NO I DH l I I I I l SIR 7 DRIVER AND GATE DRIVER sTAG E DRIVER STAGE sTAGE PULSE SOURCE MONOSTABLE B BISTABLE M/CIRCUIT CIRCUIT I s I R T I u I i- TENS ,2 UNITS )i I 1 1/} ill DRIVER AND GATE DRIVER sTAG E DRIVER sTAGE STAGE 0/ 011 PULSE souRcE K- THREE 5 BISTABLE p COUNTER cIRGuIT ,NVENrOR ROBERTS. LU/VD/N ATTORNEY June 25, 1968 R. s. LUNDIN 3,390,254

INCOMPATIBLE MODULUS COUNTING DEVICE I Filed Feb. 5, 1964 2 Sheets-Sheet f;

United States Patent 3,390,254 INCOMPATIBLE MODULUS COUNTING DEVICE Robert S. Lundin, Thomaston, Conn, assignor to General Time Corporation, New York, N.Y., a corporation of Delaware Filed Feb. 3, 1964, Ser. No. 342,171 26 Claims. (Cl. 23592) ABSTRACT OF THE DISCLOSURE An incompatible modulus counting device comprising an electrically actuated and electrically indicating counting module adapted to count to a fixed modulus. In order to count to a total count less than said fixed modulus, the

electrical indications provided by all counts higher than the desired total count are connected in a feedback circuit to the electrical module drive. Thus, upon attaining a count higher than the desired count, the module is advanced a unit count at a time to zero.

The feedback loop may include an AND gate such that the module may selectively count to its fixed modulus or to the desired lower unit count. In a 24 hour clock the unit hours module counts first to 9 to indicate 19 hours, then to 3 to indicate 23 hours; the AND gate being enabled by the attainment of a count of 2 in the tens hours module or by a separate counter activated each time the unit hours module attains its full modulus ten.

An electronic clock utilizing such modules comprises a unique monostable circuit for setting a bistable circuit controlling the AND gate. The bistable circuit is reset each time the tens hours module attains its full modulus often.

A unique inhibiting circuit for inhibiting electrical readout of a counting module during a change in the count is also disclosed.

This invention relates to a counting device employing individual counter modules which are designed to count to a given modulus, but which in this device are arranged to count to another number not an integral multiple of their moduli. It has particular relation to a digital clock device which counts up to twenty-four or twelve hours using individual counter modules each having a modulus of ten.

In contrast to the more common type of clock having hands which move continuously across a dial face, there is another type of clock employing a digital read-out approach in which the time may be read directly from number wheels. These wheels are generally situated in order from left to right so that each one represents a different digit of a time reading displayed on the face of the clock. The various number wheels are driven at a timed rate, with intermittent motion gear trains to determine the proper speed ratios between the wheels representing minutes, tens-of-minutes, and hours respectively. The first two number wheels on the right represent the two decimal orders, i.e. units and tens, of a minutes reading ranging from zero to fifty-nine. The first number wheel on the right is generally marked with numerals from zero to nine about its periphery, and is stepped one number position each minute. The second number wheel from the right is generally marked with the numerals zero to five about its periphery, and is stepped one number position every ten minutes. At the end of one hour these two number wheels step from fifty-nine to zero. The hours reading is generally provided by another number wheel on the left marked with numerals from one to twelve about its periphery, which is stepped one number position each hour.

The prior art arrangement just described has a number of disadvantages which it is among the objectives of this 3,390,254 Patented June 25, 1968 ice invention to overcome. First, intermittent motion gear trains may be expensive and difficult to manufacture, because they involve a number of precision parts having fairly complex shapes. One way of getting around this ditficulty is by using individual electromechanical counter modules with respective number wheels at each of the digit positions. In this way the carry from one digit position to another may be accomplished easily and inexpensively by electrical means. Standard electromechanical counters which are commercially available commonly provide synchronized commutation and other electrical switch opeartions to facilitate this.

Second, if it is desired to make a digital clock which covers a twenty-four period instead of the more common twelve hour period, then in the prior art clock it is diificult to put numerals from one through twenty-four about the periphery of the hour wheel without making those numerals much smaller than the numerals on the minutes wheels. The hours numerals may even be so small as to cause difiiculties in reading from a distance. This problem may be solved by having separate number wheels for the units hours digit position and the tens-of-hou-rs digit position, but this has the disadvantage of requiring an extra number wheel plus introducing certain complications in the intermittent drive owing to the fact that the units hours wheel must make two full cycles from zero to nine plus one truncated cycle from zero to three. Once again, this problem can be avoided by using electromechanical counters, since different counters can be used to represent the different orders of the hours reading, and the carry from one digit position to another, as well as the problem of the truncated cycle, can be handled electrically.

Third, in a prior art clock a certain amount of expense is entailed by the requirement of three or four different types of number Wheels, i.e. a units minutes wheel marked from zero to nine, a tens-of-minutes wheel marked from zeroto five, and either an hours wheel marked from one to twelve or a pair of hours wheels marked from zero to nine and from zero to two respectively (in the case of a twenty-four hour clock). Once again, the use of electromechanical counter modules for each of the digit positions in the time read-out avoids this problem, since the counters may all be identical, and no special mechnical equipment is required for any digit position.

Standard commercially available electromechanical counters are inexpensive enough to permit a considerable reduction in the cost of a digital clock. Another advantage is that the commutators and switch operations which are available as standard equipment on many counters of this type provide electrical read-out which makes it easy to use a digital clock of this type for program control of various types of electrically actuated equipment. For example, it may be desired to employ a twenty-four hour clock of this type to control equipment for monitoring the condition of a patient in a hospital, or the performance of a radio transmitting station, over a full days cycle.

However, most of the inexpensive standard commercially available electromechanical counters have a modulus of ten for use in the usual decimal type of counting device. This invention contemplates a new way of adapting modulo ten counters for use in a device which counts minutes by groups of sixty and/or hours by groups of twelve or twenty-four. While the invention will be described below in connection with the specific environment of a twenty-four hour digital clock, it should be realized that the principles involved are also applicable to other types of equipment in which one wishes to count to a number which is incompatible with the moduli of the individual count modules employed.

Therefore it is among the objects of this invention to provide a device which solves the problem of incompatibility between counting moduli. More specifically it is an object to provide a twelve or twenty-four hour digital clock employing inexpensive standard counter modules having a modulus of ten. Another object is to avoid the disadvantages of prior digital clocks of both the twelve and twenty-four hour variety. An additional object of the invention is the provision of a pulse-stretcher circuit which provides buffering for the time control input to a digital clock, as well as for the command output from such a clock to monitoring equipment which it controls. A further object is to provide a delay circuit which makes the output command circuit compatible with the switch ing rate of the electromechanical counter commutators. Another object is to provide a novel type of monostable circuit.

Briefly stated, the invention comprises a counting device such as a digital counter type of electric clock. There are a pair of counting modules arranged to represent different orders of a multi-digit number. Advancing means are responsive to inputs for repeatedly advancing the lower order module an increment at a time. This advancing means has a primed and an unprimed condition. The lower order module counts increments up to a selected modulus, and then returns to its starting position for the start of the next counting cycle. The higher order module is advanced an increment each time the lower order module returns to its starting condition. The higher order module is also arranged to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle. The advancing means resets the lower order module to its starting condition whenever the advancing means is in a primed condition at the same time that the lower order module attains a selected count less than its modulus. Means are arranged to prime the advancing means when the counting device attains a count equivalent to a selected number of full cycles of the lower order module. Thereafter, the next cycle of the lower order module is truncated. Means are also provided for causing the advancing means to return to its unprimed condition when the higher order module is reset. Additional features of the invention concern the reset of the higher order module, as well as still lower order modules.

A further feature of the invention contemplates the use of electromechanical counter which accomplish each incremental step in a two-part operation, and provides a circuit which enables read-out equipment to take its command from the digital counter device after the second part of this stepping operation has been completed.

The invention further contemplates circuitry which stretches brief counter input pulses to make them long enough for successful operation of the counter, and which also stretches brief counter output pulses to make them long enough for successful operation of subsequent monitoring circuitry.

Another feature concerns a monostable circuit for priming the advancing means of the lower order counting module.

The features briefly summarized above, and others, will now be more fully described in connection with the following drawings which accompany this specification:

FIG. 1 is primarily a schematic block diagram illustrating one embodiment of a digital twenty-four hour clock according to this invention.

FIG. 2 is a schematic circuit diagram of the digital twenty-four hour clock illustrated in FIG. 1, but shown here in greater detail.

FIG. 3 is primarily a schematic block diagram of a different embodiment of a twenty-four hour digital clock according to this invention.

In FIG. 1 the counting circuit shown comprises two parts, one on the right for counting units, and another on the left for counting tens. Units are registered by any known type of electromechanical counter U including a commutator which is stepped in synchronism therewith. Mechanical aspects of such a counter are conventional and are not illustrated. The units counter U has ten different positions corresponding to commutator contacts numbered from zero to nine. As seen in the drawing a units commutator wiper arm WU initially engages commutator contact U0. As the units counter U is advanced the wiper arm WU steps around to each of the next numbered commutator contacts in succession. After going past contacts U1 through U9 the wiper arm WU returns to its starting point at contact U0. For many purposes, including a digital clock display, a zero to nine number wheel (not shown) would be stepped in numerical synchronism with the wiper arm WU.

The units counter U is stepped one number position for each input delivered to its actuating solenoid LU. Current for this solenoid is provided by a driver stage DU which in turn is intermittently actuated by pulses from a source P. For clock purposes the pulse source P might have a timed repetition rate of one pulse per hour, in which case the units counter U would count units of hours.

Every time that the units counter U completes a cycle of ten counts and returns to the zero starting point, a cam causes one momentary closure of a normally open switch SU. This delivers an impulse to a tens driver stage DT. The driver stage DT then provides one pulse of energization to a tens solenoid LT to operate a tens counter T, whichincludes a wiper arm WT and commutator contacts T 0 through T9, and is identical in structure and operation to the units counter U described above. In clock applications, the tens counter would count tens of hours.

A single cycle of a twenty-four hour clock will serve to illustrate the operation of the invention. At the beginning of the day both wiper arms WT and WU are in their starting positions, engaging their respective zero contacts T0 and W0. During the next nine hours the units wiper arm WU steps at a rate of one number position per hour until it reaches contact U9. Then at 10 A.M. the wiper WU steps another position and returns to its starting condition, engaging the zero contact U0. At this time the normally open units switch SU is momentarily closed to transmit a single impulse to the tens driver stage DT which then provides a single pulse of energization to the tens solenoid LT. This causes the wiper arm WT of the tens counter to step from contact T 6 to contact T1. The two counters T and U then read one and zero respectively from left to right, as a result of which the time read-out is 10. During the next ten hours of operation the units counter U repeats its cycle, and then once again steps the tens counter another number position so that the clock progresses through readings 11 to 20. At this time, the tens wiper arm WT engages contact T2 to transmit an electrical impulse to a monostable circuit M which then prov-ides a single output pulse for setting a bistable circuit B. This bistable circuit thereafter remains in its set or primed condition for the remaining four hours of the cycle. When in the set condition, bistable circuit B provides a continuous enabling output to an and-gate driver stage A. This latter circuit performs the logical and function by detecting coincidence between the set output of bistable circuit B and another output obtainable from units counter contacts U4 through U9.

At this point nothing further happens in the and-gate driver stage A because there is no coinciding output from contacts U4 through U9. However, the output from the bistable circuit B has enabled the and-gate driver stage A and prepared it for receipt of an output from the units counter U. During the next three hours of operation the units counter U continues on its third cycle of operation, stepping one number position per hour. At the end of the twenty-fourth hour the wiper arm WU engages contact U4. At this time the two necessary inputs to and-gate driver stage A coincide, whereupon circuit A behaves exactly like the driver stage DU and provides a single pulse of energization to units solenoid LU, causing the units counter to step immediately to contact U5 without waiting for the passage of another hour. As units wiper arm WU leaves contact U4 and passes on to contact US, this causes a second discrete pulse to be applied to the and-gate driver stage A. As a result, the stepping process is repeated and the units wiper arm WU passes 'on to the next contact U6. The connections are such that this process is repeated several more times until finally the wiper arm WU is stepped from contact W9 to its original starting condition at contact W0. There it comes to rest, since U0 is the first contact to be reached which has no connection to the and-gate driver stage A. In this manner the units counter U on reaching the U4 position is rapidly stepped to the U0 position to reset itself at the end of the twenty-four hour cycle.

As it returns to the U0 position, the units counter U once more operates the units switch SU to pulse the driver stage DT and operate the solenoid LT of the tens counter T. This causes the tens counter to step from contact T2 to contact T3. Since contacts T3 through T9 are connected to the tens driver stage DT, a series of impulses then occurs which causes the tens counter to step around to contact T0 to reset itself at the end of the twenty-four hour cycle in the same manner as was described above for the units counter U. Upon resetting of the tens counter T tens switch ST is operated and transmits a single pulse to the bistable circuit B which returns the latter to an unprimed condition. Thus circuit B is also reset and ready to start the next twenty-four hour cycle.

In digital clocks constructed according to the principles just described, this resetting operation of the counters has been observed to be rapid and reliable. As the digital clock counts up to its limit of twenty-four hours there is a brief buzz in which the units counter U literally zips around to its starting position, followed immediately by another short buzz in which the tens counter T does the same. There is only a very brief moment during which the clock reads twenty-four hours, after which the reading flicks rapidly to zero zero within approximately a second.

The principles exemplified by FIG. 1 could be applied to a twelve hour clock. The only changes necessary would be to connect the monostable circuit M to contact T1 instead of T2, connect the driver stage DT to contact T2 in addition to the contacts T3-T9 to which it is now connected, and connect and-gate driver stage A to contact U3 in addition to the contacts U4-U9 to which it is now connected. With these modifications, counter U will step through one full cycle of ten hours, causing counter T to step to contact T1, thereupon triggering monostable circuit M to prime bistable circuit B. The next cycle of counter U will be truncated at two hours, with reset of the clock then taking place. Thus the total operating cycle time will be twelve hours. These principles can be extended to count to any other modulus desired, e.g. ninetynine, whether for clock purposes or any other purpose.

The system of FIG. 1 is re-illustrated in FIG. 2 in greater circuit detail and also in more complete form. Specifically, the circuit includes four electromechanical counter modules which represent minutes, tens-of-minutes, hours, and tens-of-hours respectively. Power for the system is provided by a positive bus 20, and a negative bus 22 which is connected directly to ground. A timing input of one pulse per minute is delivered over a lead 24. The source of this timing input may be a normally open switch which is momentarily closed at one minute intervals by a synchronous motor operated from calibrated sixty cycle power lines, or the output of an electronic counter which divides calibrated sixty cycle per second voltage by a scaling factor of thirty-six hundred to produce one pulse per minute, or any other conventional timing means with the required electrical output. Whatever the one pulse per minute source, there may be a problem of pulse duration. The duration of the input pulse may not be long enough to keep a solenoid on for the time required to step an electromechanical counter. Or it may be too long, with the result that the counter will be energized for a longer period of time than necessary. The latter condition is not only wasteful of power, but also delays the operation of the digital clock if the type of counter is used which does not complete its stepping stroke until its solenoid is de-energized.

Accordingly, there is provided an input pulse-stretcher circuit IPS which responds only to the positive-going leading edge of the input pulse on lead 24. Thus the duration of the input pulse after that leading edge is not important. Then the circuit IPS produces a sustained output pulse of a duration that is determined by its own internal time constant, which of course may be tailored to the requirements of the solenoids employed.

The input circuit of pulse-stretcher IPS includes a differentiating network C3, R14 which passes the positivegoing leading edge of the input through a resistor R18 to the base of transistor Q9, the first stage of circuit IPS. Q9 then turns on and draws collector current from the positive bus 20 through the Q8 emitter-base junction and limiting resistor R17. This Q8 base current turns on Q8, the second stage of pulse-stretcher IPS, which then draws current through its emitter diode from the positive bus 26. Part of the collector current of Q8 flows through a driver solenoid LUM to ground, while the remainder of it flows through a feedback path including resistor R20, capacitor C2, base resistor R18 and the base-emitter junction and emitter diode of the first stage Q9 to the ground bus 22. As long as this feedback current continues to flow, charging C2, the base current fed back to Q9 maintains Q9 in a conducting condition after the triggering input on lead 24 has terminated. In other words, regenerative feedback latches the two stages Q9 and Q8 in a mutually aiding on condition for a time determined by the time constant of C2 and its associated resistances. When C2 becomes fully charged, the feedback current through it terminates and Q9 is allowed to turn off. This in turn allows Q3 to turn off. C2 then discharges through resistor R19 and through resistor R20 and solenoid LUM, thus prolonging solenoid energization a bit longer. Thus there has been described a novel and inexpensive pulse-stretcher circuit which operates in response to inputs of inappropriate pulse duration and provides an output of a duration which is independently determined, and which may be tailored to the particular requirements by means of inexpensive RC timing components.

The input pulse-stretcher second stage Q8 and its associated circuitry comprise a solenoid driver circuit DUM which is typical of those employed for each of the four counter modules in this circuit. During the time (the stretched pulse duration) that Q8 remains on, it delivers a single energization puse of adequate duration to counter solenoid LUM. All the counters used here are of the type which prevent multiple advances on a single pulse, since energization of the solenoid produces half a step of the counter, the other half step occurring on deenergization. Thus when C2 and circuit IPS allow solenoid LUM to be decnergized, the minutes counter UM is stepped one number position, the process being repeated once for each minute of elapsed time. Diodes 31 are back-poled across all the solenoids to short-circuit inductive kick-back spikes which occur on solenoid deenergization.

On its tenth stepping operation a cam on the number wheel of counter UM momentarily closes the normally open switch SUM to deliver a pulse over lead 30 to a driver circuit DTM for the tens-of-rninutes counter. The closing of switch SUM connects base resistor R15 of transistor Q7 directly to ground. During the time that switch SUM is closed current flows from positive bus 29 through the emitter diode and emitter-base junction of Q7, base resistor R15, lead 30, and switch SUM to ground, the base current turning on transistor Q7. At this point energizing current for the tens-of-minutes solenoid LTM flows from positive bus 20 through the emitter diode and emitter-collector path of transistor Q7, and through the solenoid to ground. Then switch SUM opens, circuit DTM turns cit, and solenoid LTM is de-energized. In this manner, the tcns-of-minute counter TM is stepped one number position, the process being repeated once every ten minutes.

With the read-out of the tcns-of-minute counter TM representing the tenscf-minutes digit and that of the minutes counter UM representing the units-of-minutes digit, the result reading from left to right is a decimal representation of the number of minutes elapsed since the last hour.

At the end of sixty minutes the Wiper arm WTM of the tens-of-minutes counter TM engages its contact TM6. At this time ground potential is applied over leads 32 and 3%) to the input of the tens-of-minutes driver circuit DTM. In view of the description already given of the operation of this circuit, it will be undertsood that this causes the stage DTM to energize solenoid LTM and step the tensof-minute counter TM half-way to its next number position. As the wiper arm WTM leaves contact TM6, solenoid LTM is tie-energized and the stepping of the counter can then be completed. When wiper arm WTM engages contact TM7 another discrete pulse is applied over leads 32 and St) to circuit DTM so that stepping of the counter TM continues. The lead 32 is connected to contacts TM6 through TM9, with the result that as soon as the tens-of-minutes counter TM hits position 6 it immediately steps around until it returns to its original starting condition, engaging contact TMO. At this time counter UM is finishing its sixth full cycle, so that the minutes reading returns to zero zero to indicate the passage of a full hour.

As the tens-of-minutes counter TM resets and returns to its starting position engaging the contact TMt), it momentarily operates the normally open switch STM to transmit a pulse of ground potential over a pulse source lead P to the driver circuit DU of the hours counter U. From the discussion of counter TM it is apparent that the repetition rate of the pulses applied over the lead P is one pulse per hour. Upon receiving each pulse, driver circuit DU, operating in the manner previously described for the other driver stages, pulses the hours units counter solenoid LU to step the hours units counter U one number position.

At the end of ten hours the hours units solenoid LU returns the wiper WU to its starting position and operates the switch SU to deliver a pulse of ground potential over a lead 40 to a driver circuit DT for the tens-of-hours counter. This circuit, operating in the manner previously described for the other driver circuits, sends a single pulse of energization through the tens-of-hour solenoid LT to step the tens-of-hour counter T by a single number position. At this time the tens-of-hours counter T will be in the one" condition and, taken together with the reading of the hours units counter U, will set up decimal representations of the successive hours from ten to nineteen as the hours digits are read from left to right.

During the first twenty hours of the daily cycle, each time that the units hours counter wiper arm WU engages one of the contacts U4 through U9, ground potential is applied over a lead St to the and-gate driver stage A. However this does not cause operation of the and-gate driver stage A, because the emitter diode of its transistor Q5 is connected not to the positive bus 20 as in the case of the other driver stages, but to the bistable cir- I cuit B. The latter remains in an unprimed condition, with its transistor Q3 cut of? and unable to supply emitter potential to the and-gate driver transistor Q5 during the first twenty hours of daily operation.

However after the second full cycle of units counter U, the tens-of-hours counter wiper arm WT is stepped to its contact T2. a result, ground potential is applied over lead 68 to activate the monostable circuit M. This circuit is not the familiar one-shot circuit which reacts to an impulse and then shuts off even though the initial impulse continues to be applied. However, its operation is monostable in the sense that its off condition is the only stable state which circuit M will maintain without a continuing activating signal. When the activating ground potential input on lead 60 is applied the circuit M fires once and does not repeat until it is retriggercd. In order to be rctriggered it must first be allowed to lapse back into its unactivatcd condition. Specifically, when operation of circuit M is initiated by engaging contact T2, current flows from positive bus 2%) through a shunt resistor R1, and also through the emitter diode and emitterbase junction of transistor Q1 and capacitor C1, and then via lead 60, contact T2, and wiper arm WT to ground. During the interval that Q1 base current flows to charge C1 transistor Q1 is on. Consequently current then flows through the emitter diode and emitter-collector path of Q1, and over lead 62 and a resistor R3 of the bistable circuit B to ground.

Q1 collector current also flows through base resistor R4 and the base-emitter junction of the first stage Q2 of the bistable circuit B. As a result Q2 is turned on and draws current from the positive bus 2t) over a lead 64, through a resistor R6 and a collector resistor R5, and then through its emitter diode to ground. Current is also drawn through the emitter diode and emitter-base junction of the second stage Q3 of the bistable circuit B. This causes Q3 to turn on and draw feedback current from positive bus 2i over lead 64, through the emitter diode and emitter-collector path of Q3, and through a feedback resistor R7, base resistor R4, and the base-emitter junction and emitter diode of the first stage Q2 to ground. The feedback current regeneratively latches Q2 (and hence Q3) in a conducting condition so that henceforth the bistable circuit B remains in its set or primed condition.

Referring back to the monostable circuit M, when the capacitor C1 is tully charged, Q1 base current can no longer flow and therefore transistor Q1 turns off. However by this time the bistable circuit B has already been set and latched in its primed condition. For the remainder of the time that the tens counter wiper arm WT engages contact T2, current flows through shunt resistor R1 and maintains a voltage across the combination of C1 and R2 which keeps C1 charged and thus prevents Q1 from conducting. Thus the monostable circuit M comprises a novel and useful circuit for triggering the bistable B, and then turning off to conserve power after the bistable circuit B has been set and latched in its primed condition.

After the tens-of-hours counter T has registered twenty hours the units hours counter U continues to step each hour for the next four hours until it reaches contact U4 at the end of the twenty-four hour period. At this time ground potential is applied over lead 50 to the and-gate driver circuit A. This ground potential is communicated through base resistor R10 to the base of transistor Q5. Up until this time this base signal has had no effect on Q5 because its emitter could draw no current from the collector of the blocked transistor Q3. Now, however, over twenty hours have been counted and the bistable circuit B is primed. Q3 is therefore conducting, and its collector is substantially positive to ground and thus able to supply power to the emitter of Q5. Current flows from the collector of Q3 through the emitter diode and emitterbase junction of Q and its base resistor R10, and then over lead 50 to contact U 3, and the wiper arm WU to ground. This base current turns on transistor Q5 of circuit A and current then flows from the collector of Q3 through the emitter diode and the emitter-collector path of Q5 and then through the bulferingdiode 65 to the solenoid LU. (Buffering diode 65 prevents interaction between circuit A and circuit DU.) This advances the counter U to its US contact. in passing from the U4 to the U5 contact wiper arm WU applies a second distinct 9. input pulse over the lead 51 to the and-gate driver circuit A. This circuit again detects the coincidence of inputs from the counter U and from the bistable circuit B, and repeats its energization of the solenoid LU and stepping of the counter U. Since lead 50 is connected to the contacts U4 through U9, the counter will continue to step rapidly around to its starting position at contact U0. At this time normally open switch SU is momentarily closed, again providing an impulse over lead 40 to the tens-ofhours driver DT, energizing the tens-of-hours solenoid LT, and causing the tens-ot-hours counter to step to contact T3.

Since the wiper arm WT has been stepped to contact T3, ground potential is no longer applied to contact T2, and current flow through shunt resistor R1 therefore terminates. This removes the voltage drop across R1, which until now has been keeping capacitor C1 charged and thus blocking the Q1 base current to keep transistor Q1 cut off. However Q1 does not now turn back on again, as wiper WT no longer engages contact T2. Also, capacitor C1 must first discharge. The discharge path is through R2 and R1, and the charging polarity of C1 is as shown in FIG. 2, which assures that the voltage drop across R2 during discharge of C1 is in the wrong direction to turn on transistor Q1. This prevents spurious operation of Q1 during the resetting phase of the digital clock at the end of the day. After discharge of capacitor C1, the monostable circuit M is returned to its initial condition; i.e. transistor Q1 is off, and capacitor C1 is discharged to permit Q1 base current to flow when Q1 is turned on at the appropriate time the following day.

The stepping of wiper arm WT to contact T3 initiates resetting of counter T, since contacts T3 through T9 are connected over leads 70 and 40 to activate the driver circuit DT. Therefore in the manner previously described the circuits DT and LT are pulsed repeatedly by the stepping of wiper WT. The stepping process continues until wiper arm WT has returned to its original position engaging contact T0, at which time counter T is also reset. a

Upon resetting of counter T its normally open switch ST is momentarily closed, which serves to apply ground potential over lead 62 to the junction of the base resistor R4 and resistor R3. This removes all voltage across the emitter-base junction of the first stage transistor Q2 of the bistable circuit B, allowing Q2 to turn off. This terminates the base current of the second stage Q3 of bistable circuit B, allowing Q3 to turn off also. With both Q2 and Q3 off, the bistable circuit B is unlatched. Thus at the end of a twenty-four hour cycle the impulse from the tens-of-hours switch ST resets the bistable circuit B to its unprimed condition for the start of the next days operation.

One of the many advantages of a digital clock employing electromechanical counters is the ready availability of electrical read-out from the commutator contacts associated with each of the counters. It is seen that contacts T and T1 may be brought directly out to read-out terminals marked zero and one respectively, and that contact T2 may be brought out through a diode to a readout terminal marked two. These three read-out terminals are bracketed with the designation hours by tens. In order to prevent interaction between the monostable circuit M, which derives its triggering signal from contact T2, and the read-out circuit (not shown), which also derives a signal from the contact T2, diodes 80 are inserted in the lines for buffering purposes. Similarly, the zero through nine contacts of hours counter U are brought out to correspondingly numbered read-out terminals which are bracketed with the designation hours. Since the contacts U4 through U9 are connected to the and-gate driver circuit A as Well as to the read-out terminals four through nine, pairs of diodes 84 through 89 respectively are inserted in the leads for buffering purposes. The contacts TMtl through TMS of counter TM are also brought out to similarly numbered read-out terminals bracketed by the designation minutes by tens. In this case the commutator contacts zero through five, which are used for read-out, and the commutator contacts six through nine, which are used for counter resetting purposes as described above, are mutually exclusive groups; hence no diode buffering is necessary. In the case of the minutes counter UM, which requires no resetting, all the contacts UMO through UM9 are brought out to correspondingly numbered read-out terminals bracketed by the designation minutes. Only one pair of buffering diodes is employed, in conjunction with the contact UMO, to permit another read-out signal to be supplied by this contact over lead 92 to a command amplifier C.

The purpose of the command amplifier C and its following circuitry is to perform any desired control function in connection with electrically actuated equipment which it is desired to operate at regular timed intervals. For example, a digital clock of the type shown here may provide a print command every ten minutes throughout the day to equipment which monitors and prints out the condition of a patient in a hospital, or the performance of a radio transmitting station, or some other variable. When, at ten minute intervals, wiper arm WUM reaches contact UMO, ground potential is transmitted over lead 92 and resistor R27 to the base of transistor Q12 of the command amplifier C. When this happens current flows from the positive bus 20 over leads 94 and 96, through the emitter-base junction of Q12 and its base resistor R27, and then through lead 92 and one of the buffering diodes 90 to contact UMO and through wiper arm WUM to ground. This Q12 base current causes transistor Q12 to turn on, whereupon current drawn from lead 96 flows through the collector of Q12 and lead 98 to an output pulse-stretcher circuit OPS. When wiper arm WUM leaves contact UMO, the command grgplifier C turns oil, but by then it has triggered circuit Circuit OPS works in the same manner as the previously described input pulse-stretcher circuit IPS. Its function is to lengthen the duration of the command pulse provided by command amplifier C so that the output of circuit OPS will be long enough to assure reliable operation of equipment such as a printer. The collector current of transistor Q12 of the command amplifier C flows through lead 98, resistor R28, and lead 100' to ground. It also branches off and flows for a time through OPS triggering capacitor C5, base resistor R30, and the base-emitter junction and emitter diode of the OPS first stage Q13 to ground lead 100. This base current turns on Q13, whereupon current flows from positive bus 29 and lead 94 through resistors R33 and R32, transistor Q13, and its emitter diode to ground lead 100. Part of the Q13 current also flows through the emitter diode and emitter-base junction of the second stage Q14 of the output pulse-stretcher circuit OPS, thus turning on Q14.

Current then flowing in lead 94 branches off through the emitter diode and the emitter-collector path of Q14, and then through a feedback path comprising the collector resistor R31, feedback capacitor Q6, base resistor R30, and the base-emitter junction and emitter diode of Q13 to ground lead 100. As long as capacitor C6 is charging, the feedback current through C6 and R30 keeps Q13 turned on. This is another example of the temporary regenerative feedback arrangement as previously described in connection with input pulse-stretcher circuit IPS. This feedback keeps these pulse-stretcher circuits latched regeneratively for a time determined by the time constant of the feedback capacitor, in this case C6, and its associated resistances. When C6 becomes fully charged, the second stage Q14 no longer feeds back to the first stage Q13 of output pulse-stretcher OPS.

Prior to this time, the initial current through C and R39 which originally turned on the first stage Q13 has resulted in chargim of the capacitor C5 and a cessation of Q12 collector currrent through base resistor R39. As a result, the current through R39 required to sustain Q13 in its conducting condition now comes solely from Qi ts feedback connection through capacitor C6. For this reason, when the feedback current through C6 also terminates, Q13 is able to turn off, which allows Q14 to turn off also, terminating the activation of circuit OPS. When the command amplifier transistor Q12 turns oh, the OPS triggering capacitor C5 discharges through resistor R28 and diode 102.

During the extended period of time that transistor Q14 conducts, its collector voltage goes high, thus applying a positive output pulse over lead 104 to one of two output terminals labeled print command pulse. The other of these output terminals is connected to ground bus Till). Across these terminals may be connected any suitable load, such as the input of a printer control circuit. Furthermore, as feedback capacitor C6 becomes fully charged and causes the output pulse-stretcher circuit to turn off, C6 prolongs the output applied to the print command pulse terminals by discharging through resistor R31 and lead 1% to one print command pulse output terminal, and through diode 1G2 to the ground bus Tilt), which is connected to the other print command pulse output terminal.

The need for an inhibiting circuit INH arises as a result or" the characteristics of a particular type of electromechanical counter which may be employed with the digital clock of this invention. Specifically, in order to avoid double advancing on a single pulse, these counters operate in the following manner. When the solenoid of the counter is energized the armature actuates a mechanism which advances the couner (i.e. the number Wheel and the commutator) one half step. The counter remains in this half-advanced condition for the remainder of the time that its solenoid is energized. Then when solenoid energization terminates, a return spring activates the advancing mechanism to complete the next half-step or" the counter. Such counters are available, for example, from Rheinische Telefon Gesellschait of Dusseldorf, Germany. Thus the switching of the commutator wiper arms WUM, WTM, WU and WT from one numbered contact to the next numbered contact is not completed until some time after de energization of their respective solenoids LUM, LTM, LU and LT. The purpose of the inhibiting circuit INH is to inhibit activation of the command amplifier C until an appropriate delay interval after the energization of the solenoids has been terminated. In this way, no potential is applied to the print command output terminals until all the wiper arms have come to rest at their next contact positions.

Note first that this problem does not arise in connection with the minutes counter UM, since the command amplifier circuit C can not be activated until the wiper arm WUM has moved to engage the contact UMO to deliver a base drive pulse to transistor Q12 over lead 92. Thus, the print command output pulse will always be generated by circuits C and CPS at a time when the minutes wiper arm WUM is engaging this contact. However in most applications the information printed out would include, in addition to such parameters as the blood pressure of a hospital patient, or the signal strength of a transmitting antenna, the times (at ten minute intervals) at which the successive readings are taken. This time information may be taken directly from the read-out terminals labeled minutes, minutes by tens, hours, and hours by tens. Therefore it is essential that print-out not occur until the remaining counters TM, U and T have completed their advance.

Accordingly, the base of transistor Qltl, the first stage of the inhibiting circuit INT-l, is connected through base resistor R22 and lead lit to each of the solenoids LTM, LU and LT. Buficring diodes 112 are inserted in the lines going to the individual solenoids to prevent interaction between thcm. This base drive connection is made to the side of each solenoid which goes positive when the solenoid is energized. As a result, during energization of any one or more of the three solenoids ioned, current flows through the diode or diodes 112, the lead 110, the base resistor R22, and the emitter-base junction of the first stage transistor Qlti to ground. This base current turns on transistor Q10. Collector current then flows from position bus 20 through leads 9d and 96, a capacitor C-i, a collector resistor R23, and then through Qlii to ground. As this current charges capacitor C4, this current flow begins to be diverted through the emiIter-base junction of the second stage Q11 and its base resistor R24. This base current switches Q11 on and holds it on during the time that the capacitor Q4 stays charged. When Q11 is on, it presents a very low impedance between its collector and the positive power supply potential on leads 96 and 94 and positive bus 20. Thus the junction between the collector of Q11 and the base of the command amplifier transistor Q12 is driven positive, which makes it impossible during this time to turn Q12 on. In this way, the command amplifier circuit C is disabled during the entire time that capacitor C4 remains charged.

When all of the solenoids LTM, LU and LT have been de-energized, Q10 shuts off. However it takes a period of time thereafter for capacitor C4 to discharge, and during this discharge inerral C4 keeps transistor Q11 turned on and thus keeps the transistor Q12 of command amplifier circuit C disabled. The discharge path of capacitor C4 includes the emitter-base junction of Q11 and its base resistor R24, which together are shunted di ectly across the terminals of C4. This base current due to capacitor discharge weeps Qll on for a period of time after the sole noids have been de-energized and the first stage Qlt) has been allowed to turn oil. The time constant of C4 and its associated resistances can be selected so that C4 does not complete its discharge until the wiper arms WTU, WU and WT have completed their full stop to the next numbered contact. After the counter sepping operations have been completed, C4 completes its discharge and allows the second stage Q11 to turn off. At that time transistor Q12 of the command amplifier C is no longer disabled and can respond to the input on lead 2.

A further characteristic of the counters employed makes for a smooth system operation. Specifically, the end-of-cycle counter switches SUM, STM, SU, and ST are operated during energization of their respective solenoids, i.e. the switch closure occurs during the first half-step of counter advance, as their respective wiper arms leave their number nine contacts, and not in the second half-step as the wiper arms engage their zero contacts. The best way to illustrate the importance of this fact is to consider what happens at the end of a twenty-four hour period. Assume the clock registers 23:59. The next pulse on the input lead 24 energizes solenoid LUM to step counter UM. If wiper arm WUM were now to engage Contact UMt} before the closing of switch SUM, the command amplifier C would immediately be energized and cause the time to be printed out as 23 :50, ten minutes too slow, because at this instant the units minute digit is the only one which has changed. Instead, what happens is that switch SUM closes while wiper arm WUM gees only half-way from contact UM9 to contact UMii. This energizes the next solenoid LTM, whereupon the inhibiting circuit INH is turned on via the diode 112 and lead Ill). As a result, the print-out operation is now frozen. It remains frozen while solenoid LTM is repeatedly energized to reset counter TM, and solenoid LU is then repeatedly energized to reset counter U, and solenoid LT is then repeatedly energized to reset counter T; because the repeated energization of these solenoids keeps capacitor C4 charged, and the time constant of C4 and its associated resistances is too great to permit it to discharce in the short intervals between these repeated solenoid energizations. While the counters TM, W, and T are being reset, the second half of the unit step of counter UM is completed. That is, switch SUM opens and wiper WUM engages contact UMt), but with circuit INH turned on no printing command is issued by circuit C. Only when the reset of counter T has been completed does the INH circuit turn off, allowing the print command circuitry to respond to the presence of wiper arm WUM at contact UMO. The correct time is then printed out as 00200.

FIG. 3 shows a variation of the basic circuit of FIG. 1 in which all circuit blocks are the same except that the monostable circuit M of FIG. 1 has been replaced by a counter K with a modulus of 3. A further change is that instead of being connected to the terminal T2 of the tens counter as in the case of the monostable circuit M of FIG. 1, the counter K of FIG. 3 is connected to the units counter switch SU. Accordingly, in the operation of this circuit a pulse is registered by counter K each time the units counter U completes a counting cycle and closes its switch SU. In an operating cycle of the counters T and U the first one of the three pulses is entered into counter K when both counters T and U are reset to zero. When the units counter counts up to ten, a second count is entered into counter K. When the units counter counts up to twenty, a third count is entered into the counter K. Since the modulus of counter K is three, at this point an output pulse is issued by the counter K to set the bistable circuit B in the same manner as it was set by the monostable circuit M in FIG. 1. With the bistable circuit B thus primed, the and-gate driver stage A is enabled. Then when the units counter U comes around to contact U4 on its third counting cycle of the day, the reset operation takes place as previously described in connection with FIGS. 1 and 2.

The tens counter T would have moved around to contact T2 during the first two cycles of the units counter U. Thus on reset of the units counter U, tens counter T would be stepped to its terminal T3, and would thereupon be reset in the manner previously described. Upon reset of the tens counter T, closure of its switch ST would reset the bistable circuit B as in the embodiment of FIG. 1. The counter K may be of the known type which, at the time that it delivers its count output, simultaneously and automatically resets itself so as to be ready for the start of its next counting cycle. Such a counter is fully described in Neitzerts US. Patent No. 2,897,380, which belongs to the assignee of the present invention. Thus, at the end of the second cycle of counter U, counter K produces its output and resets simultaneously. Accord ingly, on the third or truncated cycle of units counter U, when the counter U is reset it again closes its switch SU and enters a pulse into the counter K which is count number one of a new cycle of counter K.

In respect of its detailed circuitry, the embodiment of FIG. 3 would be similar to FIG. 2, except for the substitution of the counter K (with circuitry as described in the aforesaid US. patent) and its connection as shown in FIG. 3.

What has been described is a preferred embodiment and is presently believed to be the best mode of practicing the invention, but it will be clear to those skilled in this art that modifications may be made without departing from the principles of the invention. Accordingly this description is intended merely as an illustrative example, the broader scope of the invention being stated in the appended claims.

In particular, the counters used in this invention may I lack number wheels for visual read-out, ie they may simply be stepping switches, yet the electrical features of the device would be similar. For certain purposes visual readout of the time may be unnecessary, or one might prefer to use electrically actuated visual time read-out such as a bank of Nixie type tubes connected to the time readout terminals in FIG. 2. For this reason terms such as 14 counter and counting module are intended to include any device the condition of which can represent a quantity in a device of this kind, regardless of whether such condition is manifested visually, electrically, or in any other way.

The invention claimed is:

1. A pulse-stretcher circuit comprising:

a first electronic switch connected to turn on in response to an input and to conduct monostably during said input;

a second electronic switch connected to turn on in response to the conduction of said first switch and to conduct monostably simultaneously with said first electronic switch;

a regenerative feedback connection including a capacitor arranged to draw charging current from said second switch when said second switch is on, and to apply a turn-on signal to said first electronic switch during the time that said charging current flows whereby said switches may be kept on simultaneously for a selected time after termination of said input;

said first switch being arranged to turn off and thereby turn off said second switch after termination of said input and said charging current.

2. A counting module:

adapted for counting to a fixed modulus;

said counting module providing a plurality of individual output terminals for electrically indicating a plurality of respective adjacent unit counts less than said fixed modulus;

said counting module having electrical means for ad vancing it only by unit count increments;

characterized by feedback means adapting said module to count to a count at least two lower than said fixed modulus;

said feedback means being connected to each of said indicating means which indicate counts greater than said lower count to drive said electrical advancing means through a discrete unit count increment advancing operation for each such indication;

whereby when said module reaches a count greater than said lower count, it advances by at least two successive discrete unit count increments to said fixed modulus.

3. A counting module as defined in claim 2 further defined in that said counting module is solenoid actuated and said indicating means comprises a rotary switch actuated thereby.

4. A counting module as defined in claim 2 and an AND gate connected in said feedback means for controlling whether said counting module counts to said fixed modulus or said lower modulus.

5. A counting module as defined in claim 4:

arranged to count the lower order of a multi-digit number; and

means for enabling said AND gate when said module attains a preselected number of counts equal to an integral number times said modulus.

6. A counting module as defined in claim 5, further defined in that said enabling means comprises an electrical signal means providing a signal upon the attainment of each full modulus count.

7. A counting module as defined in claim 6, further defined in that said enabling means further comprises a fixed counter for counting the signals indicating each full modulus count.

8. A counting module as defined in claim 6, further defined in that:

said enabling means further comprises a second counting module adapted for counting to a fixed modulus;

said second counting module having electrical means for advancing it by unit count increments in response to said full modulus count signals from said first module;

and said second module comprising means for electrically indicating a second count less than said fixed modulus to thereupon enable said AND gate.

9 A pair of counting modules, as defined in claim 8,

further defined in that:

said second counting module comprises means for electrically indicating all unit counts greater than said second count enabling said AND gate, and

feedback means connected between said indicating means of said second counting module and the electrical advancing means thereof.

10. A pair of counting modules, as defined in claim 9, each having a modulus of ten and arranged in an electric clock to count to twelve or twenty-four hours.

11. A pair of counting modules, as defined in claim 9, and:

a third counting module adapted for counting to a fixed modulus;

said third counting module providing means for electrically indicating a plurality of adjacent unit counts less than said fixed modulus;

said third counting module having electrical means for advancing it by unit count increments in response to ten minute indicating signals;

said third counting module providing an electrical signal to the advancing means of said first count module upon the attainment of each full modulus count;

and feedback means adapting said third-counting module to count to a count lower than said fixed modulus;

said feedback means being connected between said indicating means for indicating counts greater than said lower count and said electrical advancing means.

12. Three counting modules, as defined in claim 11, wherein the modulus of each of said module is ten, said modules being arranged in an electric clock to count to twelve hours fifty minutes or twenty-four hours fifty minutes.

13. A pair of counting modules, as defined in claim 8, further defined in that:

said second module further comprises electrical signal means providing a signal upon the attainment of each full modulus count;

and bistable means set in response to said signal from said second module indicating said second count to enable said AND gate and reset in response to each signal provided by said full modulus signal means of said second counting module to disable said AND gate.

14. A pair of counting modules as defined in claim 13 and a monostable circuit for receiving said signal indicating said second count and for providing a setting signal for said bistable means to enable said AND gate.

15. A counting module as defined in claim 7 and bistable means set in response to said fixed counter attaining its total count to enable said AND gate.

16. A counting module as defined in claim 15 and a monostable means responsive to said fixed counter attaining its total count and providing a setting signal for said bistable means to enable said AND gate.

17. A counting module as defined in claim 15 and: a second counting module for counting and indicating each full modulus count of said first counting module;

said second counting module comprising electrical signal means providing a signal upon the attainment of each full modulus count;

and said bistable means being reset to disable said AND gate in response to said full count signal.

18. A counting device comprising:

a pair electrically operated counting modules arranged to represent lower and higher orders respectively of a multi-digit number;

a driver stage responsive to inputs for repeatedly advancing said lower order module an increment at a time;

said lower order module being arranged to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a driver stage connected for advancing said higher order module an increment each time said lower order module returns to its starting condition;

said higher order module being arranged to count incrcments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a bistable circuit having a primed and an unprimed condition;

a coincidence-detecting driver circuit connected to reset said lower order module to its starting condition when said bistable circuit is primed and said lower order module attains a selected count less than the modulus thereof;

a monostable circuit connected to prime said bistable circuit when said counting device attains a count equivalent to a selected number of full cycles of said lower order module, whereby the next cycle of said lower order module is truncated;

said selected number being at least two less than the modulus of said higher order module, and said higher order driver stage being connected to reset said higher order module to its starting condition when it attains a count one greater than said selected number in response to said resetting of said lower order module, whereby said counting device terminates its counting cycle and returns to its starting condition upon the conclusion of said truncated lower order cycle;

means for causing said bistable circuit to return to an unprimed condition when said higher order module is reset;

an electronic switching device including a switching electrode and a reference electrode;

a first impedance connected across said electrodes;

means for selectively causing a current to flow through said first impedance for developing a switching potential across said electrodes sufficient to switch said device for causing operation of said monostable circuit;

a capacitor in series with the current through said impedance whereby after an interval said capacitor charges, causing the current through said impedance to drop below the level required for switching said device, terminating operation of said monostable circuit;

and a second impedance connected across said first impedance and said capacitor for diverting some of the current whereby a voltage is developed thereacross to prevent discharge of said capacitor and thereby keep said monostable circuit inoperative while said current continues to flow;

said first and second impedances providing a path through which said capacitor discharges after termination of said current, .to condition said capacitor for another operation of said monostable circuit when said current resumes.

19. A twenty-four hour digital clock employing counters of modulus ten, comprising:

an hours counter and a tens-of-hours counter, each of modulus ten, and each including a switch and operating said switch at the conclusion of each of its operating cycles;

means for receiving an'input of substantially one pulse per hour and applying said pulses to drive said hours counter;

bistable means having a primed and an unprimed condition;

coincidence-detecting and driving means connected to reset said hours counter to its starting condition upon detecting the coincidence of a four count in '17 said hours counter and a primed condition in said bistable means;

driving means arranged to advance said tens-of-hours counter by one count for each operation of said hours counter switch;

means arranged to prime said bistable means when said tens-of-hours counter attains a count of two whereby when said clock attains a count of twentyfour hours said hours counter is reset, thereby advancing said tens-of-hours counter to a count of three;

means connecting said tens-of-hours driving means to reset said tens-of-hours counter to its starting condition upon attaining a count of three;

means for returning said bistable means to said unprimed condition upon operation of said tens-ofhours counter switch;

a first electronic switch including a control electrode connected for turning said switch on only while a switching signal is applied thereto, and a main current path connected for current to flow there-through when said switch is on;

a capacitor connected in series with said main current path to charge when said first switch is turned on; said first switch when turned off blocking the discharge of said capacitor through said main current path;

a second electronic switch device comprising a control electrode and a reference electrode, and connected to switch only while a switching voltage is applied across said control and reference electrodes thereof;

and shunting means including said second switch control and reference electrodes connected across said capacitor for control of said second switch by the capacitor voltage and for discharge of said capacitor;

said shunting means providing a relatively slow discharge path and said first switch main current path providing a relatively fast charging path whereby said capacitor charges to switch said second device when said first switch is on, and requires a sufficient discharge time to keep said second device switched for a selected delay period after said first switch turns oif.

20. A monostable circuit comprising:

an electronic switching device including a switching electrode and a reference electrode, said switching device being selected so that said device conducts only so long as switching current flows between said switching and referenced electrodes;

a first impedance connected across said electrodes;

means for selectively causing a current to flow through said first impedance for developing a switching potential across said electrodes sufficient to switch said device for causing operation of said monostable circuit;

a capacitor in series with the current through said impedance whereby after an interval said capacitor charges, causing the current through said impedance to drop below the level required for switching said device, terminating operation of said monostable circuit;

and a second impedance connected across said first impedance and said capacitor for diverting some of the current whereby a voltage is developed thereacross to prevent discharge of said capacitor and thereby keep said monostable circuit inoperative while said current continues to flow;

said first and second impedances providing a path through which said capacitor discharges after termination of said current, to condition said capacitor for another operation of said monostable circuit when said current resumes.

21. A counting device comprising:

a pair of electrically operated counting modules arranged to represent lower and higher orders respectively of a multi-digit number, and having respective commutators operating in synchronism with the count condition thereof;

a driver stage responsive to inputs for repeatedly advancing said lower order module an increment at a time;

said lower order module being arranged to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a driver stage connected for advancing said higher order module an increment each time said lower order module returns to its starting condition;

said higher order module being arranged to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a bistable circuit having a primed and an unprimed condition;

a coincidence-detecting driver circuit connected to all count positions of said lower order commutator above a selected count position and connected to said bistable circuit in a manner to reset said lower order module to its starting condition when said bistable circuit is primed and said lower order module exceeds said selected count;

a monostable circuit connected to a selected count position of said higher order commutator and to said bistable circuit in a manner to prime said bistable circuit when said higher order module reaches said selected count position, whereby the next cycle of said lower order module is truncated;

the value of said selected count being at least two less than the modulus of said higher order module, and said higher order driver stage being connected to all count positions of said higher order commutator above said selected count in a manner to reset said higher order module to its starting condition when it attains a count one greater than said selected count in response to said resetting of said lower order module, whereby said counting device terminates its counting cycle and returns to its starting condition upon the conclusion of said truncated lower order cycle;

and means for causing said bistable circuit to return to an unprimed condition when said higher order module is reset.

22. A counting device comprising:

a pair of electrically operated counting modules arranged to represent lower and higher orders respectively of a multi-digit number, and having respective commutators operating in synchronism with the count condition thereof;

a driver stage responsive to inputs for repeatedly advancing said lower order module an increment at a time;

said lower order module being arranged to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a driver stage connected for advancing said higher order module an increment each time said lower order module returns to its starting condition;

said higher order module being arranged 'to count increments up to a selected modulus and then return to its starting condition for the start of its next counting cycle;

a bistable circuit having a primed and an unprimed condition;

-a coincidence-detecting driver circuit connected to all count positions of said lower order commutator above a selected count position and connected to said bistable circuit in a manner to reset said lower module to its starting condition when said bistable circuit is primed and said lower order module exceeds said selected count;

an auxiliary counter having a selected modulus, and means connecting said auxiliary counter to count cycles of said lower order module, said auxiliary counter being connected to prime said bistable circuit on completion of the count of said auxiliary counter, whereby the next cycle of said lower order module is truncated;

the modulus of said auxiliary counter being less than the modulus of said higher order module, and said higher order driver stage being connected to all positions of said higher order commutator corresponding to a count which is at least equal to said auxiliary counter modulus, in a manner to reset said higher order module to its starting condition when it attains a count equal to said auxiliary counter modulus in response to said resetting of said lower order module, whereby said counting device terminates its counting cycle and returns to its starting condition upon the conclusion of said truncated lower order cycle;

and means for causing said bistable circuit to return to an unprimed condition when said higher order module is reset.

23. A digital clock covering a period of T times ten plus H hours, comprising:

a minutes counter having a modulus of M, a tens-fminutes counter having a modulus greater than 60/M, an hours counter having a modulus greater than M, and a tens-of-hours counter having :a modulus greater than T, each of said counters including a switch and operating said switch at the conclusion of each of its operating cycles, and including a commutator operating in synchronism with the count condition of said counter; cans for receiving an input of substantially one pulse per minute and applying said pulses to drive said minutes counter;

driving means arranged to advance said tens-of-minutes counter by one count for each operation of said minutes counter switch;

means connecting all positions of said tens-of-minutes commutator which correspond to a count of at least 60/M to said tens-of-minutes driving means to reset said tens-of-minutes counter to its starting condition when it attains a count of 60/ M upon the passage of :an hour;

driving means arranged to advance said hours counter by one count for each operation of said tens-ofminutes counter switch;

bistable means having a primed and an unprimed condition;

coincidence-detecting and driving means connected to all positions of said hours commutator which correspond to a count of at least H and connected to said bistable means in a manner to reset said hours counter to its starting condition upon detecting the coincidence of an H count in said hours counter and a primed condition in said bistable means;

driving means arranged to advance said tens-of-hours counter by one count for each operation of said hours counter switch;

means arranged to prime said bistable means when said 'tens-of-hours counter attains a count of T whereby when said clock attains a count of T times ten plus H hours said hours counter is reset, thereby advancing said tens-of-hours counter to a count of T plus one;

means connecting said tens-of-hou-rs driving means to all positions of said tens-of-hours commutator which correspond to a count greater than T to reset said tensof-hours counter to its starting condition upon attaining a count of T plus one;

and means for returning said bistable means to said unprirned condition upon operation of said tens-ofhours counter switch.

24. A digital counter with electrical read-out comprising:

a counter including switching means operated thereby, a solenoid operative in response to input pulses, and a mechanism which advances said switching means part of a unit step in response to solenoid energize.- tion and then advances said switching means the remainder of a unit step in response to solenoid -de-energization;

electrical read-out means connected to operate in response to ope-ration of said switching means for producing a command output;

and an inhibiting circuit turning on in response to energization of said solenoid, remaining on while said solenoid is energized, and including energystoring means delaying the turn-off of said inhibiting circuit for a sufficient time after de-energization of said solenoid to permit said counters to complete a unit step of said switching means, said inhibiting circuit being connected to block operation of said read-out means to inhibit electrical read-out during motion of said switching means.

25. A delayed switching circuit comprising:

a first electronic switch including a control electrode connected for turning said switch on only while a switching signal is applied thereto and a main current path connected for current to flow therethrough when said switch is on;

a capacitor connected in series with said main current path to charge when said first switch is turned on;

said first switch when turned off blocking the discharge of said capacitor through said main current path;

a second electronic switch device comprising a control electrode and a reference electrode, and connected to a switch only while a switching voltage is applied across said control and reference electrodes thereof;

and shunting means including said second switch control and reference electrodes connected across said capacitor for control of said second switch by the capacitor voltage and for discharge of said capacitor;

said shunting means providing a relatively slow discharge path and said first switch main current path providing a relatively fast charging path whereby said capacitor charges to switch said second device when said first switch is on, and requires a sufiicient discharge time to keep said second device switched for a selected delay period after said first switch turns off.

26. A delayed switching circuit comprising:

a first electronic switch including a control electrode connected for turning said switch on only while a switching signal is applied thereto and a main current path connected for current to flow therethrough when said switch is on;

a capacitor connected in series with said main current path to charge when said first switch is turned on;

said first switch when turned 01f blocking the discharge of said capacitor through said main current P a second electronic switch device comprising a control electrode and a reference electrode, and connected to switch only while a switching voltage is applied across said control and reference electrodes thereof;

and shunting means including a first impedance connected from one side of said capacitor to said second switch control electrode a second impedance connected from said second switch control electrode to the other side of said capacitor, and a connection from said second switch reference electrode to said other side of said capacitor for control of said second switch by the capacitor voltage and for dis charge of said capacitor;

said shunting means providing a relatively slow discharge path and said first switch main current path providing a relatively fast charging path whereby said capacitor charges to switch said second device 21 22 when said first switch is on, and requires a sufficient 3,019,388 11/1962 Thonbrogger 324 68 discharge time to keep said second device Switc e 3,201,687 8/1965 Pasquier 324--68 for a selected delay period after said first switch 3 230 3 3 1 19 MacArthur 235 92 turns 3,278,725 10/1966 Gunst -235-92 References Cited 5 UNITED STATES P N S MAYNARD R. WILBUR, Primary Examiner. 3,177,645 4/1965 Devanney 582 G. J. MAIER,Assistam Examiner.

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