US3305738A - Single bit reversible shift register responsive to sequenced (transfer and clear) pair of input pulses - Google Patents

Description

Feb. 21, 1967 P M. KINTNER 3,305,738

SINGLE BIT REVERSIBLE SHIFT REGISTER RESPONSIVE T0 'SEQUENCED (TRANSFER AND CLEAR) PAIR OF INPUT PULSES Filed March 13, 1964 QM 09M avail/Mr United States Patent 3,305,738 SINGLE BIT REVERSIBLE SHIFT REGISTER RE- SPONSIVE T0 SEQUENCED (TRANSFER AND CLEAR) PAIR OF INPUT PULSES Paul M. Kintner, Huntington Station, N.Y., assignor to Cutler-Hammer, Inc., Milwaukee, Wis., a corporation of Delaware Filed Mar. 13, 1964, Ser. No. 351,742 Claims. (Cl. 307-88.5)

This invention relates to a novel reversible shift register. I

While not limited thereto, the shift register of the present invention is particularly suitable [for use as a correction signal generator for use in a control system of the type disclosed and claimed in the Strand and Kintner application Serial No. 351,743, filed March 13, 1964, now Patent No. 3,184,879.

It is a primary object of the present invention to provide a reversible shift register that circulates a single information bit wholly between, and never outside of or beyond, its own register elements.

Another object is to provide a shift register of the aforementioned type wherein shifting of the information bit occurs in response to pairs of input pulses and Wherein constant output voltages are generated when the information bit is in either of the endmost register elements or in register elements immediately adjacent thereto.

A still further object is to provide a shift register of the aforementioned type in which no output voltage is provided when the information bit is in the storage element midway between the two endmost register elements.

Other objects and advantages of the invention Wiill hereinafter appear.

The oocompanying drawing illustrates a preferred embodiment of the invention which will now be described in detail, it being understood that the embodiment illustrated is susceptible of modifications without departing from the scope of the appended claims.

The shift register of the present invention comprises the register elements designated I, II, III, IV and V from left to right. Elements I and II have flip-flop transistor pairs Tl-TZ and T3-T4, respectively. Elements III and IV are internally like element 11 so the details thereof are omitted for simplicity. Elements I, II, IV and V have output terminals 2, 3, 4 and 5, respectively, while element HI has no comparable output terminal.

Output terminal 2 is connected in series with a diode CR1 and a resistor R1 to the base of transistor 5, and output terminal 3 is connected in series with a diode CR2 and resistor R1 to the base of transistor 5. The base of transistor 5 is connected to ground in series with a resistor R3 and its collector is connected in series with a resistor R4 to volts. The collector of TRS is also connected directly to the base of a transistor T6. The point common between diodes CR1 and CR2 and resistor R1 is connected to 10 volts in series with a resistor R5. Transistor T6 has its collector connected to 10 volts in series with a resistor R6 and to output terminal 6.

With terminals 2 and 3 at 10 volts, which obtains when the bit 1 is not in either of the register elements I and II, transistor T5 will be conducting due to current flow from ground through its emitter and base and resistors R1 and -R5 to 10 volts. Thus the collector of T5 will be at ground and transistor T6 will be held non-conducting. Consequently, the collector of T6 and hence output terminal 6, will be at -10 volts. Now when the bit 1 is in either element 1 or II, one or the other of the output terminals 2 and 3 will be at ground potential, and current will then flow through either diode CR1 or CR2 and resistor R5 to -10 volts. This will cause the base of transistor T5 to rise to a potential rendering the latter non-conducting. Consequently, the collector of T5 is shifted to below ground potential, thus causing emitter base current flow in transistor T6 to effect conduction of the latter. When T6 becomes conducting, the potential of its collector, and hence output terminal 6, shifts from 10 volts to ground.

It will be seen that the portion of the circuit just described between terminals 2 and 3 of register elements I and II and output terminal 6 comprises a transistor amplifier-inverter circuit with a two leg OR input gate. A similar circuit designated by the rectangle 7 is connected between output gates 4 and 5 of register elements -IV and V and an output terminal 8. When bit 1 is in either of the elements IV and V terminal 8 will be at ground potential. It will be observed that when bit 1 is in the center element II'I no output voltage will be provided.

The manner in which the bit 1 is shifted between elements I to V will now be described. Assume initially that it is in element II, which means that transistor T4, will be conducting, and T3, will be non-conducting. Transistors T1 and T7 and those corresponding thereto in elements III and IV will be conducting, and transistors T2 and T8 and those corresponding thereto in elements III and IV will be non-conducting. Now let it be assumed that the first or transfer pulse of a sequenced pair of negative going pulses is impressed at input terminal 9. The lower plate of capacitor C1 will then be at 10 volts and current will flow 'from ground through the emittercollector circuit of T4, resistor R12 and capacitor C1 to charge the latter. When terminal 9 thereafter goes positive at the end of the transfer pulse the upper plate of C1 suddenly goes sharply above ground potential and a positive transient pulse is impressed on the base of transistor T1 to turn the latter off. Consequently, transistor T2 is rendered conducting to shift output terminal 2 to ground potential.

When input terminal 10 is subjected to the second or clear pulse of the aforementioned sequenced pair of negative going pulses, current will flow through the emitter and base of collector of transistor T3 and resistor R14 and this results in conduction of T3 with the consequent result that T4 will be rendered non-conducting. The same action will occur in transistor T7 of element V and the corresponding transistors of elements III and IV, but as these transistors are already conducting, no change will occur in those elements. The discharge potential of capacitor C1 remains sufficiently high during the interval of the clear pulse that the latter is over-ridden and cannot render T1 conducting.

With bit 1 in register I, let it be assumed that the trans-fer pulse of the next negative going pair of pulses is again impressed at input terminal 9. As the collector of T2 is then at ground, current will flow therefrom through diode CR3 and capacitor C1 to terminal 9, etc. to 10 volts changing C1 to ground potential. The following transfer pulse at terminal 9 causes a high transient potential on the upper plate through CR4 of capacitor C1 which maintains T1 non-conducting, and thus T2 conducting. Thus bit 1 when a succession of pairs of transfer and clear pulses is impressed at terminals 9 and 10, stays in element I.

Assume that bit 1 is in element I, and that the transfer pulse of an aforementioned pair of pulses is impressed on terminal 11. Current will then flow from the collector of T2 through resistor R17, capacitor C2 to change the upper plate of the latter to ground potential. When the last mentioned negative pulse goes positive the upper plate of capacitor C2 is subjected to a transient and suddenly goes above ground potential thereby raising the potential on the base of transistor T3 through diode CR5 to a value rendering it non-conducting. When T3 is made non-conducting T4 is thereby rendered conducting so that bit 1 is thus shifted from element I to element II. The clear pulse of the last mentioned pair of pulses, which is impressed at terminal 10, causes current flow through the emitter-collector circuit of transistor T1 and resistor 11 to render the latter transistor conducting and its companion transistor T2 non-conducting.

If the transfer pulse of the next pair of pulses is impressed on terminal 11, bit 1 will be shifted from element II to element III. So long as no intervening pairs of negative going pulses are impressed at terminals 9 and 10, between pairs of pulses impressed on terminals 11 and 10, bit 1 will continue to shift from left to right successively until it is stored in element V. However, an intervening pair of pulses impressed at terminals 9 and will cause bit 1 to be shifted from right to left, say :from IV to III.

From the foregoing it will be seen that the voltage at output terminal 6 will be 10 volts except when the bit is in either of the elements I and II and will then be at ground or 0 volts. The voltage at terminal 8 will [likewise be at 10 volts except when the bit is in the elements IV and V and will then be at 0 "volts. When the bit circulates back and forth between elements I and II, or between IV and V, the voltage at terminal 6 or terminal 8 will be continuous at 0 volts as the case may be.

The paired transfer and clear pulses that are impressed on terminals 9 and 10, and 11 and 10 are preferably of 100 micro-secs. and 4 micro-secs. duration, respectively. Preferably the clear pulse should start going negative at the instant the transfer pulse goes positive at the end thereof. The pulser circuits of the type disclosed and claimed in the Kintner application Serial No. 288,829, filed June 18, 1963, now Patent No. 3,230,394 issued January 18, 1966 are well suited to provide such paired transfer and clear pulses.

If desired additional register elements can be interposed between center element IIII and elements 11 and IV. These can be optionally provided with output terminals, :like those for elements I, II and IV and V, or without output terminals. If they are provided with output terminals their connections would appropriately be made to the two 0R logic circuits as shown for elements I, II, IV and V.

I claim:

1. A single bit reversible shift register having a plurality of register elements each comprising transistor flip-flop pairs each of which consists of two cross coupled transistors biased for conventional fiip-flop operation with the corresponding transistor of each pair when conducting being indicative of storage of the information bit in that element, means in circuit with one transistor of each pair which when subjected to a sequenced pair of input pulses shifts the information bit between elements in one direction, means in circuit with said one transistor of each pair which when subjected to a sequenced pair of input pulses shifts the information bit between elements in the opposite direction, means providing an output voltage whenever the information bit is in one or the other endrnost register element or the register elements respectively immediately adjacent thereto, and means included in at least one register element intermediate the sets of aforementioned endmost and adjacent register elements wherein no output voltage is provided.

2. The combination according to claim 1, wherein means are provided in circuit with said endmost register elements to hold the information bit when in either of them until such register elements are subjected to a sequenced pair of input pulses that will shift it to another register element in the direction toward the opposite endmost register element.

3. The combination according to claim 1, wherein all register elements have a single control gate in circuit with said one of said transistors of each pair and all but those of said endmost register elements have three pulse triggered inputs and those of said endmost elements have two pulse triggered inputs, wherein corresponding inputs of the register elements are connected in parallel, and wherein said endmost register elements have the information bit register transistor in circuit with one of its inputs and the opposite input of the register element adjacent thereto to insure the last mentioned transistor remains conducting until the opposite input of control gate of the adjacent register element is triggered.

4. The combination according to claim 3, wherein the information bit register transistor of each endmost register element and the register element respectively adjacent thereto are connected to the inputs of an OR logic circuit so the latter provides a continuous output so long as the information 'bit is in either of such storage elements.

5. The combination according to claim 1, wherein the plurality of register elements is an odd whole number equal to or greater than five.

References Cited by the Examiner UNITED STATES PATENTS 2,819,840 1/1958 Huntley et al. 328-37 3,140,472 7/1964 Adam et a]. 307-885 References Cited by the Applicant UNITED STATES PATENTS 3,176,208 3/ 1965 Gifft.

ARTHUR GAUSS, Primary Examiner.

J. HEYMAN, Assistant Examiner.

Claims (1)

1. A SINGLE BIT REVERSIBLE SHIFT REGISTER HAVING A PLURALITY OF REGISTER ELEMENTS EACH COMPRISING TRANSISTOR FLIP-FLOP PAIRS OF EACH WHICH CONSIST OF TWO CROSS COUPLED TRANSISTORS BIASED FOR CONVENTIONAL FLIP-FLOP OPERATION WITH THE CORRESPONDING TRANSISTOR OF EACH PAIR WHEN CONDUCTING BEING INDICATIVE OF STORAGE OF THE INFORMATION BIT IN THAT ELEMENT, MEANS IN CIRCUIT WITH ONE TRANSISTOR OF EACH PAIR WHICH WHEN SUBJECTED TO A SEQUENCED PAIR OF INPUT PULSES SHIFTS THE INFORMATION BIT BETWEEN ELEMENTS IN ONE DIRECTION, MEANS IN CIRCUIT WITH SAID ONE TRANSISTOR OF EACH PAIR WHICH WHEN SUBJECTED TO A SEQUENCED PAIR OF INPUT PULSES SHIFTS THE INFORMATION BIT BETWEEN ELEMENTS IN THE OPPOSITE DIRECTION, MEANS PROVIDING AN OUTPUT VOLTAGE WHENEVER THE INFORMATION BIT IS IN ONE OR THE OTHER ENDMOST REGISTER ELEMENT OR THE REGISTER ELEMENTS RESPECTIVELY IMMEDIATELY ADJACENT THERETO, AND MEANS INCLUDED IN AT LEAST ONE REGISTER ELEMENT INTERMEDIATE THE SETS OF AFOREMENTIONED ENDMOST AND ADJACENT REGISTER ELEMENTS WHEREIN NO OUTPUT VOLTAGE IS PROVIDED.

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