US3278726A

US3278726A - Flip-flop and counter

Info

Publication number: US3278726A
Application number: US273504A
Authority: US
Inventors: James C Harris; Robert W Wendelburg
Original assignee: Allen Bradley Co LLC
Current assignee: Allen Bradley Co LLC
Priority date: 1963-04-16
Filing date: 1963-04-16
Publication date: 1966-10-11
Anticipated expiration: 1983-10-11

Description

Oct. 11, 1966 J. c. HARRIS ETAL I FLIP-FLOP AND COUNTER Filed April 16, 19s: 5 Sheets-Sheet 1 37 INVENTORS JAMES C. HARRIS ROBERT W.WENDELBURG YVAM W AT TORN EY J. C- HARRIS ETAL FLIP-FLOP AND COUNTER Oct. 11, 1966 5 Sheets-$heet 2 Filed April 16. 1963 .hDaz; W v i E L I E AT TORNEY United States Patent 3,278,726 FLIP-FLOP AND COUNTER James C. Harris and Robert W. Wendelburg, Milwaukee, Wis., assignors to Allen-Bradley Company, Milwaukee, Wis., a corporation of Wisconsin Filed Apr. 16, 1963, Ser. No. 273,504 8 Claims. (Cl. 235-92) The present invention relates to a flip-flop which contains as elements a transformer with a tapped primary Winding and a secondary winding, and a bistable current gate in series with one end of the primary winding and having its control element connected to said secondary winding; and wherein the tap on the primary winding of the transformer is adapted for electrical connection with one pole of a source of input signal, and said bistable current gate and an opposite end of said primary winding are adapted for common electrical connection with another pole of said source of input signal. The present invention also relates to a counter comprised of a plurality of said flip-flops connected in succession.

Flip-flops are extensively used in computer and numerical control equipment as storage devices for bits of information, and as elements of larger components, such as counters, which perform a variety of logic operations. In such. applications it is imperative that the flip-flop be capable of continually repeating its operating cycle with uniformly unvarying accuracy in spite of fluctuating conditions. In short, the flip-flop must be both reliable and stable.

Broadly speaking, a flip-flop may be defined as a bistable device which will assume one or another of two stable conditions depending upon the history of the signal or signals fed into it. In attempting to achieve devices of that description which will perform with the necessary accuracy for computer and numerical control applications, flip-flops are frequently enlarged and increased in complexity by an accretion of new components and circuitry. Yet each additional component or complexity tends to defeat the utility of the device by increasing the criticality of operating conditions and by decreasing the reliability of the flip-flop.

The present invention cuts the Gordian knot by making possible a highly reliable and stable flip-flop, that requires only two basic components, both of which may be well known to the art and engineered over the years to achieve optimum operating characteristics. The two components are a transformer with a tapped primary and a bistable current gate, which in a preferred embodiment is a bistable relay. In the flip-flop of the present invention, the extremities of the primary winding are connected to one pole of a source of input signal, and the tap is connected to an opposite pole of the source of input signal. The transformers secondary winding is connected across a control element of the bistable current gate, which would be the relays coil, and the current gate itself, or the relays contacts are placed in series with one extremity of the primary winding and the pole of the input signal source to which it is connected. The purpose of the opening and closing of the relay contacts is to reverse the polarity of the input signal as seen by the secondary winding, and this reversing of the polarity of the signal in the secondary winding being applied to the control element of the bistable current gate results in unequivocal flipfiop action of the present invention.

By the use of only two components and by the choice of the specific components used, a flip-flop of exceptional reliability and stability is achieved. In addition, when a number of the flip-flops of the present invention are connected together to form the novel counter of the present invention, a counter of greatly enhanced reliability and stability is achieved.

"ice

Accordingly, it is an object of the present invention to provide a highly stable flip-flop.

It is another object of the present invention to provide a highly reliable flip-flop.

It is another object of the present invention to provide a flip-flop having no more than one relay.

It is another object of the present invention to provide a versatile counter requiring a minimum number of components.

It is another object of the present invention to provide an inexpensive, versatile counter having a high degree of reliability and stability.

The foregoing and other objects will appear in the description to follow. In the description, reference is made to the accompanying drawings which form a part hereof and in which there is shown by way of illustration several specific embodiments in which this invention may be practiced. These embodiments will be described in sufiicient detail to enable those skilled in the art to practice this invention, but it is to be understood that other embodiments of the invention may be used and the structural changes may be made in the embodiments described without departing from the scope of the invention. Consequently, the following detailed description is not to be taken in a limiting sense; instead, the scope of the present invention is best defined by the appended claims.

In the drawings:

FIG. 1 is a schematic diagram of a flip-flop embodying the present invention,

FIG. 2 is a schematic diagram of a counter,

FIG. 3 is a diagrammatic representation of the signal in and condition of the relay shown in FIG. 1 as a result of the input signal shown in FIG. 4,

FIG. 4 is a diagrammatic representation of an input signal to a flip-flop such as is shown in FIG. 1,

FIG. 5 is a diagrammatic representation of the function of flip-flop VIII shown in FIG. 2 corresponding to the input-signal of FIG. 9,

FIG. 6 is a diagrammatic representation of the function of flip-flop IV shown in FIG. 2 corresponding to the input signal of FIG. 9,

FIG. 7 is a diagrammatic representation of the function of flip-flop II shown in FIG. 2 corresponding to the input signal of FIG. 9,

FIG. 8 is a diagrammatic representation of the function of flip-flop I shown in FIG. 2 corresponding to the input signal of FIG. 9,

FIG. 9 is a diagrammatic representation of an input signal for the addition function of the counter of FIG. 9,

FIG. 10 is a diagrammatic representation of the function of flip-flop VIII as shown in FIG. 2 corresponding to the input signal of FIG. 14,

FIG. 11 is a diagrammatic representation of the function of flip-flop IV as shown in FIG. 2 corresponding to the input signal of FIG. 14,

FIG. 12 is a diagrammatic representation of the function of flip-flop II as shown in FIG. 2 corresponding to the input signal of FIG. 14,

FIG. 13 is a diagrammatic representation of the function of flip-flop I as shown in FIG. 2 corresponding to the input signal of FIG. 14, and

FIG. 14 is a diagrammatic representation of an input for the subtraction function of the counter of FIG. 2.

Referring now specifically to the drawings, in FIG. 1 input terminals 1 and 2 are provided for connection across an input signal source (not shown). The terminal 1 is connected through a current limiting resistor 3 to an upper portion 4 in the drawing of a primary winding 5 of a transformer 6. A lower portion 7 in the drawing of the primary winding 5 is connected through polarity reversing contacts 8 of a bistable relay 9, which contacts 8 are connected back to the input terminal 1. Hence, the upper portion 4 and the lower portion 7 of the primary winding 5 may be said to be connected to a common point, in spite of the presence of the resistor 3, since it could be eliminated without affecting the circuit by modifying the construction of the upper portion 4 to include the equivalent resistance. In terms of polarity, which is significant here, the upper and

lower portions

4 and 7 are, in any event, connected to a common point. A tap 10 on the primary winding 5 is connected through a common ground with the terminal 2. A secondary winding 11 of the transformer 6 is connected across a relay holding current source 12 and a coil 13 of the bistable relay 9, which are connected in series.

For illustrative purposes a diagrammatic representation of an ideal square wave is shown in FIG. 4 as an input signal appearing across the terminals 1 and 2. FIG. 3 is a diagrammatic representation of pulses which might be induced in the secondary 11 of the transformer 6 by the input signal which is shown in FIG. 4, and the graphs of FIGS. 3 and 4 are vertically aligned so that they share the same time reference represented by the horizontal axis. Referring now specifically to graphs in FIGS. 3 and 4, a leading edge 14 of a first input pulse 15 to the primary winding 5 would induce a negative spike 16 in the secondary winding 11, and a trailing edge 17 of the first input pulse 15 would induce a positive spike 18 in the secondary winding 11. A leading edge 19 of a second input 20 to the primary winding 5 will induce a positive spike 21 in the secondary winding 11, and a trailing edge 22 of the second input pulse 20 will induce a negative spike 23 in the secondary winding 11. The described sequence then repeats itself with a third input pulse 24, a leading edge 25 of which will induce a negative spike 26 in the secondary 11 and a trailing edge 27 of which will induce a positive spike 28 in the secondary winding 11. The sequence will continue in the same manner so long as square wave input pulses are imposed across the primary winding 4 of the transformer 5. Shaded areas 29 and 31) represent times when the contacts 8 of the bistable relay 7 are closed.

The above recited sequence of signals is effected by the flip-flop operating in the manner to be described. In the beginning the polarity reversing contacts 8 are open. Although the holding current source 12 is providing suificient energy to hold the contacts 8 in closed position, the energy provided is not sufiicient to energize the relay 9 and close the contacts 8. The input signal is fed into the input terminal 1, through the current limiting resistor 3, the upper portion 4 of the primary winding 5 of the transformer 6, and the grounded tap 10 to the terminal 2.

The polarity of the primary winding 5 to the secondary winding 11 is such that the leading edge 15 of that first pulse 16 will induce the negative spike 17 opposing the relay holding source 12, and hence the condition of the relay 13 is unchanged. However, as the first pulse 15 collapses, its trailing edge 17 will induce the positive spike 18 in the secondary winding 11. The positive spike 18, added onto the output from the source 12, will be sufficient to energize the relay 9 to close the polarity-reversing contacts 8.

Since the current source 12 provides sufiicient energy to hold the contacts 8 closed, a new path will be offered to the second input pulse 20. The second pulse 20, following the path of least resistance, will pass from the input terminal 1 down through the closed polarity reversing contacts 8 and up through the lower portion 7 of the primary winding 5 to the grounded tap 10 and thence to the grounded return terminal 2. Since the second pulse 20 passes through the primary winding 25 in the opposite direction from the first pulse 15, the leading edge 19 of the second pulse 20 will cause a positive spike 1 to be induced in the secondary winding 11. Since the relay 9 is already in its closed position, the spike 21 can have no effect upon the condition of the relay 9. However, the trailing edge 22 of the second pulse 20 will cause a negative spike 23 to be induced in the secondary 11, and the negative spike 23, opposing the holding current from the source 12, will be sufiicient to deenergize the relay 9 and open the polarity reversing contacts 8. Thus, the flip-flop returns to its original state so that the sequence may be repeated.

It will be apparent that when the polarity reversing contacts 8 are closed, two current paths are presented to the input signal, viz., one through the current limiting resistor 3 and the upper portion 4 of the primary 5 to the tap It and the other through the contacts 8 and the lower portion 7 of the primary 5 to the tap 10. However, the latter path presents the least resistance and due to the step up in the windings from the lower portion 7 of the primary 5 to the secondary 11, the part of the signal passing through the lower portion 7 of the primary dominates, and in the operation of the flip-flop, may be treated as the only signal in the primary 5.

The bistable relay 9 serves as a polarity reversing current gate which has its control element connected so that the gate may be opened or closed by the signal induced across the secondary 11. The polarity of the signal induced across the secondary 11 in conjunction with the condition of the current gate at the time of that signal determines whether the condition of the current gate will be changed by the signal. When the condition of the current gate is changed, the polarity of the signal across the secondary will be reversed, and hence the name, polarity reversing current gate.

In one embodiment of the flip-flop described above, the peak voltage of the input signal was volts, and a 22 volt supply Was used for the relay holding current source 12. The ratio of turns in the primary winding 5 of the upper portion 4 to the lower portion 7 was 5/2, and the ratio of the secondary winding 11 to the primary winding 5 was 5/7. The resistance value of the current limiting resistor 3 was in the order of 360 ohms. The 2/5 ratio of the lower portion 7 of the primary 5 to the secondary 10 provided a voltage step-up sufficient to overcome the signal induced in the secondary 11 by the increment of the input signal passing through the circuit branch including the upper portion 4 of the primary 5, as well as to overcome the source 12 so that the relay 9 would open. It will be apparent that the source 12 could be eliminated from the circuit and its purpose achieved by the addition of permanent latching magnets in functional position relative to the contacts or armature of the bistable relay 9.

FIG. 2 shows a schematic diagram for reversible binary counter made up of four flip-flops I, II, IV and VIII, each of which is substantially the same as the flip-flop shown in FIG. 1. A pair of

add input terminals

31 and 32, at the top of the schematic in FIG. 3, are provided to receive an input signal for the addition function of the counter. One add input terminal 31 is grounded, and the other add input terminal 32 is connected through a current limiting resistor 33 to an upper portion 34 of a primary winding 35 in a transformed 36 in the flip-flop I, and through polarity reversing contacts 37 to a lower portion 38 of the primary 35. A tap 39 on the primary winding 35 is grounded through a protective resistor 40. A secondary winding 41 of the transformer 35 isconnected across a relay holding source 42 and a relay coil 43, of a bistable relay 44 containing the polarity reversing contacts 37.

A point between the polarity reversing contacts 37 and the lower portion 38 of the primary winding 35 in the transformer 36 in flip-flop I is connected through a blocking diode 45' to a current limiting resistor 46 and p0- larity reversing contacts 47 of a bistable relay 48 in the flip-flop II. The current limiting resistor 46 is connected to an upper portion 49 of a primary winding 50 of a transformer 51 in the flip-flop II and the polarity reversing contacts 47 are connected to a lower portion 52 of the primary 50. The lower portion 52 and upper portion 49 of the primary 50 are separated by a tap 53 which is grounded through a protective resistor 54. A secondary 55 of the transformer 51 is connected across a relay holding source 56 and coil 57 of the bistable relay 48.

Flip-flop II is connected to flip-flop IV from a point between the polarity reversing contacts 47 and the lower portion 52 of the primary 50 through a blocking diode 58 to a current limiting resistor 59 and to polarity reversing contacts 60. In the flip-flop IV, the current limiting resistor 59 is connected to an upper portion 61 of a primary winding 62 of a transformer 63, and the polarity reversing contacts 60 are connected to the primary windings 62 lower portion 64. A tap 65 on the primary winding 62 is grounded through a protective resistor 66. A secondary winding 67 of the transformer 63 is connected across a relay holding current source 68 and a coil 69 of a bistable 70 containing the polarity reversing contacts 60.

A current limiting resistor 71 and a set of polarity reversing contacts 72 in the flip-flop VIII are connected to a point between the lower portion 64 of the'primary 62 and the polarity reversing contacts 60 of the flip-flop IV through a blocking diode 73. The current limiting resistor 71 is connected to an upper portion 74 of a primary 75 in a transformer 76, and the polarity reversing contacts 72 are connected to a lower portion 77 of the primary 75. A tap 78 on the primary 75 is grounded through a protective resistor 79. A bistable relay 80, including the polarity reversing contacts 72, has its coil 81 connected between a secondary winding 82 of the transformer 76 and a relay holding source 83, and the secondary winding 82 and source 83 are connected together to complete the circuit.

The above described portion of the reversible counter functions alone to perform the addition operation. Hence, the remainder of the counter to be described exists only to perform the subtraction operation of the counter, and to isolate the addition and subtraction portions of the counter one from another.

A subtract input terminal 84 and grounded terminal 85 are provided to receive a subtract input signal. The terminal 84 is connected respectively through

diodes

86, 87, 88 and 89 to the current limiting

resistors

33, 46, 59 and 71 and the

polarity reversing contacts

37, 47, 60 and 72 of the respective flip-flops I, II, IV and VIII. A reverse biasing circuit for the

diodes

86, 87, 88 and 89 is controlled by reverse biasing contacts 90, 91 and 92 in the

bistable relays

44, 48 and 70, respectively. One side of each of the contacts 90, 91 and 92 is connected directly to the subtract input terminal 84. The other side of each of the contacts 90, 91 and 92 is connected respectively to the

taps

53, 65 and 78 in the

primaries

50, 62 and 75 of the next succeeding flip-flop. In addition, the other side of the contact 90 associated with flip-flop I is connected respectively through

diodes

93 and 94 to the center taps 65 and 78 in the flip-flops IV and VIII.

The operation of the addition function by the counter shown in FIG. 2 is illustrated by FIGS. 5, 6, 7, 8 and 9 in the form of vertically aligned graphs. FIGS. 5 through 8 are representation-s of the signals appearing across the

secondaries

41, 55, 67 and 83 of the flip-flops I, II, IV and VIII, respectively, as the add input pulses illustrated in FIG. 9 appear across the add input terminals 30 and 31. It should be clear that no attempt is made in FIGS. 5 through 9 to reflect proportional amplitudes or accurate wave forms, as these will depend upon the specific components and signals used with a specific embodiment. Rather, the graphs appearing in FIGS. 5 through 9 are mere representations of the functioning of all of the flip-flops I, II, IV and VIII in terms of a common time reference represented by the horizontal axes, so they may be read together as a single graph.

The flip-flops I, II, IV and VIII are given the numerical values of their reference Roman numerals so that by 7 values of the actuated flip-flops.

actuating various combinations of the four flip-flops I, II, IV and VIII the sums of their assigned values might represent any decimal integer from 1 to 15. In other words, the counter registers the sum as a binary number, which may be converted to a decimal number by assigning each flip-flop the value indicated and adding the For example, the energization of flip-flops II and VIII would represent the decimal number 10. Again, the energization of flip-flops I, II and IV would represent the number seven, or the energization of flip-flops I, II, IV and VIII would represent the number fifteen. In the following description of the representations in FIGS. 5 through 7 of the addition operation, the counter will be represented as sequentially adding up a total of eight input signals.

A leading edge 95 of a 1st add input pulse (FIG. 9) will induce a negative spike 96 across the secondary 41 of flip-flop I, and a trailing edge 97 of the 1st input pulse will induce a positive spike 98 across the secondary 41. The positive spike 98 will cause the bistable relay 44 to be energized as indicated by the shaded area 99 (FIG. 8). The counter now registers the sum of one.

A leading edge 100 of a 2nd add input pulse will induce a positive spike 101 across the secondary 41 and a negative spike 102 across the secondary 55 of the flipflop II. Neither the positive spike 101 in the secondary 41 nor the negative spike 102 in the secondary 55 will cause the condition of their

respective relays

44 and 48 to change. However, a trailing edge 103 of the 2nd input pulse will induce a negative spike 104 across the secondary 41, deenergizing the relay 44, and the trailing edge 103 will induce a positive spike 105 across the secondary 55 energizing the relay 48 in flip-flop II as indicated by the shaded area 106 in FIG. 7. Now the counter shows the sum of one plus one equals two.

A leading edge 107 of a 3rd add input pulse will induce onlya negative spike 108 in the secondary 41. The negative spike 108 cannot change the deenergized condition of the relay 44. However, a trailing edge 109 of the 3rd input pulse will induce a positive spike 110 in the secondary 41, energizing the relay 44 as indicated by the shaded area 111. Now the counter shows the sum of two plus one equals three.

A leading edge 112 of a 4th add input pulse will induce a positive spike 113 across the secondary 41, another positive spike 114 across :the secondary 55, and a negative spike 115 across the secondary 67 in flip-flop IV (FIG. 6). The

positive spikes

113 and 114 cannot alter the condition of their respective energized

relays

44 and 48, nor can the negative spike 115 affect the deenergized condition of the relay 70 in flip-flop IV. However, a trailing edge 116 of the 4th input pulse will induce negative spikes 117 and 118 across the

secondaries

41 and 55, respectively, deenergizing their associated

relays

44 and 48. Also, the trailing edge 116 will induce a positive spike 119 across the secondary 67 in the flip-flop IV to energize the relay 70 as indicated by the shaded area 120 in FIG. 6. With only the flip-flop IV actuated, the counter registers four as the sum of three and one.

A leading edge 121 of a 5th input pulse will induce only a negative spike 122 across the secondary 41, having no effect upon the eondtion of its associated, deenergized relay 44. A trailing edge 123, on the other hand, will induce a positive spike 124 in the secondary 41 and energize the relay 44 as indicated by the shaded area 125. Now the counter registers the binary ,number 1010 convertible to '1 plus IV, or five.

A leading edge 126 of a 6th input pulse will induce a positive spike 127 across the secondary 41 and a negative spike 128 across the secondary 55, leaving their associated

relays

44 and 48 uneffected. A trailing edge 129 of the 6th input .pulse induces a negative spike 130 across the secondary 41 to deenengize its relay 44 and a positive spike 131 across the secondary 55 to energize its relay 48 as shown by the shaded area 132 in FIG. 7. Now the counter registers the binary number 0110, convertible to II plus IV, or the sum of five plus one equals six.

A leading edge 133 of a 7th input pulse induces only a negative spike 134 across the secondary 41, leaving the relay 44 unchanged. A trailing edge 135 of the 7th input pulse induces only a positive spike 136 in the secondary 41, but the positive spike 136 energizes the relay 44 as indicated by the shaded area 137 in FIG. 8. Now the counter registers the binary number 1110 or the decimal number seven as the sum of six input pulses plus one.

A leading edge 138 of an 8th input pulse does not change the condition of the counter as it induces positive spikes 139, 140 and 141 across the

secondaries

41, 55 and 67 in the flip-flops I, II and IV, respectively, and a negative spike 142 across the secondary 82 of the flip-flop VIII. However, a trailing edge 143 of the. 8th input pulse induces

negative spikes

144, 145 and 146 across the

secondaries

41, 55 and 67, respectively, deenergizing their associated

relays

44, 48 and 70, and the leading edge 143 induces a positive spike 147 across the secondary 82 to energize the relay 80 in the flip-flop VIII as indicated by a shaded area 148 in FIG. 5. Now the counter registers the binary number 0001 corresponding to the decimal eight as the sum of seven input pulses plus one.

The above sequence could be continued through fifteen input pulses when all of the

relays

44, 48, 70 and 80 would be energized and the counter would register the binary number 11 1 1 equivalent to the decimal number fifteen. The addition of more flip-flops would increase the capacity of the counter, for the next consecutive flipflop would be assigned the value XVI, and the one after that LXV, increasing the capacity of the counter to thirtyone and ninety-six, respectively, and so on in a theoretically unending succession. However, the above description of four flip-flops I, II, IV and VIII counting to eight is sufiicient to illustrate the embodiment of the embodiment of the invention. It may be deduced from the foregoing that to perform the addition function the circuit must be such that for each flip-flop, except flip-flop I, the bistable relay may be energized and deenergized only by the input signal that deenergized the bistable relay of the immediately preceding flip-flop. The operation of the described counter to satisfy that formula is described immediately following.

In the beginning of the addition sequence to be described, the

relays

44, 48, 70 and 80 in the flip-flops I, II, IV and VIII, respectively, are in a deenergized condition to register a sum of zero. The diode 86 and the open contact 37 in the flip-flop I, confine a 1st input pulse to the flip-flop I so that the signal will pass through the current limiting resistors 3, the upper portion 34 of the primary winding 35, the tap 39, the protective resistor 40, and back through ground to terminal 31. Hence, for the reasons set forth in connection with FIGS. 1, 3 and 4, the leading edge 95 of the 1st input pulse causes the negative spike 96 to be induced in the secondary 41, and it has no further effect on the counter. Since the trailing edge 97 of the 1st pulse must have the opposite effect on the secondary 41, it induces the positive spike 98 which adds to the holding source 42 to cause the relay 44 to be energized closing the contacts 37 as is represented by the first shaded area 99 in FIG. 6.

Since the polarity reversing contacts 37 in flip-flop I are closed, a 2nd input pulse passing from the terminal 32 through the contacts 37 will see two paths open to it. One path is through the lower portion 38 of the primary 35, the tap 39, the resistor 40 and back through ground to the terminal 31. The other path is through the blocking diode 45 to the flip-flop II, where it will pass through the current limiting resistor 46, the upper portion 49 of the primary winding 50, the tap 53 and the protective resistor 54 to the grounded terminal 31. Hence, the leading edge 100 of the 2nd input pulse, being of opposite polarity to the leading edge 95 of the 1st pulse, will induce another positive spike 101 in the secondary 41 of flip-flop I and a negative spike 102 in the secondary 55 of the flipflop If, neither of which can change the condition of the

relays

44 and 48 since their polarities are such as to tend to produce the existing conditions. The trailing edge 103 of the 2nd pulse will have the opposite effect, inducing the negative spike 104 in the secondary 41 and a positive spike 105 in the secondary 55 to open the contacts 37 of the relay 44 and close the contacts 47 of the relay 48.

Since the contact 6 in the flip-flop circuit I is open, the 3rd input pulse, like the 1st, is confined to the flip-flop I. The leading edge 107 of the 3rd pulse will cause a negative spike 108 to be induced in the secondary 41, having no effect upon the condition of the already deenergized relay 44. However, the trailing edge 109 of the 3rd input pulse will induce a positive spike 110 in the secondary 41 to add to the output of the holding source 42 and to energize the relay 44, closing the contacts 37.

The 4th input pulse will see three paths, now that both the contacts 37 in flip-flop I and contacts 47 in flip-flop II are closed. (Two other current paths open to the 4th pulse, i.e., through the current limiting resistors 33 and 46, respectively, and upper portions 34 and 49 of primaries 35 and 50, are not considered here since the portion of the signal passing therethrough cannot be permitted to have operative effect on the counter.) One path is through the lower portion 38 of the primary 35 whereby the leading edge 112 will induce the positive spike in the secondary 41. A second path is through the lower portion 52 of the primary 50 to induce the positive pulse 114 in the secondary 55. The third path is through the current limiting resistor 59 and the upper portion 61 of the primary 62 to induce the negative spike 115 in the secondary 67. Since the

spikes

113, 114 and 115 induced by the leading edge 112 of the 4th input pulse are all of polarity tending to produce the already existing condition of the

relays

44, 48 and 70, it has no effect on the counter. The trailing edge 116, havingthe opposite eifect from the leading edge 112, will deenergize the

relays

44 and 48, opening the

contacts

37 and 47, and energize the relay 70 closing its contacts 60.

Since the contact 37 in flip-flop I is now open, the appearance of the 5th input pulse across the add input terminals 30 and 31 can have no effect beyond the flip-flop I. Hence, the leading edge 121 of the 5th input pulse will pass through the upper portion 34 of the primary 35 to induce the negative spike 122 across the secondary 41, leaving the counter unchanged. The trailing edge 123 of the 5th input pulse will therefore induce a positive spike 124 across the secondary 41, energizing the relay 44 and and closing the contacts 37.

The 6th input pulse appearing across the add input terminals 30 and 31 will be able to pass through the primaries 35 and 50 of both flip-flops I and II, since the contacts 37 in flip-flop I are closed. Therefore, the leading edge 126 of the 6th input pulse, passing through the lower portion 38 of the primary 35, will induce the positive spike 127 across the secondary 41 and, passing through the upper portion 49 of the primary 50, will induce a negative spike 128 across the secondary 55 of the flip-flop II, leaving the condition of the two flip-flops I and II unchanged. The trailing edge 129 of the 6th input pulse induces a negative spike 130 across the secondary 41 and a positive spike 131 across the secondary 55, causing the relay 44 in the flipflop I to be deenergized and the relay 48 in the flip-flop II to be energized.

The 7th input pulse cannot get past the open contacts 37 in the flip-flop I, and hence the only effect of its leading edge 133 is to induce a negative spike 134 across the secondary 41. However, the trailing edge 135 of the 7th input pulse will cause a positive spike 136 to be induced across the secondary 41, energizing the relay 44 to close the contacts 37. Now the

contacts

37, 47 and 60 of the

relays

44, 48 and 70, respectively, in flip-flops I, II and IV are holding closed, and the next input pulse will reach all four flip-flops I, II, IV and VIII.

The 8th input pulse passing from the add input terminals 31 will be presented with four paths. First, part of the signal will pass through the lower portion 38 of the primary 35 so its leading edge 138 will induce the positive pulse 139 in the secondary 41. Second, part of the signal will pass through the lower portion 52 of the secondary 50 to induce the positive spike 14 in the secondary 55. Third, part of the signal will pass through the lower portion 64 of the primary 62 to induce the positive spike 141 in the secondary 67. Since the effect of those positive spikes 139, 146 and 141 would be to energize the already energized relays 44, 48 and 70, they will not change the counter. Also, the fourth path through the current limiting resistor 71 and the upper portion 74 of primary 75 will permit the leading edge 138 of the 8th input pulse to induce the negative spike 142 in the secondary 82, tending to deenergize the already deenergized relay 80. Hence, the trailing edge 143 of the 8th input pulse through the same path will have the opposite effect, and will cause the

relays

44, 48 and 70 in flip-flops I, II and IV to be deenergized and the relay 80 in the flip-flop VIII to be energized.

As has been noted, whenever the

polarity reversing contacts

37, 47, 60 or 72 are closed, a signal fed to the flipfiop I, II, IV or VIII will have two paths open to it in each primary 35, 50, 62 and 75, viz., through both the upper portion 34, 49, 61 or 74 and the

lower portion

38, 52, 64 or 77. However, due to the effect of the current limiting resistors 35, 46, 59 and 71,'the largest part of the signal will pass through the

lower portion

38, 52, 64 or 77. Also, due to the 2:5 step ratio of windings from the

lower portions

38, 52, 64 or 77 to their

respective secondaries

41, 55, 67 or 82, the effect of the part of the signal passing through the upper portions 34, 49, 61 or 74, which have a 1:1 ratio with the

secondaries

41, 55, 67 or 82, will be nullified and have no effect on the counter. Also the

diodes

86, 87, 88 and 89 effectively prevent the add input signals from getting into the subtract circuit.

FIGS. 10 through 14 are graphical illustrations of the operation of the counter as it performs its subtraction function. The limitations and purposes of the graphical representation in FIGS. 10 through 14 are the same as was pointed out for FIGS. through 9. For the purpose of illustration, FIGS. through 14 are treated as a continuation of FIGS. 5 through 9. Hence, consider that the condition of the counter is such, at the beginning of the FIGS. 10 through 14, that it will register a total of eight, which is the sum registered by the counter at the end of the 8th pulse in FIGS. 5 through 9, and that the initial subtract input pulse illustrated in FIG. 14 is the 9th successive input pulse fed to the counter, and that it will be imposed across the subtract

input terminals

84 and 85.

Hence, when a leading edge 149 of a 9th input pulse appears across the subtract

input terminals

84 and 85, only the relay 80 in flip-flop VIII is energized so that the counter registers a count of eight. The leading edge 149 of the 9th input pulse will be presented simultaneously to each of the flip-flops I, II, IV and VIII and create

negative spikes

150, 151 and 152 in the

secondaries

41, 55 and 67, respectively, and a positive spike 153 in the secondary 82. The trailing edge 154 of the 9th input pulse will have the opposite effect, inducing a negative spike 155 across the secondary 82 of the flip-flop VIII, deenergizing its relay 8t), and producing

positive spikes

156, 157 and 158 across the

secondaries

41, 55 and 67, energizing their

respective relays

44, 48 and 70 as indicated by the shaded areas 159, 160 and 161 in FIGS. 13, 12 and 11, respectively. The counter now registers the binary number 1110, or the decimal number seven as the difference between eight and one.

The sole effect of a leading edge 162 of a 10th input pulse will be to produce a positive spike 163 across the secondary 41, which positive spike 163 cannot change the condition of the already energized relay 44. However, a trailing edge 164 of the 10th input pulse will cause a negative spike 165 to be induced across the secondary 41, deenergizing the relay 44. Now the counter registers six, the difference between seven a previously registered and one, the 10th input pulse.

The effect of a leading edge 166 of an 11th input pulse will be to induce a negative spike 167 across the secondary 41 and a positive spike 168 across the secondary 55, neither of which can effect the condition of the

relays

44 and 48, respectively, which they reach. However, trailing edge 169 of the 11th input pulse will produce a positive spike 170 in the secondary 41 energizing the relay 44 as indicated by the shaded area 171 in FIG. 13 and a negative spike 172 in the secondary 55 deenergizing the relay 48 in the flip-flop II. Hence, the counter now registers a remainder of five.

A leading edge 173 of a 12th input pulse will only cause a positive spike 174 to be induced across the secondary 41 having no effect upon an energized relay 44 therein. However, a trailing edge 175 of the 12th input pulse will effect a negative spike 176 across the secondary 41, deenergizing the relay 44. Now a remainder of four is registered by the counter.

A leading edge 177 of a 13th impulse will produce

negative spikes

178 and 179 across the

secondaries

41 and 55, respectively, and a positive spike 180 across the secondary 67 of the flip-flop IV. However, the leading edge 177 of the 13th input impulse has no effect upon the condition of the counter. A trailing edge 181 of the 13th input pulse produces positive spikes 182 and 183 across the

secondaries

41 and 55 in the flip-flops I and II, respectively, energizing their

relays

44 and 48, as indicated by

shaded areas

184 and 185 in FIGS. 13 and 14, respectively. The trailing edge 181 of the 13th input pulse will also produce a negative spike 186 across the secondary 67 in the flip-flop IV deenergizing its relay 70. Now the counter shows a difference of three.

A leading edge 187 of a 14th input pulse will induce a positive spike 188 across the secondary 41, and a trailing edge 189 of the 14th input impulse will effect a negative spike 190 in the secondary 41, which will deenergize its relay 44. Now the counter registers a remainder of two.

A leading edge 191 of a 15th input pulse will cause a negative spike 192 to be induced in the secondary 41 and a positive spike 193 to be induced in the secondary 55 having no effect upon the condition of the counter. A trailing edge 194 of the 15th input pulse will then cause a positive spike 195 to be induced in the secondary 41 energizing its relay 44, as indicated by a shaded area 196 in FIG. 13, and a negative spike 197 across the secondary 55, deenergizing its relay 48. The counter now registers one.

Finally, a leading edge 198 of a 16th input pulse causes a positive spike 199 to be induced across the secondary 41, causing no change in the counter, and a trailing edge 200 will cause a negative spike 201 to be induced in the secondary 41 deenergizing its relay 44. Thus, the counter now registers zero.

The above described counter effects the subtraction operation in the manner to be described. When the 9th input pulse appears across the subtract

input terminals

84 and 85 it is assumed that only the relay 80 in the flip-flop VIII is energized, so the counter registers a total of eight. Thus, the leading edge 149 of the 9th pulse passes through the blocking diode 86, resistor 33 and upper portion 34 of the primary 35 to ground through the tap 39, through the blocking diode 87, resistor 46, and upper portion 49 of the primary 50 to ground through the tap 53, through the blocking diode 88, the resistor 59, and the upper portion 61 of the primary 62 to ground through the tap 65, and through the diode 89, the polarity reversing contacts 72 and the lower portion 77 of the primary 75 to ground through the tap 78. Thus, the leading edge 149 induces

negative spikes

150, 151 and 152 in the

secondaries

41, 55 and 67 of flip-flops I, H

and IV, respectively, but they have no effect on the already deenergized relays 44, 48 and 7 0. Since the leading edge 149 passes through the lower portion 77 of the primary 75 in flip-flop VIII, the positive spike 153 is induced in the secondary 82, without changing the condition of the energized relay 80. However, the trailing edge 154 of the 9th input pulses has the opposite effect of the leading edge 149, and it induces the negative spike 155 in the secondary 82 which deenergizes the relay 80, while producing

positive spikes

156, 157 and 158 which add to the output of the

relay holding sources

42, 56 and 68, respectively, to energize the

relays

44, 48 and 70.

The energization of the

relays

44, 48 and 70 closes the three respective pairs of

contacts

37 and 90, 47 and 91, and 6t and 92. The 10th input pulse passes from the terminal 84, through the blocking diode 86 and the lower portion 38 of the primary 35 to ground through the tap 39. However, the 10th input pulse also passes through the

closed bias contacts

90, 91 and 92, and 93 and 94, through the

taps

53, 65 and 78 and the

lower portions

52, 64 and 177 of the

respective primaries

50, 62 and 75 to the blocking

diodes

87, 88 and 89. The effect of the signal through the bias contacts 90, 91 and 92 is to bias the blocking

diodes

87, 88 and 89 in reverse, barring the 10th input pulse from reaching flip-flops II, IV and VIII. Hence, the effect of the leading edge 162 of the 10th input pulse is to induce a positive spike 163 in the secondary 41 of the transformer 36 which does not affect the already energized relay 44. However, as the 10th input pulse terminates and its magnetic field collapses as negative spike 165 is induced in the secondary 41 and this opposes the holding source 42 sufficiently to permit the relay 44 to deenergize. Thus, the polarity reversing contacts 37 and the biasing contacts 90 are now open.

The 11th input pulse sees two paths available to it. The first path is through the diode 86, the current limiting resistor 33, the upper portion 34 of the primary 35 to the tap 39 and thence through the protective resistor 48 to ground and the terminal 85. The second path is through the diode 87, the closed polarity reversing contacts 47, the lower portion 52 of the primary 58 and back through the tap 53, protective resistor 54 and ground to the terminal 85. Since the

bistable relays

48 and 78 in the flip-flops II and IV are closed, the

diodes

88 and 89 are reversely biased, and hence will not pass the 11th input pulse. As a result, the leading edge 166 of the 11th input pulse in the upper portion 34 of the primary 35 and the lower portion 52 of the primary 50 causes a build-up of magnetic fields such as will induce a negative spike 167 in the secondary 41 and a positive spike 168 in the secondary 55, and the collapse of those fields caused by the trailing edge 169 induces a positive spike 170 in the primary 41 energizing the relay 44 and a negative spike 172 deenergizing the relay 48.

The 12th input pulse is presented with the same path as was the 10th and for the same reasons as set forth above in connection therewith. Since the 12th input pulse leaves the relay 44 deenergized along with the relay 48, the biasing

contacts

98 and 91 are now open.

Hence, the 13th input pulse has three paths available to it. First, part of the 13th pulse will pass through the diode 86 and the upper portion 34 of the primary 35. Second, part of the 13th pulse will pass through the diode 87 and the upper portion 49 of the primary 50, and third, a part of the 13th pulse will pass through the lower portion 64 of the primary 62. For reasons already explained this situation will cause the leading edge 177 of the 13th input pulse to build up magnetic fields in such directions as to cause

negative spikes

178 and 179 in the

secondaries

41 and 55 and a positive spike 180 in the secondary 67, all of which would tend to produce the existing condition in the respective

bistable relays

44, 48 and 78, respectively. The trailing edge 181 of the 13th pulse causing the collapse of the magnetic fields has the opposite effect and changes the condition of the relays 12 44 and 48 to be energized and of the relay 70 to be deenergized,

The current path available to the 14th input pulse is the same as that of the 10th and 12th input pulses for the same reasons and producing the same results. Similarly, the 15th input pulse follows the same path as the 11th input pulse, since at the time of both pulses the relay 48 is energized, closing the biasing contact 91 to prevent the 11th and 15th pulses from entering other than the flip-flops I and II. The 16th input pulse is confined to the flip-flop I, same as the 10th, 12th and 14th pulses, and results in the deenergization of the relay 44, leaving the counter registering zero.

In the embodiment shown in FIG. 2, the

polarity reversing contacts

37, 47, 60 and 70 perform as bistable reversing current gates, and the

coils

43, 57, 69 and 81 function as control elements to which signals are fed from the

respective secondaries

41, 55, 67 and 82 to control the

current gates

37, 47, 60 and 72. Also, the biasing contacts 90, 91 and 92 act as bistable biasing current gates controlled by control elements in the form of the

coils

43, 57 and 59 connected to the

secondaries

41, 55 and 67. Both the polarity reversing and the biasing current gates function such that if they are closed and a positive signal is fed to their control elements, nothing happens; if they are closed and a negative signal is fed to the control elements, they open; if they are open and a positive signal is fed to the control elements, they close; if they are open and a negative signal is fed to the control elements, nothing happens; and they are stable in both the open and closed positions. Also, the

diodes

86, 87, 88, 89, 93 and 94 serve as signal valves, permitting only the desired signals to pass through, and relay contacts or other devices could be substituted therefor. Hence, as an operating formula has been stated for the addition function, so the subtraction function of the counter may be formalized as a requirement that a subtract input pulse be permitted to reach any flip-flop after flip-flop I only if each and every preceding flip-flop is in a deenergized or zero condition as distinguished from an energized or on condition.

In one specific embodiment of the counter illustrated in FIG. 2, the amplitude of both the add input signals and the subtract input signals was a positive fifty volts. The current limiting resistors 3 were 360 ohm resistors, and the protective resistors 32 were ohm resistors. Due to the added power of the input signals required to operate all four flip-flops, it was found advantageous to insert the additional protective resistor 32 to provide for the situation where the entire input signal is fed to only one or two flip-flops. The other parameters were the same as those of the corresponding components described in connection with the flip-flop illustrated in FIG. 1. Of course, substitutions of elements and modifications of parameter may be made without departing from the scope of the invention. Also, minor modifications of circuitry may convert it to a binary-coded decimal counter. The foregoing and similar substitutions are deemed to be within the scope of the present invention, which may be defined as in the following claims.

We claim:

1. In a flip flop, the combination comprising:

a transformer having a primary winding with an upper portion and a lower portion connected to a common point, a tap between said upper portion and said lower portion, and a secondary winding;

a bistable relay having a coil connected to said secondary winding, and a set of contacts connected between said lower portion of the primary winding and said common point;

and a pair of terminals adapted for connection across a source of input signal, one of said pair of terminals being connected to said common point and the other of said pair of terminals being connected to said tap.

2. In a flip-fl-op, the combination comprising:

a transformer having a primary winding with both an upper portion and a lower portion connected to a common point adapted for connection :to a source of input signal, a tap separating said upper and lower portions and adapted for connection to said source of input signal, and a secondary winding;

a bistable reversing current gate having a control elernent connected to said secondary winding, and being connected in series between one of said upper and lower portions of the primary winding and said common point.

3. A flip-flop according to claim 2 wherein said upper portion of the primary has more turns than said lower portion, and said bistable current gate is in series between said lower portion of said primary and said common point.

4. A flip-flop according to claim 2 wherein a current limiting resistor is connected in series between said upper portion of the primary winding and said common point; and said bistable current gate is connected in series between said lower portion of the primary and said common point.

5. A flip-flop according to claim 4 wherein said upper portion of the primary winding has more turns than said lower portion of the primary winding.

6. In a counter, the combination comprising:

a plurality of sucessive flip-flops, each tflip-tflop according to claim 2;

a pair of terminals adapted to receive an input signal;

a first of said successive flip-tflops having said common point connecting the upper and lower portions of its primary winding connected to one of said pair of terminals and said tap on the primary winding being connected to the other of said terminals;

each successive flip-flop after said first flip-flop having its common point connecting its upper and lower portions of its primary winding connected to an immediately preceding flip flop at a point between said polarity reversing current gate and the portion of the primary winding immediately adjacent thereto in an immediately preceding flip-flop.

7. In a counter, the combination comprising:

a plurality of fiip flops, each flip-flop as set forth in claim 2 connected in successions;

a pair of terminals adapted for connection to a source of input signal;

each of said flip-fiops having said common point connecting said portions of the primary winding in its transformer connected to one of said terminals and 14 said tap on its primary connected to the other of said pair of terminals;

a biasing current gate having its control element connected to the secondary winding of the transformer in at least each of said flip-flops except a last flip-flop of said succession, one side of said biasing current gate being connected to said one of the pair of terminals, and the other side of said biasing current gate being connected to said tap on the primary windglg of the transformer in all of the succeeding flipops.

8. In a counter, the combination comprising:

a pair of add input terminals adapted for connection across a source of input signal;

a pair of subtract input terminals adapted for connection across a source of input signal;

a plurality of flip-flops according to claim 2 connected in succession;

a first of said succession of flip-flops having said common point to which both portions of the primary winding of its transformer are connected to one of said pair of add input terminals and adapted for connection to one of said pair of subtract input terminals, and said :tap on its primary winding connected to the other of said pair of add input terminals and the other of said subtract input signals;

each succeeding flip fiop after said [first flip-flop having its common point of connection for both portions of its primary connected to an immediately preceding flip-flop at a point between said polarity reversing current gate and the portion of said primary adjacent thereto; and adapted for connection to said one of the pair of subtract input terminals so that a conducting path for an add input signal will not exist through said one of the pair of subtract input signals, and said tap on the primary winding connected to the other of said pair of add input terminals and the other of said subtract input terminals;

a biasing current gate having its control element to the secondary winding of the transformer in at least each of said flip-flops except a last flip-(flop, and being connected between said one subtract input terminal and the taps on the primary windings of the transformers in all the succeeding flip-flops.

No references cited.

MAYNARD R. WILBUR, Primary Examiner.

I. MILLER, Assistant Examiner.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 ,278 726 October 11, 1966 James C. Harris et a1.

It is hereby certified that error a pears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 2, line 21, for "the", first occurrence, read that column 3, line 29, after "input" insert pulse line 73, for "vdge" read edge column 4, line 59, for "transformed" read transformer column 6, line 62, for

"condtion" read condition column 7 line 36 f-rr-st-eeeua tenc.e strike out "the embodiment of': column 12 line 16, before "reversing" insert polarity column 14, line 17, before "according" insert each flip-flop Signed and sealed this 29th day of August 1967.

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents

Claims

1. IN A FLIP-FLOP, THE COMBINATION COMPRISING: A TRANSFORMER HAVING A PRIMARY WINDING WITH AN UPPER PORTION AND A LOWER PORTION CONNECTED TO A COMMON POINT, A TAP BETWEEN SAID UPPER PORTION AND SAID LOWER PORTION, AND A SECONDARY WINDING; A BISTABLE RELAY HAVING A COIL CONNECTED TO SAID SECONDARY WINDING, AND A SET OF CONTACTS CONNECTED BETWEEN SAID LOWER PORTION OF THE PRIMARY WINDING AND SAID COMMON POINT; AND A PAIR OF TERMINALS ADAPTED FOR CONNECTION ACROSS A SOURCE OF INPUT SIGNAL, ONE OF SAID PAIR OF TERMINALS BEING CONNECTED TO SAID COMMON POINT AND THE OTHER OF SAID PAIR OF TERMINALS BEING CONNECTED TO SAID TAP.