US3242322A - Error checking apparatus for data processing system - Google Patents
Error checking apparatus for data processing system Download PDFInfo
- Publication number
- US3242322A US3242322A US8876A US887660A US3242322A US 3242322 A US3242322 A US 3242322A US 8876 A US8876 A US 8876A US 887660 A US887660 A US 887660A US 3242322 A US3242322 A US 3242322A
- Authority
- US
- United States
- Prior art keywords
- data words
- binary
- binary digits
- coded
- arithmetic operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Description
March 22, 1966 I Filed Feb. 15, 1960 READER H. L. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM 252 Sheets-Sheet l P-BUFFER CONT/FOL TYPE- WR/ TE? O/AFACTER SORTEK 5AM? /Z0 1 50x75? C0/V77?0L MEMORY (/N/T CENTRAL MULT/PLEX PIP/N72? P19065550? Bill-Ff? Z 7 1! m 5 CONTROL cox/r201. arm/501.5 u/v/r l i 15 19 L 1 TAPE TAPE I HANDLER HANDLE? I l 1 1 #2 l l L..-
INVENTOR.
HEP/Ry 1.. nseow ATTORNL'K March 22, 1966 H. HEROLD ERROR CHECKING APPARATUS FOR DATA PRCCESSING SYSTEM Filed Feb. 15, 1960 252 Sheets-Sheet 2 Emu W Mb A oxww MEN KN ATTO/P/VEX March 22, 1966 Filed Feb. 15. 1960 H. HEROLD 3,242,322
ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM 252 Sheets-Sheet 5 PAl. 3212K 25k 61 6 R0 J n 76 6g? 401/ a 3, 3K L620 4/175 D-C/A/PUT' 9 ,u
CZUCK PULSE D/P/VEI? INVENTOR. 68 HENRy L. HEROLD //VPU7' BY March 22, 1966 H. 1.. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM Filed Feb. 15. 1960 252 Sheets-Sheet 4.
March 22, 1966 H. 1.. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM 252 Sheets-Sheet '7 Filed Feb. 15. 1960 MNN MQQQYMF H 1 wm NmN NW w s kbo w w Qwew :h
a lSRSQ mww NNN L March 22, 1966 H. L. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM INVEN TOR. HENRY L.- HEROLD l mmRhGMw Q T mkm a REQQMQQ m n 2. .F Nnw March 22, 1966 H. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM Filed Feb. 15, 1960 252 Sheets-Sheet 9 MWN March 22, 1966 H. HEROLD 3,242,322
ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM Filed Feb. 15, 1960 252 Sheets-Sheet l0 INVENTOR. HEP/R) 1.. HEROLD March 22, 1966 H. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM 252 Sheets-Sheet 11 Filed Feb. 15, 1960 lul-ll Qm l 'LIIILI'IL o mum mqw duh INVENTOR. HEr/ky L. HERoLD AI'TO )VEX QNN March 22, 1966 H. HEROLD 3,242,322
ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM Filed Feb. 15, 1960 252 Sheets-Sheet 14.
b? q r W IN V EN TOR.
HENRy HEROLD 252 Sheets-Sheet 16 H.- L. H EROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM A Q s s 3 m 0 MES 2 NQ [Ill 3 QM M waswkibk I 13m C @cw w W QR w r vb}. m v 7 4 E 0 Q. 1. WW J M H g ME 1 w -5 wk 0 Ft m A HWY fi i w N m n I m rllwsw m 9 m m HWUl-T A Smbsfi M 7 1 M? my Ex 2 ANN S W 2 1 m 2 a My N r 13.8 N? N I WW; a 9 [6N3 7 1 w 3: mm; H 1 Rx w N Nfi m MDMW I 9 Ex Q J NW} 1 9 R Si n s NS Qsfi E r PM a mum BQQQ wbwgw Nm N v: I. I \k \NML 1 mm w t 3 Q. r WfliWR g March 22, 1966 Filed Feb. 15, 1960 INVENTOR. Hsme L. HERoLD AT T OKIIEX March 22, 1966 H. L. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM Filed Feb. 15, 1960 252 Sheets-Sheet 16 +ev BY March 22, 1966 Filed Feb. 15, 1960 497 COKE RESET 420) AM- i I: l/VPU C0195 SET $433 6/175 a D //V///B/7' LOG/6 lNPUT' z I H. L. HEROLD ERROR CHECKING APPARATUS FOR DATA PROCESSING SYSTEM 252 Sheets-Sheet 20 IN VEN TOR.
HE Nky L. HEKoLP
Claims (1)
11. IN COMBINATION, A DATA STORAGE UNIT FOR STORING A PLURALITY OF DATA WORDS, EACH OF SAID DATA WORDS COMPRISING A PLURALITY OF CODED NUMBERS, EACH OF SAID CODED NUMBERS BEING REPRESENTED BY A PLURALITY OF BINARY DIGITS, EACH OF SAID BINARY DIGITS BEING ACCORDED A NUMERICAL WEIGHT IN ACCORDANCE WITH THE POSITION THEREOF IN A NUMBER; MEANS FOR ADJUSTING THE BINARY DIGITS OF A PREDETERMINED ONE OF THE CODED NUMBERS OF EACH OF SAID DATA WORDS TO PROVIDE A PREDETERMINED SUM FOR THE NUMERICAL WEIGHTS OF ALL THE BINARY DIGITS OF THE DATA WORD; MEANS FOR ENTERING DATA WORDS HAVING SAID ADJUSTED NUMBERS INTO SAID DATA STORAGE UNIT; MEANS FOR SUBSEQUENTLY EXTRACTING DATA WORDS FROM SAID DATA STORAGE UNIT; MEANS FOR VERIFYING THAT THE SUM OF THE NUMERICAL WEIGHTS OF ALL THE BINARY DIGITS OF SUCH AN EXTRACTED DATA WORD IS EQUAL TO SAID PREDETERMINED SUM; MEANS FOR MODIFYING BINARY DIGITS OF SAID PREDETERMINED CODED NUMBER OF EACH EXTRACTED DATA WORD; A CIRCUIT FOR PERFORMING AN ARITHMETIC OPERATION ON A PAIR OF SAID EXTRACTED DATA WORDS AND FOR PRODUCING THE RESULT WORD OF SAID ARITHMETIC OPERATION COMPRISING A PLURALITY OF BISTABLE RLEMENTS FOR DELIVERING BINARY OUTPUT SIGNALS, EACH OF SAID OUTPUT SIGNALS BEING WEIGHTED TO CORRESPOND TO A RESPECTIVE QUANTITY; MEANS FOR PROVIDING BINARY SIGNALS CORRESPONDING TO THE BINARY DIGITS OF SERIALLY OCCURING CODED NUMBERS OF SAID EXTRACTED DATA WORDS; MEANS RESPONSIVE TO EACH PAIR OF RECEIVED BINARY SIGNALS OF LIKE WEIGHT TO SET SAID PLURALITY OF BISTABLE ELEMENTS TO A CONFIGURATION WHEREIN THE AGGREGATE OF THE WEIGHTS OF SAID OUTPUT SIGNALS CORRESPONDS TO THE RESULT NUMBER OF SAID ARITHMETIC OPERATION ON EACH PAIR OF RECEIVED CODED NUMBERS OF SAID EXTRACTED DATA WORDS; AN ENCODING MEANS RESPONDIVE TO SAID OUTPUT SIGNALS TO PROVIDE A GROUP OF BINARY SIGNALS REPRESENTING AN OUTPUT CODED NUMBER; AND MEANS RESPONSIVE TO THE BINARY DIGITS OF THE OUTPUT CODED NUMBER REPRESENTING THE RESULT OF SAID ARITHMETIC OPERATION ON SAID PREDETERMINED CODED NUMBERS OF SAID EXTRACTED DATA WORDS FOR VERIFYING THE CORRECTNESS OF SAID ARITHMETIC OPERATION.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US8876A US3242322A (en) | 1960-02-15 | 1960-02-15 | Error checking apparatus for data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US8876A US3242322A (en) | 1960-02-15 | 1960-02-15 | Error checking apparatus for data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
US3242322A true US3242322A (en) | 1966-03-22 |
Family
ID=21734204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US8876A Expired - Lifetime US3242322A (en) | 1960-02-15 | 1960-02-15 | Error checking apparatus for data processing system |
Country Status (1)
Country | Link |
---|---|
US (1) | US3242322A (en) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2874902A (en) * | 1954-05-14 | 1959-02-24 | Ncr Co | Digital adding device |
US2888202A (en) * | 1953-11-25 | 1959-05-26 | Hughes Aircraft Co | Multiple input binary adder-subtracters |
US2936116A (en) * | 1952-11-12 | 1960-05-10 | Hnghes Aircraft Company | Electronic digital computer |
US2944248A (en) * | 1955-02-23 | 1960-07-05 | Curtiss Wright Corp | Data transfer device |
US2950464A (en) * | 1958-08-29 | 1960-08-23 | Itt | Error detection systems |
US2981470A (en) * | 1955-06-02 | 1961-04-25 | Char c ba | |
US3040300A (en) * | 1957-03-25 | 1962-06-19 | Ibm | Data selector |
US3098994A (en) * | 1956-10-26 | 1963-07-23 | Itt | Self checking digital computer system |
-
1960
- 1960-02-15 US US8876A patent/US3242322A/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2936116A (en) * | 1952-11-12 | 1960-05-10 | Hnghes Aircraft Company | Electronic digital computer |
US2888202A (en) * | 1953-11-25 | 1959-05-26 | Hughes Aircraft Co | Multiple input binary adder-subtracters |
US2874902A (en) * | 1954-05-14 | 1959-02-24 | Ncr Co | Digital adding device |
US2944248A (en) * | 1955-02-23 | 1960-07-05 | Curtiss Wright Corp | Data transfer device |
US2981470A (en) * | 1955-06-02 | 1961-04-25 | Char c ba | |
US3098994A (en) * | 1956-10-26 | 1963-07-23 | Itt | Self checking digital computer system |
US3040300A (en) * | 1957-03-25 | 1962-06-19 | Ibm | Data selector |
US2950464A (en) * | 1958-08-29 | 1960-08-23 | Itt | Error detection systems |
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