US3229258A

US3229258A - Digital storage system

Info

Publication number: US3229258A
Application number: US125018A
Authority: US
Inventors: Harry L Heibeck; Charles G Wilhelm; William M Oleson
Original assignee: Individual
Current assignee: Individual
Priority date: 1961-07-18
Filing date: 1961-07-18
Publication date: 1966-01-11
Anticipated expiration: 1983-01-11

Description

5 Sheets-Sheet l INVENTORS HAR/PY L Pif/BECK CHARLES 6" Wf/ HELM Jan. 11, 1966 H. L. HEIBECK ETAL DIGITAL STORAGE SYSTEM Filed July 18. 1961 N w@ s ICC.

WILLIAM M OLESON BY Jan. 11, 1966 H, HEIBECK ETAL 3,229,258

DIGITAL STORAGE SYSTEM 3 Sheets-Sheet 2 Filed July 18. 1961 .DaPDO N .mi

llllllllllll \l l lllllllllllllllllllll 556# n mz3 MESSE Sm L Iw .jm Two NQN mw .3m m1 wm N N E 3 mmm m25 ,5.51m mz3 @z3 v Nnmz; M6355 T1. 1. mu mz3 5355 I [i li L t I l i I i (IJ L v# mz3 M5555 lie v T t|| m mmwmm n Kim @t mz3 M @OE 8 A Jm f mbe. \\N maw EN mmh I n m x,m. N mj mw wm 1l .1 333LL1L1 J E mzlorm sbizl INVENTORB HA my L, HE/BECK CHARLES G WILHELM BY WILL/AM M OLESO/V n ATTORNEYS Jan. l1, 1966 H. HElBr-:CK ETAL. 3,229,258

DIGITAL STORAGE SYSTEM Filed July 18, 1961 5 Sheets-Sheet 5 ARE TRP

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COUNTER ATTORNEYS United States Patent O 3,229,258 DIGITAL STORAGE SYSTEM Harry L, Heibeck, El Cajon, and Charles G. Wilhelm and William M. Oleson, San Diego, Calif., assignors to the United States of America as represented by the Secretary of the Navy File-d July 18, 1961, Ser. No. 125,018 2 Claims. (Cl. 340-1725) (Granted under Title 35, U.S. Code (1952), sec. 266) The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor'.

This invention relates to a storage system and more particularly to a digital storage system having a short access time and a high read-out rate.

In burst communication systems transmissions are often so short they last for only milliseconds. It is desirable to transmit as long a message as possible during the transmission burst. Attempts have been made to record the message at a low speed on magnetic tape and then read-out the tape at high speed during the transmission burst. This mode of message storage is unsatisfactory because the mechanical inertia of the tape transport mechanism delays read-out of the stored data.

lt is an object of this invention to provide a binarycoded storage and control system having a short access time and a high read-out rate.

It is another object of this invention to provide a storage system employing parallel read-in of data and serial readout at a much higher rate.

It is an object of this invention to provide a dynamic store for controlling read-in and read-out operations.

It is still another object of this invention to provide a dynamic store with destructive read-out.

A better understanding of the invention will be afforded by the following detailed description considered in connection with the accompanying drawings wherein:

FIG. 1 is a block diagram of the read-in circuitry, the index storage line and the index shift register;

FIG. 2 is a block diagram of the dynamic storage lines and the shift registers;

FlG. 3 is a block diagram of the read-out control circuitry',

FIG. 4 shows schematically modified read-out control apparatus.

FIGS. l-3 depict a complete system in accordance with the invention. The system is a binary-coded digital system and it employs a plurality of dynamic storage lines, one of which is used to store index bits, the others being used to store data bits. The storage lines are fed pulses in parallel from a read-in means and then removed serially at a much higher speed.

The data storage lines, storage lines Nos. 1-5, are identical in component composition. Only the inputs to the lines are different. To avoid redundancy, therefore, only two data storage lines are shown in detail in FIG. 2. The other data storage lines are shown as broken-line blocks. The index storage line 11, shown in FIG. l, differs from the data storage lines.

The index storage line 11 comprises AND gates 12-14, OR gate 16, 561 ps. delay line 17, amplifier 1S, paraphase amplifier 19, and one-microsecond delay lines 21- 28. The AND gates 12-14 as well as the remaining AND gates in the apparatus are coincident circuits of the type that produce a 1, or an asssertion," output pulse only as long as all of the input pulses are ls" or assertions." The output is a or a negation whenever one or more inputs are a "0 or a negation The logical equation of a two-input circuit of this type wherein the inputs are A and B and the output is C is C:A B. OR gate 16 as "ice well as the other OR gates in the apparatus are circuits that produce a "1 pulse output when one or more input pulses are a l or an assertion." They produce a 0 output in the absence of a "1 input. The logical equation for a two-input OR gate wherein the inputs are A and B and the output is C is CIA +B. AND gates and OR gates of a suitable type may be found described and shown in Basic Theory and Application of Transistors, Department of the Army Technical Manual TM 11-690, March 1959, pages 210-219, and A Handbook of Selected Semiconductor Circuits, NAVSHIPS 93484, Bureau of Ships, Department of the Navy, part 7. The long delay line 17 in the index storage and long delay lines in the data storages may be of the magnetostrictive variety, whereas the shorter delays in the storage lines may be of the electrical type. Paraphase amplifier 19 may be any conventional inverter circuit that produces one output signal in phase with the input signal and one output signal degrees out of phase with the input signal. Tubetype paraphase amplifiers are shown and described in Radar Electronic Fundamentals, NAVSHIPS 900,016, June 1944, pages 139-143, available from the Government lrinting Office, Washington 25, D C. The paraphase amplitier may be a transistor amplifier with a transformer output, the transformer having two secondary windings, an assertion winding and a negation winding, said windings being biased to produce a 0" and a l output condition, respectively, with no input pulse. Lead 29 is the input lead to paraphase amplifier 19, lead 31 is the inphase or assertion output lead and lead 32 is the 180- degree out-of-phase or negation output lead. Thus, when a "1 pulse is on lead 29, output TD-0 is a 1" (is "truc) and output TIT-'0 (the negation of 'ID-0) is "0" (is false). In the absence of a l pulse on input lead 29, output TD-U is a "0 ("talse) and output TDA) is a 1 (true).

A l pulse is fed into the index storage line every time a bit is fed to each of the data storage lines. The bits circulating in the index storage line are monitored so as to provide control functions for read-in and read-out operations in the data storage lines. The bit period or duration is one microsecond in all of the storage lines. Initially it is necessary to insert a single l pulse in the index storage line. This is accomplished by depressing momentary, normally open, switch 33 so as to allow a l voltage from voltage source 34 to be applied to one input of non-exclusive OR gate 36. With no l pulse on the input of paraphrase amplifier 37 the assertion output of the amplifier, TXL, is 0" ("'false") and TXI., the negative output. is "l" ("true"). When switch 33 is depressed, a "l" is produced at the output of OR gate 36, TXl. becomes "true and Tll-rl. delayed one microsecond by delay 38, remains true one microsecond before becoming "false. During the one microsecond period when both TXL and 'lXIft1 are ls ("true), a l is produced at the output of AND gate 14 and fed into delay 17 via OR gate 16. Pulses delayed in delay line 17 are amplified by amplifier 18 which may be any conventional amplitier suited to amplify pulses. Amplified pulses emitted from amplifier 18 pass through paraphase amplifier 19 before reaching serially connected delays 21-24 and 25-28. Pulses traveling in the former string of delays are circulated back into delay 17 via either feedback path 39 or feedback path 41 (short line). Function ELL is the negation of function ESL (see FIG. 4 for an illustration of the apparatus producing these functions) and one is true" (a "1") at any given time. Thus, if ESL is true, 1`s can pass through AND gate 12 and OR gate 16 into delay line 17 and if ELL is true" (a "l), 1" pulses can pass through AND gate 13 and OR gate 16 into delay line 17. If a pulse feeds back via the long line path it will circulate the entire loop in 565 as. whereas if it feeds back via the short line it will circulate the loop in 564as. Bits fed into the index storage line continue to circulate until they are eliminated during read-out. The outputs of delays 21-24 are TD-l, TD-Z, TD-3 and 'TD-4, respectively. The outputs of delays 25-28 are TD-l, TD-2, TD-3 and TD-4, respectively, the negations of TD-l, TD-Z, TDeS and TD-4. 1f the storage line only contains one "1 pulse, for example, when it enters paraphase amplifier 19, TD-O becomes true" (a 1) and 'lD-t) becomes false One microsecond later, TD-O becomes false, TD-t) becomes true, TD-l becomes true, TD-l becomes false and so forth. The index storage line is monitored or examined to enable recognition of certain pulse sequence patterns. Recognition of certain pulse sequence patterns initiates control functions tied in with read-in, read-out and other operations.

An index bit, a 1, is fed into the index storage line every time a set of data bits is fed in parallel into the data storage lines, and index bits are always added onto the trailing end of bits already in the storage line. As a result of this action, there are no breaks or gaps between the first index bit and last index bit circulating in the index storage line, that is to say, there are no Os between the first or head 1I and the last or tail "1" in the index storage line. Recognition of certain pulse sequence patterns in the index storage line is brought about by means of AND gates such as AND gates 42-44 shown in FIG. 1. For example, AND gate 42 is employed to recognize a 1 0-0 pulse sequence pattern in the index storage line. The three inputs of AND gate 42 are TD-3, Tl and TD-l. As the end index bit in the index storage line leaves one-microsecond delay 23, TD-3 will be true (a "1"). As there are no index bits (1s") following the bit leaving delay 23, TD-l and 'TD-2 will be false (`s) and the negations of TD-1 and TD-Z, namely TD-l and TD-2, will be true Thus, since 'TD-3, r1D-2 and TD-1 are all true simultaneously, the output of AND gate 42, EOT (End Of Train) will be true (a 1). This "1 pulse is used to enable other AND gates in the apparatus, for example, AND gate 45. In a similar manner AND gate 301, shown in FIG. 3, is used to recognize a pulse sequence pattern in the index storage line. In this case the functions fed to the AND gate are FD-3, TD-Z and TD-O. A 1" output is produced by this AND gate when a 1 0-1 index bit pattern is recognized. AND gate 44, FIG. 1, is used to recognize a 1-*-*0-1 index pulse sequence pattern. Note that only a three-input AND gate is employed. Only three positions (the First, Fourth and Fifth) are examined along the storage line as it is immaterial whether the positions in the pulse pattern shared by the asterisks are Os or 1s.

The data storage lines, storage lines Nos. 1-5 are identical in component composition. They each comprise three AND gates, a non-exclusive OR gate a 564-microsecond delay line, an amplifier and a one-microsecond delay line. They each have a long line feedback path and a short line feedback path. The total circulation time via the former path is 565 us. and circulation time via the latter path is 564 ps. These circulation times agree with those found in the index storage line. Data pulses from the read-in apparatus are fed into the data storage lines in parallel where they continue to circulate until read-out.

Binarycoded information is supplie-d to the dynamic storage lines by means of tape reader 46. Reader 46 may be a conventional punched tape reader capable of handling a 6-bit punched tape 48. One longitudinal row of tape 48 is punched with a continuous string of holes to provide "1 index pulses for the index storage line. The other five spaces of a transverse row across the tape are used for one binary-coded character, a punched hole being a l and the absence of a hole being a Since there are five spaces available for a character, thirty-two different characters can be derived. Driving mechanism 47 moves the tape 48 past sensing mechanism 49 whenever relay contacts 54 and 55 are closed. The tape may be examined by mechanical fcelers which close a circuit and produce a "1 pulse when a hole is sensed, or the tape may be examined by photosensitive detection apparatus which produces a 1 pulse Whenever electromagnetic radiation penetrates a hole and impinges on a photocell. If teletype punched tape is employed, the index pulses can be produced by examining the sprocket holes and only live bit tape need be used. Every time a transverse row of tape 48 is sensed by sensing mechanism 49, an index pulse is produced and function EXL (Enable indeX Load) becomes true (a "1). The outputs from the data channels of the sensing mechanism 49, TD-l to TD-S, become true or false, respectively, depending on the nature of the character sensed. The speed of driving mechanism 47 should be such that sensing mechanism 49 is able to produce 0 and 1 pulses at least 565 its. in duration. The actual length of the pulses fed into the dynamic storage line is controlled by enabling pulse EOT produced by AND gate 42.

Reader 46 reads tape 48 whenever there are less than 561 index bits in the index storage line and stops reading the tape when the index storage line lls to 561 bits. Relay contacts 54 and 55 control the action of the driving mechanism of reader 46. Relay coil S6 is connected to the output of static flip-dop circuit 51. A static Hip-flop circuit of a suitable type may be found described and shown in Basics of Digital Computers by John S. Murphy, published by John F. Rider Publisher, Inc., 1958, pages 2-73 to 2-77. The tube-implemented ip-fiop, as is known, has two tubes with cross-connected grids and anodes. It has two stable conditions, one with one tube conducting and the other tube cut ott, and the second condition with the conduction-nonconduction states of the tubes reversed. If one condition is designated as the set condition and the other condition as the reset condition, then the tube grid to which a 1 pulse is applied to establish the set condition may be designated the set input. Accordingly, the other grid may be designated the reset input. The output of AND gate 43 is connected to the set input of flip-tlop 51 and the output of AND gate 44 is connected to the reset input of the Hip-Hop. When AND gate 43 recognizes a I-O-D-t-t) pulse sequence pattern in the index storage line a l output pulse is produced and the ip-tlop switches from one stable state to another. In doing so coil 56 is energized and contacts 54 and 55 are closed. When AND gate 44 recognizes a 1-*-*-0-1 pulse sequence pattern in the index storage line, that is when TD-4, TD4 and TD-O are all true` (a 1") simultaneously, a 1" output pulse is produced causing ip-op 51 to switch states and switch contacts 54 and 55 are opened so as to rie-energize reader 46. During the period bits are being loaded into the storage lines from reader 46, readout of the stored bits can occur simultaneously because the bits read out are always taken from the leading end of the train of pulses in any one storage line and the bits being loaded are always added to the trailing end of the train of pulses in any one storage line.

As was pointed out above, the initial index pulse (a 1) is loaded into the index storage line via AND gate 14. All the other pulses loaded into the index storage line from reader 46 enter via the same gate. The three inputs of AND gate 45 are EXL (Enable indeX Load), EOT (End Of Train) and ELL (Enable Long Line). EXL becomes true" (a 1) every time reader time reader 46 scans a binary-coded character from tape 48. When the end of the pulse train in the index storage passes the proper l-fis delays, AND gate 42 produces a 1 output pulse making EOT true Assuming ELL to be true also, AND gate 45 produces a 1 output pulse which passes through OR gate 36 to paraphase amplifier 37. The 1 input pulse to amplifier 37 makes TXL true and TXL1 remains true" for one microsecond before TXL passes through one-microsecond delay 38. During the time TXL and TXL-1 are both true (one microsecond) a l output pulse is produced by AND gate 14 and loaded into delay 17 via OR gate 16. Twoleg AND gate 57 insures that only one bit is fed into index storage line 11 for every character read from tape 48. The inputs to AND gate 57 are EXL and TXL. As soon as a "1 pulse is fed to paraphase amplifier 37 from AND gate and OR gate 36, TXL becomes truef EXL and TXL both being lrue. AND gate 57 produces a 1 output pulse and keeps TXL true until EXL becomes "fa|se. Without AND gate 57, EXL true if longer than two loop circulation periods (longer than two times 565 ,its could enable a bit to be loaded into index Storage line ll every time EOT became true Data bits, TD-l to TD-5, read in parallel from reader 46 are loaded into storage line Nos. 1-5, respectively, by means of three-input AND gates. Two of these AND gates, AND

gates

201 and 202, are illustrated in FIG. 2.

These gates have the same enabling inputs as AND gate 45 in FIG. l, namely ELL and EOT. Thus, in storage line No. l a. l pulse is loaded into 564 as. delay 203 whenever TD-l, ELL and EOT are true simultaneously; in storage line No. 5 a 1" pulse is loaded into 564 ps. delay 204 whenever TD-2, ELL and EOT are "true" simultaneously. and so forth in the other three data storage lines. As pointed out above, EOT is true just as the trailing index bit in index storage line 11 enters delay 24. This causes all loaded bits to always be tacked on to the trailing bit in each of the respective dynamic storage lines.

Binarycoded information loaded into the storage lines from reader 46 continues to circulate in the closed loops until it is read out. The stored information may be read out at the same time new information is loaded as the oldest information in the lines is always read-out first.

Information loaded in parallel in the storages is readout serially character by character by means of six registers, the index shift register 75 (FIG. 1) and shift registers Nos. 1-5 (FIG. 2). For any given character that is read out of the storage lines. the bit in storage line No. 1 associated with that character is read out first and the index pulse associated with that character is read out last. The bit length in the storage lines is one microsecond. In the shift registers the bit length is expanded to 565 microseconds. Thus, one character (five data bits and the index bit), or one frame of bits, is read out in six times 565 microseconds or 3.39 milliseconds. The read-out rate in terms of characters is 294.9 characters per second. In accordance with the American Standard Association detinition of telegraph transmission speed wherein a wor is defined as five letters and a space, the read-out speed is or 2949 words per minute. The logic circuitry that controls the read-out of information from the storage lines is illustrated in FIG. 3.

The index shift register (FIG. l) 75 employs two AND gates, an OR gate and a paraphase amplifier whereas the data shift registers, shift registers Nos. 1-5 (FIG. 2), employs three AND gates, an OR gate and a paraphase amplifier. As shift registers Nos. 2-4 bear the same circuit implementation as shift registers Nos. 1 and 5, they are shown as broken-line blocks. Binary function TSR is fed to the first or uppermost AND gate (AND gate 205 in shift register Nos. 5 and AND gate 206 in shift register No. 1) in each shift register. Binary function TSR is fed to the second AND gate (AND gate 207 in shift register No. 5 and AND gate 76 in the index shift register) in each of the registers. Binary function TRP is fed to the third or lowermost AND gate (AND gate 208 in shift register No. 5) in shift registers Nos. 1-5. TR-X, the assertion output of paraphase amplifier 77 (FIG. 1), is

fed to AND gate 207, the second AND gate in shift register No. 5 (FIG. 2). TR-S, the assertion output of paraphase amplifier 209 is fed to the second AND gate in shift register No. 4; TR3, the assertion output of the paraphase amplifier in shift register No. 4 is fed to the second AND gate in shift register No. 3; and so forth. The negation outputs of index shift register and shift registers NOS. l-S ttc Tlt}, Tl'l. TRY-2, TRAS, Tite-l and Tii, respectively.

The output of five-input AND gate 302 (FIG. 3) is ARE (Anticipate Registers Empty). When the index shift register and shift registers Nos. 2-5 are empty of "Vs", TIE- 1 Tft- 5, I. TTS. and the inputs of AND gate 302, are true" and ARE is true" (a 1).

The output of three-leg AND gate 303 (FIG. 3) is HOT (Head Of Train). The inputs of AND gate 303 are TD4), TID-2 and TD-l. They and IIOT are all true" during the one microsecond when the head of the index pulse train is recognized. HOT, when it becomes "true, is used as an enabling function for AND gates 304-306. TSE is the assertion output of paraphase amplifier 321. The output of AND gate 301 and TSE become "true" when TIE, TD-1 and TD become "true. This condition occurs when there is only one 1" pulse left in the index storage line (a 0-1-0 pulse sequence pattern is recognized). Once TSE becomes "true, it remains so until two consecutive "0'5" are recognized in the index storage line. AND gates 322 and. 323 are employed to recognize the 0s. When TIT- and T1053- both become false," TSE becomes false Switch 324 is closed whenever high-speed read-out from the storage lines is desired. Closing switch 324 causes a 1 voltage to be imposed on input 326 of AND gate 325. TS1-ti, the negation output of paraphase amplifier 321, is fed to the other input of the AND gate. When switch 324 is closed and TSE is truef the output of AND gate 325, EDR (Enable Data Read-out), is a "1." Once EDR becomes a 1" it remains so until either becomes a 0 or switch 324 is opened.

AND

gates

304 and 207 and OR gate 308 (FIG. 3) are used to produce ESD (Enable Stored Data). When EDR, ARE and HOT are all ",ls" the output of AND gate 304 is a 1 and the output of OR gate 308, ESD, is a 1." The inputs to two-leg AND gate 307 are ESD and EDR. As soon as EDR becomes a "0 ESD changes to "0, as neither AND gate 307 nor AND gate 304 can produce a l output with EDR being a 0.

The output of four-input AND gate 305 is TRP. When EDR, ARE, ESD and HOT are all "true TRP is true TRP is true for one microsecond every 3.39 milliseconds when data is to be read from the storage lines. As was stated above TRP is fed to the third AND gate in each ot' the data shift registers. See FIG. 2. TRP true enables one bit from each of the data storage lines to be read in parallel into the shift registers. For example, if a "l" pulse is on input line 211 of AND gate 208 when TRP is true (a l), the output of the AND gate will be a 1. When the output of AND gate 208 is a 1, TR-5. the assertion output of paraphase amplifier 209. will be a 1. TR-5 feeds into AND gate 205 along with fl so TR5 will thus remain true as long as TSR is truef TSR is the negation output of paraphase amplifier 78 shown in FIG. l. TSR is the assertion output of the same amplifier and is used in all of the shift registers as the shift-right" pulse. The input leads 82 and 83 to AND gate 79 are connected4 to the outputs of

delay lines

23 and 28, respectively. When a 1" appears on both leads (when a l-0 pulse sequence pattern is recognized) TSR is true" and Fili-SR is falsef TSR remains true for only one niicrosecond every circulation of the index bits in index storage line l1. It becomes "true when the head bit in the index storage line is recognized. is thus true" for 564 /is at a time. TSR is fed to the second AND gate in each f the shift registers whereas TSR is fed to the first AND gate in cach register. TSR enables the bit from a register to be loaded into the succeeding register, and TSR' enables the retention of that bit in the register until it is ready to be shifted. Bits are loaded into the data shift registers in parallel (via the third AND gates in the registers) whenever TRP is "true. Bits fed into the registers are serially shifted from one register to another every time TSR becomes true," because the timing of TSR true, bits in the registers are 565 as in duration rather than one microsecond in duration as they are in the storage lines.

The outputs TR-l and Tit-1 of the end register, shift register No. 1, are fed to the set and reset inputs, respectively, of static flip-flop circuit 212. A 1 output pulse is produced on output lead 213 when TR-l is a l and a "0 output pulse is produced on lead 213 when TR-l is a 0. Thus, bits shifted down through the registers appear one after another on output lead 213. Bits exit at a rate of one every 565 ps.

The index shift register is not directly connected to a storage line as are the five data registers. A l pulse is always loaded into the index shift register whenever TSR and ARE are true regardless of what pulses are circulating in the index storage line. As was pointed out above, ARE is true whenever the index shift register and shift registers Nos. 2-5 are devoid of 1s. This condition occurs after the index bit reaches the end register, shift register No. 1. During read-out, ARE becomes true once every 3.39 milliseconds and an index pulse (a 1) is effectively loaded into the index shift register once every 3.39 milliseconds. The index bit follows the tive data bits as they pass from one register to another and the data bits leave flip-flop 212 before the index bit. Each character leaving the flip-flop comprises tive data bits and an index bit. The read-out rate is thus 294.9 (1/.00339) characters per second. In terms of telegraph transmission speed as dened by the American Standard Association wherein a word comprises ve letters and a space, the speed is 2,949 words per minute. The index bits accompanying the data bits can be used for synchronizing purposes when the data is analyzed.

Each time a set of data bits is read out of the storages, the short lines of all the storages are enabled by ESL being true (a 1). The engagement of the short lines causes the specific data bits that were read out to be erased, and permits compensation for the one-microsecond timing discrepancy which would result from the erasure. ESL (Enable Short Line) is the assertion output of paraphase amplifier 313 and ELL (Enable Long Line) is the negation output of the same amplier. When the four inputs, ESD, EDT, ARE and HOT, of AND gate 306 are all 1"5, the AND gate output is a 1, the output of OR gate 312 is a 1 and ESL is a 1. ESL and TD-3 are the inputs of AND gate 311. Once ESL become true it will remain so until TD-3 becomes false TD-3 becomes false after the end of the index pulse train passes into one-microsecond delay 24.

Each storage line has an AND gate for enabling pulse or bit circulation via the long line and each storage line has an AND gate for enabling pulse circulation via the short line. AND gate 13 is the long-line AND gate in the index storage line and AND gate 12 is the shortline AND gate for the same storage line. The long-line AND gates are enabled when ELL is true (a 1), resulting in a loop delay of 565 as. The short-line AND gates are enabled when ESL, the negation of ELL, is true, resulting in a loop delay of 564 lits. Thus, only one type of line is ever in use at a given time in all six of the dynamic storage iines. At the instant a set of bits is read in parallel from the last one-microsecond delay in each storage line, the long-line path is disabled, and the short-line path is enabled. As a result, each leading pulse that is read out is left without a circulation path and hence, is cancelled. Thereafter, the new leading pulse and the train of pulses following are sent once through the short line so as to arrive at the read-out point in the prescribed interval of 565 as. Idling circulations are made via the long-line path.

FIG. 4 reveals in accordance with the invention a modified apparatus for producing function ARE. The output of signal pulse counter 401 is fed to one-shot multivibrator 405 by means of lead 403. Function or signal TSR is applied to input 402 of pulse counter 401. Counter 401 is a divide-by-live counter so that every time ve TSR l (true) pulses enter input 402, a pulse leaves counter 401 and enters multivibrator 405 via lead 403. The pulses from counter 401 repeatedly trigger one-shot multivibrator 40S. The resistance-capacitance coupling circuit in multivibrator 405 is adjusted so as to cause a 565 ns duration l pulse to be produced every time a trigger pulse enters the multivibrator from counter 401. These pulses leave the multivibrator via output lead 406. The output signal on the lead is designated ARE. When the one-shot res and produces the 565 as. pulse, ARE is a 1. ARE is 0 when the 565 its. pulse expires. The counter circuit and multivibrator circuit are conventional and well known in the electronics art. A one-shot multivibrator of a suitable type is described and shown in Radar Electronic Fundamentals, NAVSHIPS 900,016, June 1944, pages 194-198. available from the U.S. Government Printing Oce, Washington, D.C. A pulse counter of a suitble type is disclosed in pages 233-235 of the same publication.

If the index shift register and AND gate 307 are removed from the apparatus of FIGS. 1-3 and the output of multivibrator 405 is substituted for the output of AND gate 302, an index bit will no longer follow a set (five) of data bits at output 213. Instead, one set of data bits will follow another without pause and the readout rate will increase to approximately 354 characters per second or 3,540 words per minute, in accordance with the ASA definition mentioned above.

It should be appreciated that the number of data storage lines employed may be increased or decreased to handle as many different binary-coded characters as needed. The length of the delay lines in the storages rnay be increased so that additional bits can be stored. Other readers such as a magnetic-tape reader may be used in place of a punched tape reader.

Although there has been described above a storage system in accordance with the invention, it is intended that the specific apparatus shown in FIGS. 1-4 and described in detail above be exemplary only of the manner in which the principles of the present invention may be used to advantage. Accordingly any and all variations, modifications, or equivalent arrangements falling within the scope of the annexed claims should be considered to be a part of the present invention.

What is claimed is:

1. A digital storage system comprising, a dynamic storage line for storing binary-coded index pulses, said line having an input, a plurality of dynamic storage lines for storing binary-coded data pulses, each of said lines for storing data pulses having an input and an output, means connected to said input of said index-pulse storage line for generating index pulses, means including said generating means connected to said inputs of sa-id data-pulse storage line for generating data pulses, means coupled to said index-pulse storage line for controlling the start-stop operation of both said generating means, means connected to said outputs of said data-pulse storage lines for serially removing said data pulses `in said data-pulse storage lines, said index-pulse storage line comprises a non-exclusive OR gate having first, second and third inputs and an output, said third input being adapted for the application of said index pulses, means for delaying pulses, said last mentioned means having an input connected to said OR- gate output and an output, a paraphase amplifier having an input and first and second outputs, first, second, third and fourth delay lines each having an input and an output, said first, second, third and fourth delay lines being serially connected output-to-input in ascending order so as to form a linear chain of delay lines, means for coupling said output of said delaying means to said input of said paraphase amplifier, means for coupling said first output of said paraphase amplifier to said input of said first delay line, fifth, sixth, seventh and eighth delay lines each having an input and an output, said fifth, sixth, seventh, and eighth delay lines being serially connected output-toinput in ascending order so as to forni a linear chain, means for connecting said second output of said paraphase amplifier to said `input of said fifth delay line, a first AND gate having an output connected to said first input of said OR gate and first and second inputs, means for connecting said output of said fourth delay line to said rst input of said first AND gate, means coupled to said second input of said first AND gate for periodically generating enabling pulses, a second AND gate having first and second inputs and an output connected to said second input of said OR gate, means for connecting said output of said third delay line to said first input of said second AND gate, means connected to said second input of said second AND gate for periodically generating enabling pulses, and ten output terminals, one of each of said terminals being connected to said first and second outputs of said paraphase amplifier and to said output of said first through eighth delay lines, said output terminals permitting examination of the pulse sequence pattern existing in said delay lines.

2. A dynamic digital storage line comprising a nonexclusive OR gate having first, second and third inputs and an output, means for delaying pulses, said means having an input connected to said OR-gate output and an output, a paraphase amplifier having an input and first and second outputs, first, second, third and fourth delay lines each having an input and an output, said first, second, third and fourth delay lines being serially connected output-to-input in ascending order so as to form a linear chain, means for coupling said output of said delaying means to said input of said paraphase amplifier, means for coupling said first output of said paraphase amplifier to said input of said first delay line, fth, sixth, seventh and eighth delay lines cach having an input and an output, said fifth, sixth, seventh and eighth delay lines being serially connected output-to-input in ascending order so as to form a linear chain, means for connecting said sec ond output of said paraphase amplifier to said input of said fifth delay line, a first AND gate having an output connected to said first input of said OR gate and rst and second inputs, means for connecting said output of said fourth delay line to said first input of said first AND gate, means coupled to said second input of said first AND gate for periodically generating enabling pulses, a second AND gate having first and second inputs and an output connected to said second input of said OR gate, means for connecting said output of said third delay line to said first input of said second AND gate, means connected to said second input of said second AND gate for periodically generating enabling pulses, said third input of said OR gate being adapted for application of pulses to be stored, and ten output terminals, one of each of said terminals being connected to said first and second outputs of said paraphase amplifier and to said outputs of said first through eighth delay lines, said output terminals permitting examination of the pulse sequence pattern existing in said delay lines.

References Cited by the Examiner UNITED STATES PATENTS 7/1957 Lubkin 23S-92 9/1959 Golden 34(1 1725

Claims

1. A DIGITAL STORAGE SYSTEM COMPRISING, A DYNAMIC STORAGE LINE FOR STORING BINARY-CODED INDEX PULSES, SAID LINE HAVING AN INPUT, A PLURALITY OF DYNAMIC STORAGE LINES FOR STORING BINARY-CODED DATA PULSES, EACH OF SAID LINES FOR STORING DATA PULSES HAVING AN INPUT AND AN OUTPUT, MEANS CONNECTED TO SAID INPUT OF SAID INDEX-PULSE STORAGE LINE FOR GENERATING INDEX PULSES, MEANS INCLUDING SAID GENERATING MEANS CONNECTED TO SAID INPUTS OF SAID DATA-PULSE STORAGE LINE FOR GENERATING DATA PULSES, MEANS COUPLED TO SAID INDEX-PULSE STORAGE LINE FOR CONTROLLING THE START-STOP OPERATION OF BOTH SAID GENERATING MEANS, MEANS CONNECTED TO SAID OUTPUTS OF SAID DATA-PULSE STORAGE LINES FOR SERIALLY REMOVING SAID DATA PULSES IN SAID DATA-PULSE STORAGE LINES, SAID INDEX-PULSE STORAGE LINE COMPRISES A NON-EXCLUSIVE OR GATE HAVING FIRST, SECOND AND THIRD INPUTS AND AN OUTPUT, SAID THIRD INPUT BEING ADAPTED FOR THE APPLICATION OF SAID INDEX PULSES, MEANS FOR DELAYING PULSES, SAID LAST MENTIONED MEANS HAVING AN INPUT CONNECTED TO SAID ORGATE OUTPUT AND AN OUTPUT, A PARAPHASE AMPLIFIER HAVING AN INPUT AND FIRST AND SECOND OUTPUTS, FIRST, SECOND, THIRD AND FOURTH DELAY LINES EACH HAVING AN INPUT AND AN OUTPUT, SAID FIRST, SECOND, THIRD AND FOURTH DELAY LINES BEING SERIALLY CONNECTED OUTPUT-TO-INPUT IN ASCENDING ORDER SO AS TO FORM A LINEAR CHAIN OF DELAY LINES, MEANS FOR COUPLING SAID OUTPUT OF SAID DELAYING MEANS TO SAID INPUT OF SAID PARAPHASE AMPLIFIER, MEANS FOR COUPLING SAID FIRST OUTPUT OF SAID PARAPHASE AMPLIFIER TO SAID INPUT OF SAID FIRST DELAY LINE, FIFTH, SIXTH, SEVENTH AND EIGHT DELAY LINES EACH HAVING AN INPUT AND AN OUTPUT, SAID FIFTH, SIXTH, SEVENTH, AND EIGHT DELAY LINES BEING SERIALLY CONNECTED OUTPUT-TOINPUT IN ASCENDING ORDER SO AS TO FORM A LINEAR CHAIN, MEANS FOR CONNECTING SAID SECOND OUTPUT OF SAID PARAPHASE AMPLIFIER TO SAID INPUT OF SAID FIFTH DELAY LINE, A FIRST AND GATE HAVING AN OUTPUT CONNECTED TO SAID FIRST INPUT OF SAID OR GATE AND FIRST AND SECOND INPUTS, MEANS FOR CONNECTING SAID OUTPUT OF SAID FOURTH DELAY LINE TO SAID FIRST INPUT OF SAID FIRST AND GATE, MEANS COUPLED TO SAID SECOND INPUT OF SAID FIRST AND GATE FOR PERIODICALLY GENERATING ENABLING PULSES, A SECOND AND GATE HAVING FIRST AND SECOND INPUTS AND AN OUTPUT CONNECTED TO SAID SECOND INPUT OF SAID OR GATE, MEANS FOR CONNECTING SAID OUTPUT OF SAID THIRD DELAY LINE TO SAID FIRST INPUT OF SAID SECOND AND GATE, MEANS CONNECTED TO SAID SECOND INPUT OF SAID SECOND AND GATE FOR PRIODICALLY GENERATING ENABLING PULSES, AND TEN OUTPUT TERMINALS, ONE OF EACH OF SAID TERMINALS BEING CONNECTED TO SAID FIRST AND SECOND OUTPUTS OF SAID PARAPHASE AMPLIFIER AND TO SAID OUTPUT OF SAID FIRST THROUGH EIGHTH DELAY LINES, SAID OUTPUT TERMINALS PERMITTING EXAMINATION OF THE PULSE SEQUENCE PATTERN EXISTING IN SAID DELAY LINES.