US3172087A - Transformer matrix system - Google Patents

Transformer matrix system Download PDF

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US3172087A
US3172087A US431164A US43116454A US3172087A US 3172087 A US3172087 A US 3172087A US 431164 A US431164 A US 431164A US 43116454 A US43116454 A US 43116454A US 3172087 A US3172087 A US 3172087A
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matrix
transformer
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Francis R Durgin
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International Business Machines Corp
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H03K17/81Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit

Description

March 2, 1965 F. R. DURGIN TRANSFORMER MATRIX SYSTEM Filed May 20, 1954 5 Sheets-Sheet l FRANCIS R. DURGIN BY WILFORD M.WITTENBERC- ATTORNEY 5 Sheets-Sheet 2 W H 2mm EE; mun n w v v W. RM. R
h wmf m 1I l, [l ,Illlll mm M n w T @S Fw @a @QT @QT @Qn s Q F. R. DURGIN TRANSFORMER MATRIX SYSTEM March 2, 1965 Filed May 20, 1954 March 2, 1965 F. R. DURGIN 3,172,087
TRANsFoRMER MATRIX SYSTEM Filed May zo, 1954 5 sheets-sheet s 6 0% @9 C@ C@ @i9 5 @9 Q@ @9 of@ @9 UNES Q@ @9 o@ @Q 0% @9 3 0% @Q C@ @9 Q@ FIG. 3o
Memx@ INVENTORS FRANCIS R, DURGIN WILFORD M.W|TTENBERG AT TORNEY March 2, 1965 F. R. DURGIN 3,172,087
TRANSFORMER MATRIX SYSTEM Filed May 20, 1954 5 Sheets-Sheet 4 To SENSE AMPLIHER f". fc FIG. 3b
SENSE WINDING 1N V EN S N R. DUR F D M* WITTENBERG ATTORNEY March 2, 1965 F. R. DURGIN 3,172,037
TRANSFORMER MATRIX SYSTEM Filed May 20, 1954 5 sheets-sheet 5 FIG. 4 To n 4th ARRAY rk' kk BY @uw X LINE S 1st ARRAY ATTORNEY United States Patent() 3,172,087 TRANSFRMER MATRIX SYSTEIVI Francis R. Dur-gin, Poughkeepsie, NY., assigner to international Business Machines Corporation, New York, INK., a corporation of New York Filed May 2t), 1954, Ser. No. 431,164 Claims. (Cl. 340-174) The present invention relates to a matrix switching system of the type used extensively in digital computing devices and in other systems where electrical signals representing an instruction are employed to exercise control of multiple electric circuits.
ln a three dimensional array of magnetic cores employed as a memory element in digital computers, it is desirable that an addressing system be capable of selectively providing either a positive or a negative current to a designated address in the array in order to allow storage and read out of information. Heretofore, complex circuitry has been required to allow such addressing.
An object of the present invention is to provide a simplied and more reliable system for addressing any one of a plurality of magnetic memory registers with bi-directional currents for read in and read out purposes.
Another object of the invention is to provide a transformer matrix for selectively energizing any one of a plurality of output conductors with bi-directional currents.
Still another object is to provide a simple, reliable transformer selecting matrix readily adaptable to low cost manufacturing methods.
Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by way of example, the principle of the invention and the best mode which has been contemplated of applying that principle.
ln the drawings:
HG. 1 is a schematic diagram of a magnetic core storage system showing the 'principal components in block form.
FIG. 2 is a wiring diagram of the transformer matrix illustrated in block form in FIG. 1, together with some of its associated terminal equipment.
FlGS. 3a, 3c and 3d illustrate the various windings used in a magnetic storage array, and FIG. 3b is a curve illustrating the hysteresis loop of the magnetic cores involved.
FIG. 4 shows in perspective view a three dimensional magnetic core array.
Reference is made to FlG. 1 wherein an address register 1) shown in block diagram form is connected by six output lines, 11 through 16 inclusive, to a matrix 17 which in turn is connected by leight output lines, 13 through 25 inclusive, to a transformer matrix 26. A matrix having L input lines and l( output lines will be referred to as an L x K matrix for convenience throughout the specification. Matrix 17, for example, will be referred to as a 6 x 8 matrix. The address register 10 is further connected by six additional lines, numbered 313 through 35, to a 6 x 8 matrix 36 which is connected by lines 37 through 44 to the transformer matrix 26. It is seen that the upper half of the output lines of the4 address register 10 supplies signals to matrix 17, whereas the ilowerhalf of the output lines supplies signals to matrix 36. Matrices 17 and 36 are preferably of the same type; for example, if matrix 17y is a crystal matrix, then matrix`36 is also a crystal matrix.
The address register 1t) may be any one of a variety of well-known types such as a vacuum tube register cornposed of Hip-flops, a relay register composed of electromagnetic relays, a magnetic core register, a transistor ice register, etc. Likewise, matrix 17 may be any one of a plurality of well-known types of matrices such as a Vacuum tube matrix, a crystal matrix, a magnetic relay matrix, a transistor matrix, etc.
One suitable circuit illustrating the upper half of address register 10 and matrix 17 in detail is disclosed in an article entitled Rectifier Networks for Multiposition Switching, published in the Proceedings of the I.R.E. in February 1949 on pages 139 through 147. Particular reference is made to FIGS. 3 and 2() of that article. The circuits for the lower half of address register 10 and matrix 36 are preferably a duplication of that used for the upper half of address register 1t) and matrix 17 regardless of the particular type of address register or particular type of matrix selected.
Transformer matrix 26, described more fully hereinafter, is connected by sixty-four output lines to a magnetic memory unit 6G composed of a plurality of magnetic core arrays. Only two lines numbered 50 and 51 on one end of the sixty-four output lines of transformer matrix 26 and two lines numbered 52 and 53 on the opposite end are shown. The magnetic memory unit 60, described in detail hereinbelow, is a three dimensional system of magnetic core arrays forming 4096 magnetic core registers of 33 bits each. The sixty-four output lines from transformer matrix 26 supply energy to the Y coordinate lines of the magnetic memory unit 6G and will be referred to hereafter as Y-drivers for convenience. Address register 1i?, matrix 17, matrix 36 and transformer matrix 26 constitute the driving circuit for selectively energizing any one of the Y coordinate lines of the magnetic memory unit 66.
The X-plane driving circuit for the magnetic memory unit 6d, shown in the lower half of FIG. l, is like the Y-plane driving circuit shown in the upper half of FIG'. l. An address register 61 is connected by the output lines of the upper half thereof `to a 6 x S matrix 62 and by the output lines of the lower half to a 6 x 8 matrix 63. The outputs of matrices 62 and 63 feed into a transformer matrix 65 which is identical to transformer matrix 26, and the outputs of transformer matrix 65 constitute the X-drivers for magnetic memory unit 60. By energizing the address registers 19 and 61 with proper signals any one of 4G96 magnetic registers in the magnetic memory unit 6) can be selected for reading or writing information therein.
In operation, the X-plane driving circuit and the 'if-plane driving circuit perform in similar manner. An address signal from the address register 16 causes various ones of the output lines 11 through 16 and various ones of the output lines 36 through 35 to be energized. Activation of certain ones of the lines 11 through 16 causes matrix 17 to energize only one of lines 13 through 25, and activation of certain ones of the lines 3i) through 35 cause matrix 36 to energize only one of the lines 37 through 44. In other words, the register 1t) can be controlled to selectively energize any one output line of matrix 17 and any one output line of matrix 36. Transformer matrix 26 will, therefore, have only one input line of the group of lines 18 through 25 and only one line of the group of lines 37 through 44 energized, which in turn cause this matrix Ito energize only one of its sixty-four output lines feeding the Y coordinate lines of the magnetic memory unit 69. In a like manner, the X-plane driving circuit selects one of the sixty-four Xcoordinate lines of the magnetic memery unit 6u. By means of this system of addressing the X and Y coordinate lines, any register in the magnetic memory unit 60 can be selected for storage or interrogation. The transformer matrices shown by blocks 26 and 65 in FIG. 1 are illustrated in detail in FIG. 2.
A transformer matrix 71B, illustrated in FIG. 2 as that equipment within the broken line block 71, has its X coordinate lines 80 through 87 connected to the cathodes of vacuum tubes labeled 90 through 97, respectively. The output lines 18 through 25 of matrix 17 (FIG. 1) are connected to the control grids of vacuum tubes 90 through 97, respectively. The transformer matrix 70 has its Y coordinate lines 100 through 105 connected to the anodes of a group of vacuum tubes labeled 110 through 115, respectively. Each of the vacuum tubes 90 through 97 and 110 through 115 are normally biased below cut off by means not shown. For convenience, live pairs of Y lines have been omitted in FIG. 2. Output lines 37-44 of matrix 36 (FIG. l) are connected to correspondingly labeled lines in FIGURE 2, line 37 supplying energy to each grid of vacuum tubes 110 and 111 through a pair of logical AND circuits 120 and 121, respectively, line 38 supplying energy to each grid of vacuum tubes 112 and 113 through .a pair of logical AND circuits 122 and 123, respectively, and line 44 `supplying energy to each grid of vacuum tubes 114 and 115 through a pair of logical AND circuits 124 and 125, respectively. The logical AND circuits 120, 122 and 124 are each connected to a write generator 126 whereas the logical AND circuits 121, 123 and 125 are connected to a read generator 127. Each of the logical AND circuits must receive two input signals simultaneously in order to produce an output signal. Thus, it can be seen that before energy from any one of the lines 37 through 44 can be applied to any one of the grids of the vacuum tubes 110 through 115, it is necessary that either the write generator 126 or the read generator 127 simultaneously supply energy to its respective logical AND circuits.
The Y lines 100 through 105 and the X lines 80 through 87 of lthe transformer matrix 70 of FIG. 2 can be considered as corresponding to Cartesian coordinates which, instead of forming conventional intersections in terms of Cartesian rectangular coordinates, have a series circuit connected between the X and Y lines at the position where such rectangular coordinate intersections would occur. That is to say, the X and Y lines are displaced to cross one another at points where rectangular coordinate intersections would occur and `are interconnected at such crossover points by a circuit consisting of a transformer primary winding and series connected unidirectional conducting device. Thus, the term coordinate intersection, hereinafter referred to with reference to FIG. 2, will define these cross-over points.
A series circuit such as that described and comprising a transformer primary winding 130A and diode 131 is connected between the Y line 100 and X line 80 at the coordinate intersection thereof. Likewise, a series circuit consisting of transformer primary winding 150B and diode 132 is connected between the X line 80 and Y line 101 at their coordinate intersection. Primary windings 130A and 130B are mutually coupled to a common secondary winding 136 which supplies bi-directional currents, depending on which primary winding is energized, to one of the coordinate drive lines of magnetic memory unit 60. A separate secondary winding mutually coupled to a single primary winding may be used, but the arrangement employed reduces the number of secondaries to a minimum. While only the primary windings 130A and 130B together with associated diodes 131, 132 and secondary winding 136 have been labeled and described, it is understood that the remaining circuit components for each unnumbered coordinate intersection are connected and perform in a like manner.
Alternatively, the transformer matrix 70 may be considered to consist of a plurality of banks of transformers. It is to be understood that the term bank as used herein refers to an electrical arrangement rather than a mechanical coniguration oftransformers. The banks of transformers may be designated as horizontal and vertical. One horizontal bank of transformers, for example, is shown between Y lines 100 and 101 With the transformers connected in electrical circuits. One electrical circuit shown in the upper left corner of FIG. 2, for example, includes a first diode 131, a first primary winding 130A, a second primary winding 130B and a second diode 132 serially connected. The first and second primary winding may be respective halves of a center-tapped transformer primary winding. The common point between the two primary windings of this electrical circuit is connected to X line as at point 135, and in a like manner each such common point in the other electrical circuits included between Y lines and 101 is connected to a respective X line. A group of electrical circuits with their Common points between the two primary windings connected to a single X line constitutes a vertical bank of transformers.
Resistors 140-147, connected to X lines 80-87 respectively, serve as cathode return resistors for vacuum tubes 917-97 respectively. Although not essential, these resistors are desirable because they maintain the cathodes of the vacuum tubes 90-97, when in a non-conducting state, at such a value of potential that the bias required on the grids of these tubes to insure non-conduction is smaller than that required where these cathodes are left floating or unconnected. Consequently, smaller input signals may be used on the lines 18-25 for control purposes.
The resistors 140-147 should be large to prevent back currents from giving the transformer matrix a poor Selection Ratio. Back current is defined as current flow in an unselected transformer. Selection Ratio is defined as the ratio of current flow in a selected transformer to the current ow in a non-selected transformer, and should be as high as possible. In order to illustrate current flow in an unselected transformer, consider X line 80 and Y line 102 to be energized. Current now flows in the transformer primary winding 150 and diode 151. In addition, an undesired current llows from ground through the resistor 141, transformer primary winding 152, diode 153 to Y line 102 since this line is lat a value of potential determined by the voltage drop across vacuum tube 112. In a like manner, an undesired current will flow in each of the transformer primary windings and its associated diode connected 4to Y line 102. Since the voltage drop across vacuum tube 112 is relatively small and the resistance value of individual resistors 141 through 147 is large, it follows that the magnitude of individual back currents is relatively small. Although the back currents never approach a value suthcient to select an undesired transformer, they nevertheless represent a power loss, which can be minimized by proper selection of circuit cornponents.
To illustrate the operation of the transformer matrix 70, assume that line 18 is energized with a positive signal, line 37 is energized with a positive signal and the write generator 126 is energized. Vacuum tube 90 then conducts and X line 80 is energized with a positive potential. The AND circuit supplies a positive signal which is applied to the grid of the vacuum tube 110 and overcomes a negative bias normally maintained theeron by a source not shown, and renders this -tube conductive. Energy then flows from X line 80 through the transformer primary winding A and 131 to Y line 100 and thence through the vacuum tube 110 to ground. A voltage pulse of one polarity is thereby induced in the secondary winding 136. The vacuum tube 110 derives its positive plate potential from the X line 80 in this instance. Now assuming that line 18 is energized with a positive signal, line 37 with a positive signal, and the read generator 127 is energized. Vacuum tube 90 remains conductive, but in this case, the logical AND circuit 121 supplies a positive signal to the grid of vacuum tube 111 to render it conductive. The energy ow in this instance is from the X line 80 through the transformer primary winding 130B, crystal diode 132 to Y line 101 and through vacuum tube 111 to ground. The transformer secondary 136 now develops a voltage pulse of opposite polarity. Vacuum tube 111 also receives its positive plate potential from the X line 80. Vacuum tubes 110 through 115 receive positive plate potential from an energized X line in any given case. Thus, it is seen that the secondary winding 136 may be selectively energized with a voltage of one polarity or of the opposite polarity dependent upon energization of the read or write generator. As previously mentioned, the secondaries of one transformer matrix are connected to the X lines of magnetic memory unit 60 of FIG. 1 and the secondaries of another transformer matrix are connected to the Y lines thereof, with the several matrices controlled, as described, in directing bi-directional currents to particular registers of the memory unit 60 for storage or interrogation purposes.
Reference is made to FIGS. 3a, 3b, 3c and 3d for a more detailed illustration and an explanation of the operation of the magnetic memory unit 60 shown in block form in FIG. 1. The memory unit 60 is composed of 33 arrays with each array sixty-four cores wide and sixty-four cores high. For ease of illustration, FIGS. 3a, 3c and 3d are limited in their showing to an array six cores wide and six cores high. A complete core array has the X and Y coordinate lines of FIG. 3a, the Z winding of FIG. 3c and the sense winding of FIG. 3d all wound in a single array. However, each of the various windings of a cornplete array is shown separately in FIGS. 3a, 3c and 3d in order to avoid confustion and facilitate tracing the path each winding follows.
The bistable magnetic cores employed for the purposes of the present invention are interlinked with X and Y input windings, which, when energized, cause the core to be magnetized in one or the other direction. A single X or Y line passing through a core is equivalent to a winding having one turn. An output sense winding associated with the cores develops an induced voltage as a result of the change in tlux occasioned by shifting the magnetic state of the core through pulsing of the X and Y drive windings.
FIG. 3b illustrates an idealized hysteresis loop for commercially obtainable magnetic material. If the state of remanence of a core of such material is that indicated by the point 61, application of a positive magnetomotive force causes it to traverse the hysteresis curve to point c, and, upon relaxation of this positive force, reverts to point a. Application of a negative magnetomotive force, greater than the coercive force, causes the curve to be traversed to point d and, when the force is terminated, traversed to point b. Similarly, with the remanence state of the core standing at point b application of a negative magnetornotive force causes the curve to be traversed to point d, and return to point b when the negative force is relaxed, while a positive force, greater than the coercive force, causes a traversal of the curve from point b to point c and return to point a when the positive force is terminated.
Points a and b are stable remanence states readily adapted for representing binary information and a core may be driven to one or the other of these two states by energizing both its X and Y lines. A change in state is observed through a voltage pulse induced in the output winding as the magnetic field in one direction co1- lapses and builds up in the other direction. With point a arbitrarily selected as representing a binary one state and point b a binary zero state, application of a negative force by pulsing the X and Y drive windings simultaneously causes a voltage to be induced in the output sense winding if a one is stored, while a negligible connected between core arrays as are the X and Y windings. In this arrangement, the cores are driven toone remanence state by coincident currents, individually less than the coercive force, applied to the X and Y windings. The magnitude of either the X or the Y line current alone is insufficient to overcome the coercive force, but applied together, they exceed the coercive force. To prevent a change in the magnetic state of a core, the windings X Aand Y are pulsed in coincidence with energization of the inhibiting winding which is labeled as element Z in FIG. 3c. The inhibiting winding, for convenience called a Z winding, of each array is individually controlled by a Z driver which, although not shown, may be any suitable energizing circuit. The magnetomotive force produced by current in the inhibiting winding opposes the magnetomotive force produced by either the X or Y line current. This prevents the applied total magnetomotive force from reaching the coercive force thereby inhibiting a change in the remanence state of a core. FIG. 3c shows how the Z winding is threaded through the cores in veach array, where, for example, it is desired to oppose the Y line currents. Output signals are obtained on a sense winding shown in FIG. 3d upon reversal of the direction of current flow through the X and Y windings whereupon those cores which have changed remanence states in storing binary ones are returned to their initial state. The transformer secondaries of matrices Z6 and of FIG. 1 supply current pulses to the Y lines and X lines, respectively, of each magnetic core array ot' meinory unit 60. The X and Y lines of each array are interconnected as shown in FIG. 4 with each Y line in a horizontal plane threading all cores of each array in that plane and each X line in a vertical plane threading all cores of each array in that plane. The cores are arranged to form registers for storing binary numbers. The bits of Ione register, composed of the cores in the lower left corner of each array in FIG. 4, are shown in solid black lines and numbered 1400 through 1420, respectively.
In order to illustrate the operation of the system of FIG. 1, assume that the binary number 101 previously has been written into the cores labeled 1400l to 1420 which define aregister whose address is X1,'Y1 in FIG. 4. Core 1400 holds a binary one, core 1410 `a binary zero, and core 1420 a binary one. In other words, cores 1400 and 1420 "are in the state of remanence indicated by point a in FIG. 3b, and core 1410 is in the state of remanence indicated by point b. Since it is desired to read the binary number 101 from the subject register,V this register must have its Y1 line and its X1 line of FIG. 4 energized with coincident negative currents suiiicient in magnitude to change the magnetization of the cores 1400 and 1420 from the point af to the point dl on the curve of FIG. 3b.
The Y1 line and the X1 line are energized by the Y plane driving circuit of FIG. 1 and the X plane driving circuit, respectively, when proper address signals are applied to address registers 10 -and 61respectively. It will be noted that the X and Y lines in FIG. 4 are threaded in a manner to cause a change in direction of current liow through the cores 'of a given register in alternate arrays. The direction of thev resultant magnetomotive force acting on each core, however, is such as to create a flux in the same direction within each core. The sense winding of each array is sampled by sensing means, not shown, during the period when X and Y negative currents are present to deter-mine which ones of the cores undergo a change in magnetization from point a to point "d in FIG. 3b.. Since each sense winding must be electrically separate and distinct from the remaining sense windings, the sense windingv in each core array has its own individual sensing means. Binary ones are indicated by voltages induced in the various sense windings when a change of magnetization within associated cores take place. The induced voltages are supplied to a load device, not shown. A relatively large voltage is induced in the sense winding in the first array and the third array, respectively, when the coincident negative currents are applied because of the resulting change in flux as cores 1400 and 1420 change their magnetization from point af to point d in FiG. 3b. Thus binary ones are indicated. There is negligible change in flux as core 1410 changes its magnetization from point b to point d of FIG. 3b. Consequently, a voltage of negligible magnitude is induced in the sense winding 'of the second array, and a binary zero is indicated.
Assume now, that it is desired to rewrite the binary number 101 into the subject register. It is necessary, therefore, to energize the Y1 line and the X1 line of FIG. 4, with coincident positive currents suiiicient in magnitude to change the magnetization of the cores 1400 and 1420 from the point b to the point c on the curve of FIG. 3b. Coincident positive currents for the Y1 line and the X1 line likewise are supplied by the Y plane driving circuit and the X plane driving circuit of FIG. 1 when proper address signals are applied to address registers and 61, respectively When the coincident positive currents are relaxed all the cores return to the stable state of remanence indicated by point a of FIG. 3b with binary one representations stored in a-ll cores. Since a binary zero is to be stored in core 1410, in the example taken, it is necessary to prevent this core from being magnetized to point c of FIG. 3b. This is done by energizing the Z winding in the second array with a current from the Z driver that is approximately equal to and in opposition with the Y line current. The Z driver must come on simultaneously with or earlier than the X and Y drivers to prevent core 1410 from being magnetized to point c of FIG. 3b. The magnetomotive force applied to core 1410 by the Z winding current neutralizes the magnetoiotive force applied to this core by the Y1 line current.
The total magnetomotive forces applied to core 1410 are thus less than the coercive force, and the core remains in the stable state representing a binary zero as indicated at point b of FIG. 3b. Thus, the binary number 101 is restored.
The normal sequence of operation employed here is to read first then write. This is because binary ones are written, and it is necessary to insure that all cores are in the binary zero state of remanence before writing takes place. The read operation changes all cores in a given register to the binary zero state of remanence. It is equally feasible, however, to write with binary zeros and return all cores to the binary one state by the reading operation.
While there have been shown and described and pointed out the fundamental novel features of the invention as applied to a particular embodiment, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art, without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims.
What is claimed is:
1. In an electronic signal system wherein electric .energy pulses of different character are selectively applied to different ones of a plurality of conductors: a plurality of transformers each having at least one secondary winding connected to one of said conductors and at least first and second primary windings; and, a matrix system for selectively energizing said primary windings said system including first and second pluralities of x-coordinate conductors, irst and second pluralities of y-coordinate conductors, means connecting one end of each of different group of said iirst primary windings to one of said first x-coordinate conductors and the other end of each of said first primary windings to one of said first y-coordinate conductors, and means connecting one end of each of said different groups of said second primary windings to one of said second .vc-coordinate conductors and the other end of each of said second primary windings to one of said second y-coordinate conductors.
2. For selectively applying positive and negative current signals to any one of a plurality of output circuits, a drive circuit including: a transformer for each output circuit, each of said transformers having a secondary winding and first and second primary windings; means connecting said first and second windings, respectively, into first and second matrices of xand y-coordinate conductors; each of said first primary windings being connected between yan x and a y conductor of the first matrix at their intersection and each of said second primary windings being similarly connected between an x and a y conductor of the second matrix; a separate individual switching element connected in series circuit with each individual x and y conductor of each matrix; and, means for selectively actuating a pair of switching elements connected to an x and a y conductor of any selected one of the matrices to allow current to flow through the primary winding at the intersection of those conductors and thereby induce an output signal in the secondary winding of the selected transformer, the first and second primary windings of each transformer being so arranged as to induce currents in opposite senses in the secondary winding.
3. A drive circuit according to claim 2 in which the means for actuating the switching elements include: an xcoordinate selection matrix connected to the x-coordinate switching elements of the first and second matrices, a ycoordinate 'selection matrix connected to the y-coordinate switching elements of the first and second matrices; and, means for selectively applying an actuating signal to the xand y-coordinate switching elements of the first and second matrices.
4. A drive circuit as claimed in claim 3 in which pairs of switching elements consisting of one of the xor ycoordinate switching elements of the first matrix and one of the xor y-coordinate switching elements, respectively, of the second matrix consist of double triodes.
5. A drive circuit according to claim -4 including an isolating diode connected in series with each primary winding between the xand y-coordinate conductors to which it is connected.
References Cited in the tile of this patent UNITED STATES PATENTS 2,540,654 Cohen Feb. 6, 1951 2,613,267 Durkee Oct. 7, 1952 2,691,151 Toulon Oct. 5, 1954 2,708,267 Weidenhammer May 10,1955 2,719,965 Person Oct. 4, 1955 2,734,187 Rajchman Feb. 7, 1956 2,773,444 Whitney Dec. 11, 1956 2,913,706 Thorensen Nov. 17, 1959 2,932,008 Hoberg Apr. 5, 1960 OTHER REFERENCES Publication I, Edvac Progress Report No. 2, June 30, 1946, pp. 4-22, 4-23, PY-o-i64.
Publication II, Proc. of IRE, October 1953, page 1419.
Publication III, an article entitled: Static Magnetic Memory-its Applications to Computers and Controlling Systems, by An Wang, published May 2-3, 1952 in Proc. of Assoc. of Computing Machinery, pp. 207-212, FIG. 2(b), specifically relied upon.

Claims (1)

  1. 2. FOR SELECTIVELY APPLYING POSITIVE AND NEGATIVE CURRENT SIGNALS TO ANY ONE OF A PLURALITY OF OUTPUT CIRCUITS, A DRIVE CIRCUIT INCLUDING: A TRANSFORMER FOR EACH OUTPUT CIRCUIT, EACH OF SAID TRANSFORMERS HAVING A SECONDARY WINDING AND FIRST AND SECOND PRIMARY WINDINGS; MEANS CONNECTING AND FIRST AND SECOND WINDINGS, RESPECTIVELY, INTO FIRST AND SECOND MATRICES OF X- AND Y-COORDINATE CONDUCTORS; EACH OF SAID FIRST PRIMARY WINDINGS BEING CONNECTED BETWEEN AN X AND A Y CONDUCTOR OF THE FIRST MATRIX AT THEIR INTERSECTION AND EACH OF SAID SECOND PRIMARY WINDINGS BEING SIMILARLY CONNECTED BETWEEN AN X AND Y CONDUCTOR OF THE SECOND MATRIX; A SEPARATE INDIVIDUAL SWITCHING ELEMENT CONNECTED IN SERIES CIRCUIT WITH EACH INDIVIDUAL X AND Y CONDUCTOR OF EACH MATRIX; AND, MEANS FOR SELECTIVELY ACTUATING A PAIR OF SWITCHING ELEMENTS CONNECTED TO AN X AND A Y CONDUCTOR OF ANY SELECTED ONE OF THE MATRICES TO ALLOW CURRENT OF FLOW THROUGH THE PRIMARY WINDING AT THE INTERSECTIOIN OF THOSE CONDUCTORS AND THEREBY INDUCE AN OUTPUT SIGNAL IN THE SECONDARY WINDING OF THE SELECTED TRANSFORMER, THE FIRST AND SECOND PRIMARY WINDINS OF EACH TRANSFORMER BEING SO ARRANGED AS TO INDUCE CURRENTS IN OPPOSITE SENSES IN THE SECONDARY WIONDING.
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US431164A US3172087A (en) 1954-05-20 1954-05-20 Transformer matrix system
FR1141398D FR1141398A (en) 1954-05-20 1955-05-12 Transformer matrix system
GB1420155A GB769384A (en) 1954-05-20 1955-05-17 Transformer matrix system

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US3231872A (en) * 1960-12-20 1966-01-25 Ericsson Telefon Ab L M Magnetic memory
US3307148A (en) * 1962-04-16 1967-02-28 Nippon Electric Co Plural matrix decoding circuit
US3351924A (en) * 1964-11-27 1967-11-07 Burroughs Corp Current steering circuit
US3358269A (en) * 1964-04-10 1967-12-12 Bell Telephone Labor Inc Square switch distribution network employing a minimal number of crosspoints
US3360786A (en) * 1963-04-30 1967-12-26 Electro Mechanical Res Inc Magnetic core memory system
US3453607A (en) * 1965-10-24 1969-07-01 Sylvania Electric Prod Digital communications system for reducing the number of memory cycles
US3460092A (en) * 1965-03-31 1969-08-05 Bell Telephone Labor Inc Selector matrix check circuit
US3500358A (en) * 1967-02-02 1970-03-10 Singer General Precision Digit line selection matrix
US3638199A (en) * 1969-12-19 1972-01-25 Ibm Data-processing system with a storage having a plurality of simultaneously accessible locations

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US2992410A (en) * 1956-02-28 1961-07-11 Bell Telephone Labor Inc Selector for switching network
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GB885775A (en) * 1957-07-23 1961-12-28 Ericsson Telephones Ltd Improvements in and relating to electrical translators
GB842928A (en) * 1957-07-24 1960-07-27 Ericsson Telephones Ltd Improvements in and relating to electrical code translators
US3114134A (en) * 1957-07-26 1963-12-10 Ibm Switching circuit
US3058096A (en) * 1957-08-23 1962-10-09 Sylvania Electric Prod Memory drive
US3159821A (en) * 1957-09-25 1964-12-01 Sperry Rand Corp Magnetic core matrix
US3110015A (en) * 1957-10-28 1963-11-05 Honeywell Regulator Co Memory circuitry for digital data
NL234723A (en) * 1958-01-02
NL237700A (en) * 1958-04-02
US3084335A (en) * 1958-10-16 1963-04-02 Rca Corp Readout circuit for parametric oscillator
US3109161A (en) * 1958-12-03 1963-10-29 Bell Telephone Labor Inc Electrical selection circuits
US3214740A (en) * 1959-01-16 1965-10-26 Rese Engineering Inc Memory device and method of making same
US3155943A (en) * 1959-03-09 1964-11-03 Ampex Magnetic-core memory driving system
US3056948A (en) * 1959-06-15 1962-10-02 Bendix Corp Magnetic memory circuit
US3068452A (en) * 1959-08-14 1962-12-11 Texas Instruments Inc Memory matrix system
DE1273583B (en) * 1960-03-07 1968-07-25 Siemens Ag Magnetic core storage matrix
US3115583A (en) * 1960-04-18 1963-12-24 Ibm Information-gated flip-flop adapted to generate output in response to millimicrosecond sampling pulse from blocking oscillator
NL132967C (en) * 1960-05-24
US3223984A (en) * 1960-05-25 1965-12-14 Ibm Magnetic core memory
NL296665A (en) * 1962-08-20
US3317896A (en) * 1963-06-04 1967-05-02 Control Data Corp Transformer switching matrix
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US3231872A (en) * 1960-12-20 1966-01-25 Ericsson Telefon Ab L M Magnetic memory
US3307148A (en) * 1962-04-16 1967-02-28 Nippon Electric Co Plural matrix decoding circuit
US3360786A (en) * 1963-04-30 1967-12-26 Electro Mechanical Res Inc Magnetic core memory system
US3358269A (en) * 1964-04-10 1967-12-12 Bell Telephone Labor Inc Square switch distribution network employing a minimal number of crosspoints
US3351924A (en) * 1964-11-27 1967-11-07 Burroughs Corp Current steering circuit
US3460092A (en) * 1965-03-31 1969-08-05 Bell Telephone Labor Inc Selector matrix check circuit
US3460093A (en) * 1965-03-31 1969-08-05 Bell Telephone Labor Inc Selector matrix check circuit
US3453607A (en) * 1965-10-24 1969-07-01 Sylvania Electric Prod Digital communications system for reducing the number of memory cycles
US3500358A (en) * 1967-02-02 1970-03-10 Singer General Precision Digit line selection matrix
US3638199A (en) * 1969-12-19 1972-01-25 Ibm Data-processing system with a storage having a plurality of simultaneously accessible locations

Also Published As

Publication number Publication date
GB769384A (en) 1957-03-06
FR1141398A (en) 1957-09-02

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