US3167660A

US3167660A - Selective counting apparatus

Info

Publication number: US3167660A
Application number: US6280A
Authority: US
Inventors: Gerald T Moore; Henry P Kilroy
Original assignee: Giddings and Lewis LLC
Current assignee: Giddings and Lewis LLC; Giddings and Lewis Machine Tool Co
Priority date: 1960-02-02
Filing date: 1960-02-02
Publication date: 1965-01-26
Anticipated expiration: 1982-01-26

Description

Jan. 26, 1965 G. T. MOORE ETfAL SELECTIVE COUNTING APPARATUS 3 Sheets-Sheet 1 Filed Feb. 2. 1960 W USMQ @awww e Nm United States Patent O 3,167,660 SELECTEJE CGUNTHNG APPARATUS Gerald T. Moore, Bedford, and Henry P. Kilroy, Littleton, Mass., assignors to Giddings Qa Lewis Machine rool Company, Fond du Lac, Wis., a corporation of Wisconsin Filed Feb. 2, 1960, Ser. No. 6,239 9 Claims. @L3M-88) The present invention relates to the art of data processing and is more especially concerned with the selective counting or measuring off of different numbers of timespaced recurring signals.

It is the general aim of the invention to provide new and improved apparatus for counting or measuring olf different selected numbers of signals produced by a recurring signal source, such apparatus being characterized by its simplicity in organization and its reliability in operation.

More specifically, it is an object of the invention todo away with the need for gates of the type commonly employed in this art, and the vacuum tubes or transistors which they require, in apparatus of the type above specified.

Another object of the invention is to bring forth selective counting apparatus characterized particularly in that the over-all ratio of a scaling chain is changed according to the setting of one of a plurality of bi-state elements, preferably magnetic cores, and in which input signals are passed from a source to the scaling chain by the bi-state elements themselves as a result of non-destructive interrogation thereof in response to the input signals.

It is a further object to provide an advantageous system for selectively routing signals or pulses from a first terminal to any one of a plurality of output terminals.

Another object is to provide such a selective routing system employing bi-state elements which function not only as a means selectively set or conditioned to designate the particular output terminal which is to receive the signals, but also as a means for selectively transmitting input signals to the designated output terminal.

Other objects and advantages will become apparent as the following description proceeds, taken in conjunction with the accompanying drawings, in which:

FIGURE 1 is a diagrammatic block-and-line illustration of apparatus for initially setting shifting register cores according to a selected one of a plurality of numbers of signals to be measured off;

FIGS. 2A and 2B, when joined along the indicated junction line, form a diagrammatic block-and-line illustration of selective counting apparatus embodying the features of the invention; and

FIG. 3 is a schematic diagram showing the details of interconnections between exemplary ones of the magnetic cores employed in the apparatus of FIG. 2.

While the invention has been shown and Will be described in some detail with reference to a particular embodiment thereof, there is no intention that it thus be limited to such detail. On the contrary, it is intended here to cover all modifications, alterations, and equivalents falling within the spirit and scope of the invention as defined by the appended claims.

i@ Patented Jan. 26, i965 To make clear the environment of the invention and to illustrate one manner of transferring information to the selective counting means so as to establish different total numbers of signals which will be counted or measured off, FIG. 1 shows a plurality of counting or time selection cores 11-19 which are disposed at the ends of four shifting registers 21-24. Such shifting registers have respective input lines 21a-2da and are made up by a plurality of tandemly connected bi-state elements or magnetic cores 25 in a manner familiar to those skilled in the art.

The-magnetic cores here diagrammatically illustrated are of the familiar type often used as components in digital computers and data processing apparatus. Such cores are made of a ferromagnetic material which possesses a substantially rectangular hysteresis characteristic. The cores may, therefore, reside in either of two states, designated as the 0 and 1 states, depending upon the sense or direction of the residual magnetism or flux therein. If a magnetic core residing in a given state receives a magnetomotive force which tends to create flux in the same direction as the residual flux, there will be no appreciable change of flux within the core. Little or no voltage will be induced in an output winding, and the state of the core will be left unchanged. Conversely, if a core is residing in a given one of its two possible states and a magnetomotive force is applied to that core which creates flux in a direction opposite to the sense of the residual ux, and which drives the core to saturation, there will be a considerable flux change within the core and the latter will be switched to and left in its opposite state.

Connected to the input lines 21a-24a are the output terminals 31-34 of a coding device 35. The latter functions to convert signals appearing sequentially on difierent ones of plural input terminals 36 and representing the respective decimal characters 0-9 into a four place binary code representation. Since the organization and operation of such a decimal-to-binary code conversion device is Well known in the art, its details have not been illustrated. For purposes of explanation, it will be assumed that the Coding device 35 converts signals representing decimal digits 0-9 into a binary representation according to four-place 5211 code. This code may be best understood by reference to the following table:

Binary Code Decimal Number It will be seen from the foregoing table, that the four digit places of the binary code are assigned the respective decimal values of 5, 2, l and l. The presence of a aie-73660 E binary 1, as opposed to a binary 0, in each place of a four-place code representation, indicates that the decimal value assigned to that column is to be a part of the sum which equals the decimal number represented. For example, it will be seen from the table above that the decimal number 8 is represented by binary ls in the column, the 2 column, and the 1B column, so that the binary code representation 1101 equals the sum of 5, 2, and 1.

Although the organization of the device 3S is not shown in detail, it may be noted that each time an input signal is applied to one of the input terminals'vti, then the four output terminals 31-34 will be simultaneously and momentarily placed at relatively high or low potentials corresponding to the "0s and ls of the binary code for the particular decimal digit which corresponds to that input terminal. For example, if the input terminal 36 which corresponds to the decimal number 8 receives an input signal, then the output terminal 33 will -be momentarily and simultaneously elevated to a relatively high voltage, while the

terminals

31, 3,2, and 34 will be left at a-relatively low or zero potential. The terminals :i1-34 respectively correspond to the 5, 2, 1A and 1B digit places of the binary code.

Let it be assumed that each of the shifting registers 21-24 includes, say, ktwenty-seven tandemly connected cores 25. If thirty decimal digits are fed into the code device 35 by thirty successive signals applied to different ones of the input terminals 36, then the output terminals 31-34 will be energized in thirty successive combinations which, according to the 5211 binary code explained above, correspond to those decimal digits. It may be assumed that the cores in the shifting register all normally reside in the 1 state, and tha-t the first core iny each shifting register will be set to the "0 state in response to a high voltage received on the associated output terminals of the coding device. Thus, after each code response of the device and a corresponding setting of the first vertical row of cores 25, a shifting action will be induced (by means not shown) tol step the state of the cores, and the decimal number represented thereby, to the cores immediately on the right. In the process, the first vertical row of cores ZS will be returned to the 1 state, so that they are ready to receive the next output signals which appear on the terminals Iii-Sli. From this brief explanation, it will be understood that after thirty input signals representing decimal characters have been received and shifted into the registers 2,1-24, each group or" four vertically aligned cores will store and represent by their states one of the decimal digits. The first decimal digit will be stored in the last vertical row of cores on the right, and the last decimal digit will be stored in the rst vertical row of cores on the left.

The first three decimal digits shifted into the registers 2li-24S will be stored in the first, second and third vertical rows of cores from the right end of the shifting registers. Since these first three rows of cores on the right are here employed to store information which designates the time or the number of `signals to be counted, they are labeled in FIG. 1 as the Time Section of the shifting registers. If the very first decimal digit supplied to the coding device 35 and shifted into the register is the number 2, then the four vertically aligned cores at the extreme right in FIG. l will be set tothe states'0100 from bottom to top since the first core' on the right in the sluiting register 22 corresponds to the 2 column of the binary code. The core 11 and only this core in that vertical row will be set to the 1 state to represent the y decimal number 2.

measured off. Exemplary counts are designated in the first columns of the following table:

' Time Decimal Binary Codes Count Selection, Represec. sentation i To set the cores Tri-19 in the time section of the shifting registers so as to designate which of the nine possible counts is to be measured off, the first three digits in a set of decimal numbers fed to the terminals 36 will have the decimal values indicated in the third column of the foregoing table. And, after those first three digits have been fully shifted through the registers so `that they are represented in binary code by the states of the first three vertical rows of cores on the right, those cores will have the binary states which are represented in the last four columns of the foregoing table. For example, if a count of 1 105 signals is desired, the first three decimal characters supplied to the coding device 35 will be 005. When the first two zeros of this expression are shifted into the shitting registers, the first two vertical rows of cores on the right will all be left in their 0 states. The third digit 5 when shifted into theregisters will, however, resul-t in the core 16 being set to its 1,state, while the cores 17, 1S and 19 will be left in their 0 states. It Will be seen from an inspection of the foregoing table that for each of the nine decimal representations of the nine possible counts,7 one and only one of the nine time storage cores 11-19 will be set to the l state. The remaining ones of these cores 1149 will be left inthe 0 states. Thus,kit will be clear that whenever any one of the nine cores lli-19 is set toits "1 state, the count shown below has been selected by the information receivedk on the input terminals 36.

' Selected Time Sclec- Selected Time Number of tion Cores Period, scc. Signals to be t Counted 1l 200 4 106 l2 100 2)(10i 13 50 1)(10x 14 20 4 l05 15 10' 2X1()5 1G 5 Y 1)(105 17 2 l 4)(104 18 1 2X104 19 M Il l04 If the recurring signals occur at a uniform repetition rate or frequency, the counting off of different numbers of such signals will also measure off different time periods between the beginning and the end of the counting cycles. By way of example, if the recurring signals have a frequency of 20,000 signals per second, then the counting of the diferent numbers of signals indicated in the foregoing tables will occupy the different time periods listed in the second columns of the two tables.

The cores 111-19 described in connection with FIG. 1 also appear in FIG. 2A and their operation in connection with the selective counting apparatus will be made clear below.

The selective counting apparatus of FIGS. 2A and 2B includes, as a lirst component thereof, a scaling chain it? which accepts recurring input signals and produces one output signal for each predetermined number of input signals. This ratio of input to output signals is termed the scaling ratio. As here shown, the scaling chain is made up of a plurality of bi-state elements, specifically, iip-iiop circuits labelled FR connected in tandem counting relation. The rst flip-flop 41 is connected in tandem relation with six decade scaling units i2-47, and the latter such unit works into a final flip-flop 4S. A carry output terminal S0 for the latter iiip--op may be considered as the completion output terminal for the entire scaling chain 4f@ since it will receive a pulse or output signal only at the completion or end of each counting cycle.

Before describing the operation of the scaling chain 40 as a whole, it may be pointed out that the iiip-iiop circuits used therein are well known to those skilled in the art. Brieliy stated, each such flip-flop may, in one form, be made up of two cross-connected vacuum tubes or transistors, each being complementally cut off or conductive when the circuit is in its two possible stable states. Each such ip-op switches from a to a 1 state and from a "1 to a 0 state in response to two successive input pulses supplied thereto. The flip-nop produces a carry output pulse each time that it switches from the "1 to the "0 state, thus creating one-half as many output pulses as received input pulses. Thus, a single Flip-flop operates as a scaling device having a scaling ratio of two.

By connecting two, three or `four hip-flops in tandem relation so that the output pulses of one for-n1 the input pulses of the next, a unit is created which scales by a factor of 4, S, or 16, respectively. In the present instance, however, it is desired to utilize units which scale by factors of 10, i.e., each of which produces one carry output pulse for each ten input pulses. Such decade scaling units may take a variety of forms such as the familiar multi-anode counting tubes, but in the present instance are made up of four liip-liop devices interconnected in a special way so that they scale with a ratio of ten rather than a ratio of sixteen. Since the decade units i2-47 lare all substantially alike, a description of one will sulice for all.

Referring to the decade unit 42, the `four tandemly connected flip-flops therein are designated by the characters A, B, C and D. Ordinarily, `four tandernly connected ip-liops would create a sealer or divider unit having a seating ratio of sixteen operating with ordinary binary scaling action. Scaling with a ratio of ten is obtained in the present decade unit 4Z through the use of a normally open gate E connected between the output of the ip-iop A and the input of the ip-iiop B. A second, normally closed gate F is connected between the output of the flip-liep A and the input of the hip-flop D. The gate E is controlled by a potential supplied over a line 51 from the fourth iiip-liop D, so that it is closed only whenever the latter iiip-llop is in the "1 state. A suitable delay means d1 is interposed in the line 511 to give adequate switching time. The normally closed gate F is controlled by a potential supplied over a line 52 which leads through a delay device d2 from an output terminal of the fourth ip-ilop D, this gate thus being opened or closed whenever the fourth flip-iiop is in the "1 or "0 state, respectively. It will be understood by those skilled in the art that the delay devices d1 and d2 connect to an output terminal of the ip-op D which resides at, say, a high voltage when the ip-op is in the 1 state, and at a low voltage when the ip-ilop is in the 0 state. Assuming that the high voltage actuates the gates E and F, the latter will be respectively closed and opened shortly after flip-dop D is set to the 1 state, and will be respectively opened and closed shortly after the flip-liep D is restored to the 0 state. The output terminal 58 of flip-flop D, on the other hand, is associated in well-known manner with a ditferentiating and clipping circuit, so that sharp negative-going pulses appear thereon only when the flip-flop D switches from the l to the 0 state. These latter pulses iorrn the input to the next decade unit 43.

Considering that the input terminal 54 of the flip-op A .forms the main input terminal -for the decade unit 4t2, as input signals or pulses are supplied successively to that input terminal, the four ltandemly connected flip-flops A, B, C, and D, behave as an ordinary binary scaling chain in response to the lirst eight pulses which are received. During this mode of operation, it will be seen that output pulses from the tiip-tiop A pass through an or circuit 5S and the normally open gate E to the input terminal of the flip-hop B. Similarly, output pulses from the iiip-fiop B pass directly to the input of the iiip-op C; and output pulses from the ip-iiop C pass directly to the input terminal of the Hip-lop D. Thus, assuming that all of the flip-flops were initially in their "0 states, eight pulses supplied to the input terminal 54 will result in the last flip-flop D being set to the "1 state, and the first three ilip-iiops A, B, and C being in their 0 states.

After the eighth pulse has been received and the flipop D has been switched to the l state, the control signals passed over the lines 51 and 52 will respectively close and open the gates E and F. T he ninth input pulse, therefore, switches the first flip-flop to the 1 state and creates no output signal on the output terminal of that flip-flop device. The tenth input pulse returns the ip-flop A to the "0 state and creates an output pulse which cannot pass through the gate E, but which passes through an or circuit 5d and the open gate F directly to the input terminal of the fourth flip-dop D. This switches the fourth flip-flop D to the U0 state and creates a pulse on its output terminal 58 which forms the main output terminal for the scaling unit 42. As an incident to switching of the ip-flop D back to its G State, the control signals supplied over the lines 51 and 52 re-open the gate E and reclose the gate F, so that the unit 42 is returned to its original condition and is ready to repeat the scaling cycle described in response to the next ten input pulses received on the terminal S4. The counting or scaling action of the decade unit may thus be illustrated by the following table:

Flip-Flop States Input Pulses A (1) B (2) C (4) D (8) 0 0 0 0 0 1 1 0 0 0 2 0 1 D 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 l* 9 l 0 O 1 10 o 0 0 ot *Gates E and F close and open. 'tOutput pulse on terminal 58; gates E and F open and close.

This table shows the states of the four liip-ops A, B, C

and D in the decade units 42 after each of ten input pulses has been received. When the tenth input pulse occurs,

ener/,aco

one output pulse appears on the terminal 58 and the four flip-Hops of the decade units are restored to their original states, ite., are all set in the state, so that the counting cycle of the unit will be repeated as the next ten input pulses are received.

It is possible to make a decade scaling unit, such as the scaling unit 42, scale by a factor Aof if the input pulses are by-passed around the rst flip-flop A. For this purpose, input pulses may be supplied to an alternate input line 59 instead of to the input terminal S4. The line 59 leads through the or gate 55 and the normally open gate E to the input of the second ip-iiop B. With the three flip-hops B, C, D initially in the "0 state, the rst four input pulses received over the line 59 pass through the normally open gate to the input of the flip-flop B. After the fourth pulse is received, however, the flip-flop D will be in the 1 state, causing the gates E and F to be respectively closed and opened. Thus, the fifth input pulse over the line 59 Will pass through the or circuit 56 and the gate F directly to the input of the flip-flop D. This switches the flip-op D from the l to the "0 state, producing an output pulse on the terminal 58 and restoring the flip-ops B, D and C to the 0 state. The manner in which the unit 42 scales by a factor of 5 if input pulses are by-passed around the first ip-op A, is illustrated by the following table:

Flip-Flop States Input Pulse A B C D *Gates E and F respectively close and open.

TGates E and F respectively open and close.

tOutput pulse on terminal 58.

The decade unit 42 may also be made to scale by a factor of 2 by by-passing input pulses around the first three Hip-flops A, B, C and supplying them directly to an alternative input line 60 which leads to the input of the fourth iiip-lop D. Under these circumstances, the last flip-flop D scales by a factor of 2 in the same manner as a single, isolated liip-flop, there being one Output pulse appearing on the terminal 58 for every two input pulses passed over the line 60.

Considering now the scaling channel 40 as a whole (made up of the flip-Hop 41, the six decade units i2-17, and the last flip-flop 43), one complete counting cycle as the term is here employed, is the operation of the chain in counting (from an original condition in which all the flip-flops are in their "0 state), the number of input pulses necessary to produce an output pulse on the final output terminal 50. It will be apparent that just before the last input pulse for any given counting cycle is received, all of the iiip-iiops which are effective in the scaling chain will be in the l state. The last input pulse restores all of the flip-flops to the "0 state, and this switching of the ip-op to the 0 state produces a final output pulse on the terminal 50.

In order to make the scaling chain have different effective scaling ratios so that any one of a plurality of different predetermined numbers of signals must be received during different counting cycles, means are provided to change the effective length or over-all scaling ratio of the chain. This is done by providing a plurality of input terminals 61-69 for the scaling chain, any one of which may receive input signals or pulses, thus by-passing different numbers or combinations of the flip-ops at the front or left end of the scaling chain 40. Inspection of FGS. 2A and 2B will show that if input pulses are supplied to the first input terminal 61, all of the flip-flops are effective in the scaling chain L10. Since the flip-flops 41 and 43- both scale by factors of 2, and the six decade units l2-47 scale by factors of 10, the entire scaling ratio of the chain is 2 10 10 10 10 10 10 2, or 4 106. Thus, atotal of 4 million pulses must be received from a signal source over the input'terminal 61 before a final output pulse appears on the terrninalll.Y

If, however, input pulses are received over the

terminals

62 or 63, the decade unit e2 will scale by factors of l0 or 5, respectively, and the first flip-flop 41 will be entirely by-passed or made ineffective. Under these circumstances, the effective scaling ratio of the scaling chain is 2X106, or 1 105, respectively.

With the foregoing examples in mind, the following table will be readily understood as showing the different total scaling factors created when the input pulses are supplied over different ones of the input terminals S1-69.

The foregoing table not only shows the total scaling factor of the scaling chain 40 and the number of input pulses required on the different input terminals 61-69 to produce a complete counting cycle and a final output pulse on the terminal 50, but it also shows in the last column on the right the time periods which will be measured off if those input pulses occur with a predetermined frequency, e.g., 20,000 pulses per second. It will be seen that by supplying input pulses at -this `frequency to any one of the nine input terminals of the scaling chain, time periods ranging from 200 seconds to as low as 1/2 second may be measured off between the instant that the input pulses begin arriving at one of the input terminals 6h69 and the instant that an output pulse appears at the inal terminal 50.

The input signals or pulses to be supplied to the scaling chain 40 `are created in the rst instance by a suitable recurring signal source 70 which may take any variety of forms such as a free-running multivibrator, a blocking osf cillator or a sinusoidal oscillator combined with a pulse shaping network. For purposes of the present explanation, it will be assumed that the souce 70 produces input signals at a constant frequency of 20,000 pulses per second, although the source 70 need not necessarily produce signals at a constant repetition rate. Signals from the source 70 are passed through a gate 71 to a terminal 72. A counting cycle is commenced by a signal applied to a start terminal 5 which sets a ip-flop 73 to its l state. rlhis produces a control signal on a line 73a which opens the gate 71 so that input signals begin appearing on the terminal 72. The terminal 7?. may thus be considered as the output terminal of the pulse source 70 `and on which appear recurring signals which are to be selectively routed to different ones of the scaling chain input terminals 61-69.

The problem exists of routing signals from the terminal 72 to any one of the input terminals 621-59 according to the selective information represented by the states of the cores 111-19. In accordance with the present invention, selective pulse routing apparatus 74 is interposed between the source 70, i.e., its terminals '72 and the plurality of terminals 61-69, this apparatus functioning to pass input signals to any one of the latter terminals according to the information which is received by the cores 11-19 and which designates the count or time period which is to be measured olf. While the plurality of ter- Q minals 61-69 may be considered as input terminals for the scaling chain 40, they may also be viewed as the output terminals for the selective routing apparatus 74.

In carrying out the invention in its preferred form, a plurality of bi-state devices Sil-S9 are employed, each corresponding to one of the terminals 61-69 and to one of the possible counts or time periods which may be selected. The bi-state devices 81-39 preferably take the form of magnetic cores similar in character to the cores 11-19 described above. These magnetic cores 81-89 all normally reside in the state, but may be switched between their two states by magnetomotive forces of opposite senses applied thereto.

In order to set any one of the cores 81-89 to its l state when a corresponding one of the plurality of possible counts is to be measured off, interconnections 81a- 89a are established between the cores 111-19 and corresponding ones of the cores 81-89. A transfer line 90 leads to all of the cores 11-19 and is connected with means for setting any of the cores Slt-S9 to its l state in response to an energization pulse or signal applied to the transfer line if the corresponding one of the cores 11-19 is then in its 1 state. The details of such transfer means will be made clear below with reference to FiG. 3; it need only be understood at this point that a pulse applied to the line 90 will drive any one of the cores 81-89 to its 1 state if a corresponding one of the cores lil-19 is in its l state.

After any one of the bi-state devices or cores 81-89 has been set to the 1 state to designate which of the possible counts or time periods is to be measured off, signals originating at the source 70 are transmitted by that particular bi-state device or core to the corresponding one of the terminals 61-69. For this purpose, means are provided to non-destructively interrogate all of the bistate cores 81-89 in response to each signal from the source 7i) and to pass a signal or pulse to any of the terminals 61-69 which corresponds to one of the cores {i1-89 then in the 1 state. As here shown in FIGS. 2A and 2B, the output terminal 72 of the source 70 is connected directly to an interrogate line 76 which leads to all of the plurality of magnetic cores 81-89. The cores 81.- 89 are respectively paired with a second plurality of cores 91-99. The cores 91-99 are all normally in their 0 states. Each input signal passed over the interrogate line 76 tends to drive all of the cores 81-89 to their 0 states, in a manner which will be more fully explained below. Any of the cores 8].-89 which is switched from its l to its 0 state in response to an inpu-t pulse applied to the interrogate line 76 causes the associated one of the cores 91-99 to be switched to the l state by an energization signal passed over the corresponding one of thehtransfer links Sib-8%.

To complete the selective routing apparatus 76, means are also employed which tend to drive all of the second plurality of cores 91-99 to their 0 states a predetermined time after the appearance of each input signal on the terminal 72. As here shown, the input terminal 72 is connected through a time delay device 77 to a restore line 7S which leads to all of the cores 91-99. The period of delay created by the device 77 is chosen to be less than the shortest time between successive ones of the input signals produced by the source 70. Thus, in response to each input pulse appearing on the terminal 72, a delayed signal is created on the restore line 78 and, in a manner to be explained in detail, drives all of the second cores 91-99 toward the 0 states. If any one of the cores 91-99 is at that instant in its l state, it will be switched back to its 0 state; those cores which are at that instant in their 0 state will simply be left in that condition.

Means are provided to produce two effects in response to the switching of any one of the second plurality of cores 91-99 from its 1 state to its 0 state. First, output lines Mer-99a lead from the respective cores 91-99 through buffer amplifiers lijf-lil? to the respective output terminals 61-69. These output lines @1a-9% are associated with output windings which transmit signals only in response to the switching of their associated cores from the l to the state, as will be more fully detailed below. Secondly, restoring links @1b-9% are connected between each one of the cores 91-99 and the associated one of the cor-es 'd1-89 to serve as a means for switching any one of the cores iii-3% to its l state in response to switching of the corresponding cores i1-99 from its l to its 0 state. The detailed nature of these restoring links will be rnade clear subsequently with reference to FIG. 5'.

ln order that the interconnections and operation of the magnetic cores shown in FIGS. 2A and 2B may be er understood, exemplary ones of those cores and the windings thereon are shown in detail by FlG. 3. Con- Sider first the cores 25, 1S and 1S shown in FTG. 3 and which, as indicated in FG. l, are a part of the shifting register 24. These shifting register cores are provided with input windings 25a, 13a., 15a; output windings Zb, 13b, 15b; and advance windings 25e, idc, 15C. Assume that after one set of information has been partially shifted into the register Zd, that the core 25 is in the 0 state and that

cores

13 and 15 are in the l state. Advance pulses are then sequentially applied to the advance windings 15C, 18e and 25C in the order named, each such pulse tending to drive its core to the l state. There is no flux reversal in the cores 1S and 15 in response to these advance pulses, but the core 2S will be switched from the 0 state to the l state. As a result, a voltage is induced in the output winding 25h which causes current flow through a diode 115 to the input winding 18a, such current setting the core 18 to its 0 state. No output current flow occurs in the winding 15b because the induced voltage therein reversely biases the diode 11d. Thus, the advancing action shifts the state of each core to the core immediately on the right. The input winding 2.5! may or may not be energized from the preceding core (not shown), depending upon whether the latter was in the 0 or i state when the shifting action begins.

When the advance windings are again sequentially pulsed, the core 18 will be reset from the 0 to the l state, and an output voltage will be induced in the winding 13b to create current flow through the diode 116. Such current energizes the input winding 15a and thus sets the core 15 to its O state.

Summarized, each set of advance pulses shifts the state of any core in the shifting register to the next succeeding core on the right. Thus, either of the cores 13` or 15 may be set to the l state in accordance with information received by the coding device 35 (FIG. l) and shifted into the register 24.

Assume that after a complete block of information has been received by the shifting register that the core 18 is in the l state and the core 15 is in the 0 state, indicating a selected count of 2 104 or time period selection of one second. After the time cores have been set in accordance with the information received by the input terminals of FTG. l, an energizing signal is applied (by means not shown) to the transfer line 90. This line leads to the junction 118 between windings 119e and 1191) which are wound in opposite directions on the core 88. The winding 11951 is returned to a common point 117 through a resistor 120, a diode 121, and a transfer winding 122 wound on the core 1S. The sense of the winding 122 is such that the current flow therethrough from the diode 121 creates a magnetomotive force which tends to drive the core 18 to its 0 state. The winding 1191; is returned to the common point 117 through a resistor 124 and a diode 12S. The impedance of the transfer winding 122 to a current pulse passed therethrough will be one of two values, depending upon whether the core 1S is then resid- V or "1 states, respectively.

1 1 ing in the 0 or the l state. The values of the resistors 120 and 12d are so proportioned that if the core 13 is in the 0 state, then current from the transfer line 90 will divide equally between the windings 11M and 11%, thus creating counteracting magnetomotive forces which leave the core 8g in its 0 state. On the other hand, if the core 1S is in its l state, the impedance of the winding 122 has a different value so that current fiowing from the transfer line 90 divides unequally between the windings 11%, 11%, creating a net magnetomotive force in the core S8 which drives the latter to its l state. An an incident to this current flow through the transfer winding 122, the core 18 is returned from its l state to its 0 state. It will be apparent, therefore, that a current pulse appearing on the transfer line 90 acting in the split transfer circuit or link 38a will drive the core 11S toward its 0 state, and will switch the core 83 to its l state if the core 1@ at that time is in its l state. On the other hand, if the core 115 is in its 0 state when a transfer pulse occurs on the line 90, the

cores

88 and 13 will be left in their 0 states.

The transfer link 85a between the

cores

15 and 85 is identical to the link 58a just described in detail. The common point 117 in the link Sa leads in series to the junction 127 in the link 85a, thus indicating that current pulses applied to the transfer line 90 pass in series through all of the transfer links 31a-29a. Thus, in response to a transfer pulse appearing on the line 90, the link 85a will serve to set the core 85 to its 17 state if the core at that time is in its 1 state, returning the latter core to its 0 state. Conversely, if the core 15 is in its 0 state, the core 85 will be left in its 0 state. The transfer links @1a-59a shown in FIG. 2 are` all organized and operate in the same manner as the links S31-rnd 85a which are shown in detail by FiG. 3.

The transfer link SSI: which interconnects the core 32'; and its paired core 98 is substantially like the split transfer loop previously described for the transfer link Sa. That is, the interrogate line n leads to a junction between two oppositely wound windings 12% and 12% on the core The winding 129er is returned through a resistor 13d, a diode 131 and a transfer winding 132 to a common point 13.3; while the winding 129i) is returned directly to the same point through a resistor 134 and a diode 135. In response to a current pulse of the polarity indicated on the interrogate line 76, therefore, the core 85S will be driven towards its 0 state, while the core 9S will be left in its 0 state or switched to its 0 state if the core at that instant is in its The transfer link 85h between the cores and 5 is identical to and connected in series with the transfer link heb just described. Thus, it will be apparent that in response to each interrogate pulse appearing on the line 76 the transfer connections @1b-39h in FTG. 2 will serve to switch any one of the cores 91-93! to the 1 state if the corresponding one of the cores 81-39 is in its l state. Any of rthe cores 81-39 which is in its 1 state when the interrogate pulse occurs will be returned to its 0 state.

The restore line 7S as shown in PEG. 3 passes in series through restore windings 13d and 137 on the cores 9S and 95. The sense of these restore windings is such that current flow through them creates a'magnetomotive force n the cores 9S and 95 which tends to drive fiux in those cores to the "0 state. 1f either of the cores 9S or 95 was in the "0 state before the restore signal appeared, then no output response is created in output windings 13S or 139 disposed on those cores. 1f, however, the core 93 has been set to its 1" state before a restore pulse appears on the line '73, then that restore pulse will switch the core 98 to its "0 state and induce a voltage in the output winding 138 which creates current flow through an associated diode 140, such current passing over the output link Mia to the associated buffer amplifier shown in FG. 2. Thus,

13 it will be clear that a restore signal on the line 78 in FG. 2 drives all of the cores 91419 toward their zero states, and any one of such cores which in response switches from the l to the 0 state will produce an output signal on the corresponding one of the output lines 9151-9961.

As previously indicated in connection with FIG. 2, restore links Sb-9% are provided between the cores 1-93 and the associated cores d1-89 to reset any one of the latter to its "1 state whenever the associated core of the group 91-99 is switched from its 0 to its "1 state. As shown in detail by FIG. 3, the restore link 95h corn- 98 and connected in series through a diode 142 to a restore input winding 144 on the core S8. The sense of the winding 141 is such that when flux within the core 9S switches from the 1to the 0 state, the voltage induced in the winding 141 is of a polarity to create current flow through the diode 142. This current flow through the winding 144 creates a magnetomotive force in the core 93 which drives the latter to its 1 state. Thus, if the core $5 is switched from its 1 to its 0 state, not only is an output signal produced on the output line 98a, but the core $8 is restored to its original l state.

The restore link 95b connected between the core 95 and the core is identical and functions in the'same manner as the restoring link 98b just described.

At the completion of a counting cycle, that one of the cores 81-89 previously set to the l state is cleared or returned to the 0 state so that a new count may be selected. This is done by applying a clear current pulse to a clear line 147 (FIGS. 2 and 3). The clear line leads in series through windings (exemplified by winding 143 and 149 in FlG. 3) on all the cores S1-89, such windings being wound in a sense to drive the cores toward their "0 states. Any one of the cores which is switched to its "0 state when cleared produces no effect on the associated cores, since the diodes in the transfer links Sfar-89a and @1b-89h prevent responsive current in those links.

Assuming now that at the beginning of acycle of operation the core 18 was lin its l state and the core 1S in its 0 state, a transfer pulse appearing on the line 90 sets the core 55 to its l state and leaves the core S5 in its 0 state. With the commencement of pulses from the source 70 appearing on the terminal 72 (FlG. 2), recurring interrogating pulses are applied to the line 741. The device 77 produces a pulse appearing on the restore line 78 shortly after each such interrogate pulse. The core d@ ywill be driven to its 0 state and the core 98 driven to its l state in response to the rst input `or interrogating pulse. Then the core 9S will be driven to its "0 state in response to the first restore pulse to produce an output signal on the output line 98a and to produce a signal in the restore link 98h which resets the core 33 to its original l State. S0 long as input pulses from the source 70 continue to occur, therefore, the cores SS and 9S will be switched from one state to the other and back to their original states in response to each such input pulse. Each time this switching of the core 93 back to its "0 state occurs, an output pulse will appear on the output link 9&1. That is, there will be one output pulse on the line 93a for each input pulse appearing on the terminal 72. On the other hand, because the core 15 was assumed to originally be in the 0 state and the transfer pulse appearing on the line t) thus left the core 8S in its 0` state, the alternate interrogato pulses on the line 7o and the restoring pulses on the line 7S simply leave the

cores

35 and 95 in their 0 states. No switching ofthe core 95 occurs, and no output pulses at all appear on the output line a.

It is to be understood that all of the transfer links 81st-89a shown diagrammatically in FIG. 2 are identical in organization and operation with the links 38a and 85a which are shown in detail by FIG. 3. Similarly, all of the transfer links S1b89b shown in FIG. 2 are identical to the links Sb and b shown in detail by'FlG. 3.

Moreover, the restore links 981') and 95h shown in detail by FlG. 3 indicate the organization and operation of all of the restore links 9117-98!) illustrated diagrammatically in FIG. 2. The restore line 78 shown in FlG. 2 as leading to all of the cores 91-99 passes in series through restore windings on all of these later cores, as is illustrated by the restore winding 13d, 137 in PEG. 3. Finally, the output links 91a-99a are all identical in their organization and operation to the output links shown in detail by FlG. 3 and constituted by the

output windings

138 and 139 on the cores 9S and 95, such output windings being connected in series with diodes which transmit an output signal only when the associated core switches from its l to its state.

Rsum of operation With the foregoing in mind, the operation of the selective counting apparatus as a whole may now be described. At the beinning of a cycle of operation, the flip-flop 73 will be in its 0 state and the gate 71 closed, so that no input pulses appear on the terminal 72. A set of information which by the first three characters therein designates the desired count, is received on the input terminals 36 (FIG. l) and will be shifted into the register Zit-24. A particular one of the cores 11-19 will be set to its l state to designa-te which of the several time periods or numbers of pulses is to be measured off. Following this shifting of information into the registers, a transfer pulse will be applied to the transfer line 90 and a particular one of the cores dll-S9 which corresponds to that one of the cores 11-19 previously set to its l state will be switched to the l state, thereby designating which of the several counts is to be measured olf. Assume that the core 15 in FIG. 2 was initially set to the 1 state, while the remaining cores 11-14 and 16-19 were left in their 0 states. The appearance of a transfer pulse on the line 90 will thus set the core 85 to its l state and leave the cores fil-S4 and S6-89 in their "0 states.

The gate '71 is now opened in response to a start signal applied to the terminal S, so that recurring input signals are passed from the source 70 through the gate to the terminal 72. These recurring input signals appear sequentially on the interrogate line 76, each one tending to drive all of the cores 81-89 to its 0 state and thus switching any one of those cores which was in its l state to the 0 state. Pursuing the example initiated above, if the core 3S was in the l state, that core will be returned to the 0 state in response to each interrogate pulse appearing on the line 76. As a result of this switching of the core 85, the interrogate link S51) will cause the associated core 95 to be switched to its l state. Thus, each input pulse appearing on the terminal 72 sets any of the cores 91-99 to itsl state if the associated one of the cores Slt-8g was in its 1 state.

After a predetermined time delay produced by the device 77 from the instant that each input pulse appears on the terminal 72, a restore pulse appears on the line 70. This restore pulse on the line 7S tends to drive all of the cores 91-99 to their 0 states, and thus will switch any one of those cores originally in its l state. If the core 95 has been set to its 1 state in response to the previous interrogating pulse, the restore pulse will switch it back to the 0 state. As an incident to switching of any core 91-99, from is l to its O state, an output signal is passed through the associated buffer amplifier to the associated one of the output terminals 61-69. Moreover, in response to the switching of any of the cores 91-99 from its 1 to its 0 state, the associated restore link 91b-99b causes the associated one of the iirst set of cores 81-89 to be restored to its l state. Thus, the l state of any of the cores 31439 is non-destructively sensed by each input pulse appearing on the terminal 72 and an output pulse is generated on the output terminal which corresponds to that core which is in the l state.

Pursuing the example, initiated above, the alternate interrogate pulses on the line 7d and restore pulses on the line 73 wil cause switching of the core 95 first to its l state and then to its 0 state. Each time that the core 9S returns to its 0 state, a pulse will appear on the terminal 65 which leads to the input terminal of the ilip-llop A in the decade scaling unit 43. Thus, the effective scaling ratio of the scaling chain t0 will be 2 l05, and a total of 200,000 input pulses must appear on the terminal 72 and be transmitted to the terminal 65 before a nal output pulse appears on the scaling chain terminal 50. Thus, the setting of the core 15 to its l state and the subsequent operation of the apparatus will result in the scaling chain 40 measuring off 200,000 pulses before signifying by an output pulse on the terminal 50 that such number of pulses has been received. lf the pulse source 70 has a constant frequency, for example, 20,000 pulses per second, then an elapsed time of 10 seconds will occur etween the opening of the gate 71 and the appearance of an output pulse on the terminal 50.

In like manner, if any of the cores 11419 is originally set to the l state by information received on the terminals 36 (FIG, l), then the numbers of pulses which will be generated by the source 72 during one complete counting cycle, and the time periods occupied by such counting cycle, will have the values which are set forth in the preceding table.

In order to terminate the operation of the scaling chain after it has completed any counting cycle, the final output pulse appearing on the terminal 50 is passed over a line to an input terminal of the flip-flop 73. This output pulse resets flip-flop 161 to its 0 state, the control potential passed over the line 73a closes the gate '71, thereby terminating the appearance of input pulses on the terminal 72. The inal output pulse on the terminal 50 is also passed over a line 161i to the clear terminal associated with the cores Slt-89. In response to this pulse, therefore, all of the cores Sli-39 are driven toward their 0 states, and that one of these cores which was previously in its l state will be returned to its 0 state Without affecting any of the associated cores 93-99.

The next set of information, which may have been shifted into the shifting registers of FIG. l during the counting cycle described, may now be transferred to the cores 81-89 by a transfer signal applied to the transfer line 90. Following this, a start signal may be applied to the terminal S to set the flip-flop 73 to its l state. With this, the control signal passed over the line 73a opens the gate 7l so that pulses generated by the source 70 appear on the terminal 72 and the counting or scaling action previously described is started for the next cycle. ln each instance, the particular one of the cores til-S which was set to its l state before the beginning of a scaling cycle determines which of the terminals 61-60 will receive input pulses, and thus the total number of pulses which will be measured olf during that cycle.

It will be apparent from the foregoing that the present arrangement makes it possible to measure olf any one of 'different numbers of pulses generated by the source 70,

and to measure off any one of a plurality of time periods if the pulse source 70 operates at a substantially constant frequency. Since the bi-state elements or cores employed therein are switched repetitively in response to input pulses and serve to transmit output pulses to a selected one of the scaling chain input terminals ell-6%, the principal components of the selective routing apparatus '74 do not involve the -use of vacuum tubes or transistors. The use of vacuum tubes or transistors, except as power ampliers, is substantially eliminated. The arrangement is characterized by relatively simple structural components and a high degree of reliability in operation.

We claim as our invention:

l. In apparatus for measuring off diiferent selected numbers of recurring input signals received from a source, the combination comprising a scaling chain having a plurality of scaling units connected in tandem relation with the last such unit having an output terminal, a'plurality of input terminals ieading to dilierent points in said scaling chain to provide ditlerent over-all scaling ratios for the chain, a plurality ot bi-state devices adapted to reside in either l or 0, states and normally residing in the state, each of said bi-state devices corresponding to one of said input terminals, means for setting one of said devices to its l state according to the particular selected number of signals which is to be measured off, means responsive to each of said input signals for driving all of said bi-state devices toward their 0 states, means responsive to the switching of each of said bi-state devices from its l to its G state for restoring that device to its l state after a time delay which is less than the eriod between said recurring input signals, means responsive to the switchinY of any of said oi-state devices from its l to its "0 state for creating a signal on the corresponding one of said input terminals, and means responsive to a signal on the output lterminal of said scaling chain for clearing all of said 'bi-state devices to their states without transmitting a signal to any of said input terminals.

2. ln apparatus for measuring oli different selected numbers of recurring input signals received from a source, the combination comprising a scaling chain having a plurality of scaling units connected in tandem relation with the last such unit having an output terminal, a plurality of input terminals leading to dilerent points in the scaling chain to provide different over-all scaling ratios for the chain, a plurality o pairs of iirst and second magnetic cores, each said pair of cores corresponding to one of said plurality of input terminals, each of said magnetic cores having a substantially rectangular hysteresis characteristic and being susceptible of residing in 0 or l states represented by the direction of residual magnetic flux therein, means for selectively setting to its l state the first core ot the pair of cores which corresponds to vthe particular selected number ot' input signals which is to be measured off, means responsive to each of said input signals for driving the first core in all of said pairs toward its 0 state, means responsive to switching of the iirst core in any of said pairs from the l to the 0 state for switching the second core in that pair to the` l state, means responsive to each of said input signals for driving the second cores in all of said pairs toward the il state after a time delay which is shorter than the period between said recurring input signals, means responsive to the switching of the second core in any of said pairs from the l to the O state for transmitting a signal to the corresponding one of said plurality of terminals, means responsive to the switching of any ot' said second cores from its l to its G state for switching the corresponding core from its 0 to its l state, and means responsive to the appearance of an output signal on said output terminal for driving all of said irst cores toward their zero states without atiecting any of said second cores.

3. ln apparatus for measuring ott different predetermined numbers of recurring signals, the combination comprising a source of recurring signals, a scaling chain having a plurality of input terminals each of which leads to a diierent point along the chain and which causes the latter to have a different effective scaling ratio when input signals are applied to that terminal, a plurality o pairs of magnetic cores each having a substantially rectangular hysteresis characteristic and susceptible of residing in either a or a l state, each of said pairs of cores corresponding to one of said different predetermined numbers, means tor setting the lirst core of a pair which corresponds to a selected one of said predetermined numbers to its l state, means for driving the irst cores of all of said pairs ktoward their O states in response to each signal from said source, means responsive to switching ot the first core in each of said pairs from its l to ,its 0 state for setting the second core of that pair to its l state, means for driving the second core in all of said pairs towards its O state a predetermined time instant after operation of said first-mentioned driving means, means responsive to switching of the second core in any one ot said pairs from the l tothe O state for transmitting an input signal to the corresponding one of said input terminals, and means tor clearing and restoring to its 0 state the irst core in all of said pairs in response to the completing of one counting cycle by said scaling chain.

4. The combination set forth in claim 3further characterized in that said source of recurring signals is a substantially constant frequency source, so that the selective counting of said different numbers of signals-also selectively measures ot different timeperiods. t

5. In apparatus for selectively measuring ol'diilerent numbers of recurring signals, the combination comprising Va scaling chain having a plurality of scaling units connected in tandem relation and an output terminal at the ,last such scaling unit, a plurality of input lines leading to dierent points along said scaling chain andrespectively by-passing different numbers of ,said scaling units to create different over-all scaling ratios for said chain, a irst plurality of magnetic cores each corresponding to one of said input lines, a second plurality of magnetic cores each corresponding to one of said input lines, said cores having a substantially rectangular hysteresis characteristic and being susceptible of residing in 0 or l states depending upon the sense of the residual magnetism therein, said cores normally residing in the state, means for setting any one of said iirst cores to its O state to designate the selection of the corresponding one of said different numbers of said recurring signals to be measured oil, a source of recurring signals which are spaced apart in time, a single interrogate line associated with all of said first cores, means for applying each signal from said source to said interrogato line, means responsive to a signal on said interrogate line for vriving any of said first cores which is in its l state to its 0 state, means responsive to switching of any of said tirst cores from the l to the O state for switching the corresponding one of said second cores to its l state, a restore line, a time delay device interconnected between said source and said restore line, means responsive to a signal on said restore line for switching any of said second cores which is in the l state to the G state, an output winding on each of said second cores, means interconnectingeach said output winding with a corresponding one of said input lines to produce a signal on any input line when the corresponding core switches from its l to its 0 state, and means responsive to switchingof any ot said second cores from the to the 0 state for restoring the associated first core to its l state. t

6. In apparatus for selectively routing recurring input signals appearing on a rst terminal to any one of a plurality of outputterminals, the combination comprising a plurality of bi-state devices adapted to reside in either l or 0 states and normally residing in the 0 state, each of said bi-state devices corresponding to one of said plurality of terminals, means for setting one of said devices to its l state according to a selected one or" said plurality of terminals which is to receive said input signals, means responsive to each of said input signals for driving all of said bi-state devices to their 0 states, means responsive to the switching of each of said bi-state devices from its l to its 0 state for restoring that device to its l state after a time delay which is less than the period between said recurring input signals, and means responsive to the switching of any of said bi-state devices from its l to its O state for creating a signal on the corresponding one of said output terminals.

7. In apparatus for selectively routing recurring input signals appearing on a first terminal to any one of a plurality of outputterminals, 'the combination comprising a plurality of bi-state devices each corresponding to one of said output terminals and adapted to reside in either a or 1 state, said bi-state devices normally residing in the 0 state, means for setting one of said bi-state devices in its l state according to a selected one of said output terminals which is to receive said signals, an interrogato line connected to said first terminal to receive said input signals, means including connections from said interrogate line to all of said bi-state devices for switching any one of such devices which is in the l state to the 0 state in response to each said input signal, a restore line, a time delay device interconnected between said input terminal and said restore line, means including connections from said restore line to all of said bi-state devices for switching any one of such devices which is in the 0 state to the 1 state in response to each delayed input signal, means responsive to switching of any of said bistate devices from a rst of said states to the second of said states for producing an output signal on the corresponding one of said output terminals, and means for clearing said bi-state devices prior to the next operation of said setting means.

8. in apparatus for selectively routing recurring input signals appearing on a first terminal to any one of a plurality of output terminals, the combination comprising a plurality of magnetic cores each corresponding to one of said output terminals, each of said cores having a substantially rectangular hysteresis characteristic and being susceptible of residing in 0 or 1 states represented by the direction of residual magnetism therein, said cores normally residing in the 0 state, means for setting a selected one of said cores to the 1 state to designate which of said output terminals is to receive signals, means for driving all of said magnetic cores to their "0 states in response to each input pulse appearing on said rst terminal, means responsive to switching of ilux in said selected core from the 1 state to the 0 state for restoring the said selected core to its 1 state, and means interconnecting each said core with the corresponding output terminal for creating a signal on the latter only in response to switching of that core from the 1 to the 0 state.

`9. In apparatus for selectively routing recurring input signals appearing on a first terminal to any one of a plurality of output terminals, the combination comprising a plurality of pairs of rst and second magnetic cores, each pair or cores corresponding to one of said plurality of terminals, each of said magnetic cores having a substantially rectangular hysteresis characteristic and being susceptible of residing in 0 or 1 states represented by the direction of residual magnetic flux therein, means for selectively setting to its l state the irst core of the pair of cores which corresponds to any seiected one of said plurality of terminals which is to receive signals, means responsive to each of said input signals for driving the iirst core in all of said pairs toward its 0 state, means responsive to switching of the first core in any of said pairs from tire l to the 0 state for switching the second core in that pair to the l state, means responsive to each of said input signals for driving the second core in all of said pairs toward the 0 state after a time delay which is shorter than the period between said recurring input signals, means responsive to the switching of the second core in any of said pairs for transmitting a signal to the corresponding one of said plurality of output terminals, and means responsive to the switching of any of said second cores from its l to its 0 state for switching the corresponding rst core from its 0 to its l state.

References Cited in the tile of this patent UNITED STATES PATENTS 2,800,596 Bolie July 23, 1957 2,803,812 Rajchman H Aug. 20, 1957 2,884,622 Rajchman Apr. 28, 1959 2,921,136 Cooke Jan. 12, 1960 2,923,333 Lawrence Feb. 2, 1960 2,930,029 Moore Mar. 22, 1960 2,932,013 Sager et al Apr. 5, 1960 2,988,653 Samusenko tune 13, 1961 3,015,806 An Wang et al. Ian. 2, 1962

Claims

1. IN APPARATUS FOR MEASURING OFF DIFFERENT SELECTED NUMBERS OF RECURRING INPUT SIGNALS RECEIVED FROM A SOURCE, THE COMBINATION COMPRISING A SCALING CHAIN HAVING A PLURALITY OF SCALING UNITS CONNECTED IN TANDEM RELATION WITH THE LAST SUCH UNIT HAVING AN OUTPUT TERMINAL, A PLURALITY OF INPUT TERMINALS LEADING TO DIFFERENT POINTS IN SAID SCALING CHAIN TO PROVIDE DIFFERENT OVER-ALL SCALING RATIOS FOR THE CHAIN, A PLURALITY OF BI-STATE DEVICES ADAPTED TO RESIDE IN EITHER "1" OR "O" STATES AND NORMALLY RESIDING IN THE "O" STATE, EACH OF SAID BI-STATE DEVICES CORRESPONDING TO ONE OF SAID INPUT TERMINALS, MEANS FOR SETTING ONE OF SAID DEVICES TO ITS "1" STATE ACCORDING TO THE PARTICLES SELECTED NUMBER OF SIGNALS WHICH IS TO BE MEASURED OFF, MEANS RESPONSIVE TO EACH OF SAID INPUT SIGNALS FOR DRIVING ALL OF SAID BI-STATE DEVICES TOWARD THEIR "O" STATES, MEANS RESPONSIVE TO THE SWITCHING OF EACH OF SAID BI-STATE DEVICES FROM ITS "1" TO ITS "O" STATE FOR RESTORING THAT DEVICE TO ITS "1" STATE AFTER A TIME DELAY WHICH IS LESS THAN THE PERIOD BETWEEN SAID RECURRING INPUT SIGNALS, MEANS RESPONSIVE TO THE SWITCHING OF ANY OF SAID BI-STATE DEVICES FROM ITS "1" TO ITS "O" STATE FOR CREATING A SIGNAL ON THE CORRESPONDING ONE OF SAID INPUT TERMINALS, AND MEANS RESPONSIVE TO A SIGNAL ON THE OUTPUT TERMINAL OF SAID SCALING CHAIN FOR CLEARING ALL OF SAID BI-STATE DEVICES TO THEIR "O" STATES WITHOUT TRANSMITTING A SIGNAL TO ANY OF SAID INPUT TERMINALS.