US3146135A - Four layer semiconductive device - Google Patents

Four layer semiconductive device Download PDF

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US3146135A
US3146135A US812433A US81243359A US3146135A US 3146135 A US3146135 A US 3146135A US 812433 A US812433 A US 812433A US 81243359 A US81243359 A US 81243359A US 3146135 A US3146135 A US 3146135A
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layer
junction
slice
current
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Sah Chih-Tang
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Clevite Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices

Definitions

  • Semiconductive devices including four layers forming three junctions have been described in the prior art.
  • the devices have two stable states: a low impedance high current state, and a high impedance low current state.
  • the devices are switched into the high impedance low current state when the current falls below a predetermined value and are switched into the low impedance high current state when the applied voltage reaches a predetermined breakdown or switching level. Gne application of such devices is in bistable switching circuits.
  • the breakdown voltage and holding currents for devices of the character described is usually controlled by controlling the thickness, the sheet resistance, the impurity concentration of the various layers forming the device and the impurity gradients at the junctions. It becomes relatively diilicult to construct devices having relatively low breakdown voltages with predetermined relatively low holding current characteristics due to the heavy doping and high impurity concentration gradients required. Another problem which arises is that ambient conditions elfect the high voltage junctions and deteriorate the devices voltage characteristics.
  • FIGURE 1 is a sectional view of a four layer, three terminal semiconductive device in accordance with the invention.
  • FIGURE 2 shows typical voltage-current characteristics for a semiconductive device of the type shown in FIGURE 1;
  • FIGURES SA-I show the steps in manufacturing a four layer semiconductive device in accordance with the present invention.
  • FIGURE 4 shows a two terminal, four layer semiconductive device in accordance with the present invention
  • FIGURE 5 shows a two terminal, two layer semiconductive device manufactured in accordance with the present invention
  • FIGURE 6 is a perspective view showing one contiguration of a semiconductive device in accordance with the present invention.
  • FIGURE 7 shows a semiconductive device in accordance with the present invention which is symmetrical about a line
  • FIGURE 8 shows a semiconductive device in accordance with the present invention which is symmetrical about a line
  • FIGURE 9 shows a semiconductive device in accordance with the present invention which is symmetrical about an axis
  • FIGURE l0 is a sectional view taken along the line 1tl*1 of FIGURE 9.
  • the semiconductive device illustrated in FIGURE 1 includes a first layer 11 of one conductivity type.
  • a second layer 12 of opposite conductivity type forms a rectifying junction therewith.
  • the second layer 12 includes a region of low impurity concentration 12a and a region of higher impurity concentration 12b.
  • a third layer 1d of said one conductivity type includes a portion which forms a junction with the region of high impurity concentration 12b and another portion which forms a junction with the region of low impurity concentration 12a.
  • a fourth layer 15 of opposite conductivity type forms a rectifying junction 16 with the third region.
  • ohmic contact 17 is formed with the region 15 and ohmic contact 18 is formed with the region 11.
  • ohmic contact 19 may be made to the region 12b.
  • the junction 102 has relatively low concentration gradient; thus, the breakdown voltage across this junction is relatively high.
  • the junction I C1 has a relatively high impurity concentration gradient and the breakdown voltage for this junction is relatively low.
  • the breakdown voltage for the four layer device is controlled by the concentration gradient of the junction I C1. This is controlled by the impurity concentration of the region 12b of layer 12 and of layer 13. It is sometimes preferable to outdifuse slightly after the completion of the diffused slice so that the highest concentration gradient region of the junction I C1 is beneath the surface and the breakdown current Hows more uniformly over the entire area of the junction I c1.
  • the breakdown voltage VB is controlled by controlling the concentration gradient at the junction Jol. It is observed that the curve 21 rises with increasing current.
  • the amount of rise can be controlled by controlling the Width D (FIGURE l) of the N-layer 14 between the two P layers, or by con-trolling the impurity concentraton of the layer 1d, or the width WN (FIGURE 1).
  • the ditused slice may be outdiffused in high vacuum so that the highest concentration gradient of junction JCI is moved inward from the surface to make the initial breakdown occur over a much larger junction area and thus less resistance (line 21) to the breakdown current can be obtained.
  • the junction JCI acts as an avalanche diode breakdown at a voltage which is dependent upon the concentration gradient at this junction region.
  • the breakdown current increases and spreads over the junction 16 and causes the alpha (current amplification ratio of the PN-P- transistor to increase.
  • the junction JC2 and the base layers 12a and 14 then play a predominant role in controlling the holding current IH and the characteristics of the device in the low impedance high current state (the on state).
  • Turn-off of the device occurs at a current slightly less than the holding current IH as shown by the dotted line (FIGURE 2).
  • the reason for slightly lower turn-off current is the fact that in the on condition most of the current flows in the region of low concentration gradient or high breakdown voltage.
  • the magnitude of the current due to recombination in the space charge layer is proportional to the space charge layer width which, in turn, is inversely proportional to the one-third power of the concentration gradient at the junction.
  • a slice of serniconductive material 31 of desired acceptor impurity concentration and thickness is formed by well known processes. For example, a silicon ingot having the desired acceptor impurity concentration is sliced and lapped to form slices of the desired thickness. The slice is then cleaned, such as by burning in an oxygen atmosphere at about 1300 C. for 10 to 15 minutes. This develops a silicon oxide film on the surface of the slice. The silicon oxide film is removed in a hydrouoric acid solution.
  • a donor impurity is predeposited on the surface. The predeposition may be carried out in a furnace having several temperature zones. The slice may be placed in a zone having a temperature of about 800 C.
  • Phosphorus oxide is placed in another zone of the furnace having a lower temperature, for example 200 C.
  • a carrier gas is caused to pass over the P205 into the relatively high temperature zone at a rate of between 150 and 250 cubic centimeters per minute in a typical size furnace.
  • the temperature of the first or high temperature furnace is selected to give the desired four point probe or sheet resistance for the N-type layers.
  • the temperature of the first furnace is dependent on the desired Q, the number of atoms of impurity per centimeter squared which it is desired to diffuse into the slice during preditfusion.
  • the phosphorus prediffuses into the slice a distance indicated by the layer 32.
  • FIGURE 3B The penetration is controlled largely by the temperature of the high temperature zone and the period of time that the slice is in the furnace.
  • a phosphorus silicon glass-like layer 33 is formed on the surface. Loose P205 (not shown) may be dispersed on the surface of this glasslike layer.
  • the layer 32 is about 0.05 micron in thickness and the glass-like layer 33 is greater than about 0.1 micron.
  • the next step in the process is to mask the slice and wash one surface.
  • the unmasked side of the slice is washed in hydrofluoric acid to remove the loose phosphorus and the phosphorus silicate glass-like layer 33 from the selected surface to provide a clean surface 34 (FIG- URE 3C).
  • the slice is then placed in a furnace and subjected to a diffusion process at a suitable temperature, for example, 1300 C.
  • a suitable temperature for example, 1300 C.
  • the phosphorus impurity is diffused further into the slice to a depth which is dependent upon the time the slice is held in the furnace and the temperature of the furnace.
  • the calculation of diffusion times and temperatures is well known in the art.
  • the resulting device is shown in FIGURE 3D.
  • the final thickness of the resulting upper N-type layer 36 is less than the thickness of the lower N-type layer 37.
  • the lower N-type layer has a constant phosphorus surface concentration or infinite phosphorus source from the glasslike layer 33 during the high temperature diffusion step.
  • the upper N-type layer has only a small constant phosphorus source from the prediused N-type layer 32. Consequently, the impurity concentration of the N-type layer 35 is less than the impurity concentration in the lower N-type layer 37.
  • the slice includes adjacent layers 36, 37 and 3S forming a pair of junctions.
  • the concentration gradient at the junction 39 may be less, equal or more than the concentration gradient at the junction 41 depending on the preditfusion and diffusion schedule due to the concentration dependence of the phosphorus impurity diffusion coefiicient in silicon.
  • the glass-like layer on the lower portion of the slice becomes thicker.
  • a silicon oxide layer is formed on the upper surface.
  • a step 42, FIGURE 3E, is formed on the upper surface.
  • the step has a depth such that no N-type material or a relatively thin N-type region 43 remains at the bottom of the step.
  • this region is less than about three microns in thickness.
  • a step of this type might be formed by mechanical operations such as grinding or lapping, or by chemical means such as etching. l'n the etching process the surface of the slice may be masked with suitable acid resist such as wax, and placed in an acid bath which etches away the upper oxide coating and the underlying N- region to the desired depth to form the step 42.
  • Wax, acid resist or the like is then removed from the surface of the slice.
  • the upper surface is masked and a longitudinal strip of wax or other resistive material is applied.
  • the slice is then washed in hydrofluoric acid to remove all of the oxide layer with the exception of the strip 44.
  • a structure of the type shown in FIGURE 3F results.
  • FIGURE 3F The structure shown in FIGURE 3F is then placed in a furnace and a predeposition and diffusion operation in the presence of acceptors, for example a B203 atmosphere, is carried out in a temperature of approximately 1200" C. for a predetermined period of time.
  • acceptors for example a B203 atmosphere
  • the boron is deposited and diffused into the upper surface of the slice; however, the boron is masked by the oxide strip 44 and the silicate glass-like coating 33.
  • Two spaced P type regions 45 and 46 are formed. The regions are separated by the N- region which extends to the upper surface beneath the strip 44. It is seen that the separation of the P region is controlled by controlling the width of the silicon oxide strip 44 and the depth of diffusion of the boron into the slice.
  • a boron silicate glasslike layer 47 is formed over all of the surfaces of the slice.
  • the rising portion of the step 42, and the surface of the slice in the vicinity of the strip 44 are masked 48, and the slice is etched to remove all of the oxide and glass-like layers except for the portion under the mask 48.
  • the slice is then nickel plated, FIGURE 3I, to form Ohmic contacts with the exposed surfaces, namely the P regions 45 and 46, and the N region 37.
  • the ends of the slice are chemically removed to form a structure of the type shown in FIGURE 3l. Suitable terminal leads 5l, 52 and 53 may then be connected to the ohmic contacts.
  • the length D which controls the resistance between the two P layers may be controlled by controlling the Width of Starting slice:
  • Wax mask
  • Nickel plate Apply and solder or alloy contacts. Etch on ends with CP-8 etch.
  • a device was formed having an overall thickness of 42 microns with step of 8 microns.
  • the thickness of the layers was as follows:
  • FIG- URE 4 A two terminal four layer device is illustrated in FIG- URE 4.
  • the step 42 is protected from the nickel plate by the silicon oxide.
  • a two terminal two layer device is shown in FIGURE 5.
  • the concentration gradient at the junction can be controlled to give the desired breakdown voltage characteristics.
  • a high concentration gradient junction 54 is formed between the P layer 56 and the N layer 57.
  • a low concentration gradient junction is formed between the N layer 57 and the P- layer 58.
  • the lower surface includes a P layer 59 for providing better ohmic contact.
  • FIGURE 6 shows the device of FIGURE l in a perspective. It is seen that the device, as shown, is a rectangular wafer having a step.
  • FIGURE 7 A device similar to thatl of FIGURE 6 but symmetrical about a line through its center is shown in FIGURE 7.
  • the device illustrated is a two terminal device.
  • FIGURE 8 shows another configuration symmetrical about a line.
  • FIGURE 9 shows a device similar to that shown in FIGURE 1 but which is symmetrical about an axis.
  • FIGURE 10 is a sectional view of the device shown in FIGURE 9. It is to be noted inthe device of FIG- URES 9 and 10 that the oxide layer 44 completely protects the ends of the high voltage junction so that no part of the junction is exposed to ambient conditions.
  • a four layer semiconductive device including a wafer of semiconductive material having first and second spaced faces comprising a iirst region of one conductivity type extending to the first surface, a second region of opposite conductivity type forming a junction with said rst region and extending to the second surface, said second region including a portion having a higher impurity concentration of said opposite conductivity type than the remainder of said second region and extending to the second surface, a third region of said one conductivity type forming a junction with the second region including the portion of higher impurity concentration, said third region defining a surface on said second surface in common with the surface of the second region, a fourth region of opposite conductivity type inset into the third region forming a junction with said third region, said fourth region defining a surface on said second surface in common with the surfaces of the second and the third regions, the end of the junctions between said second and fourth regions and the third region extending to said one surface.

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Description

CURRENT I 2 Sheets-Sheet l VOLTAGE CHIH-TANG sAH FOUR LAYER sEMcoNDU'cTIvE DEVICE Aug. 25, 1964 Filed May l1, 1959 FIG.
ug 25, 1964 CHIH-TANG sAH FOUR LAYER SEMICONDUCTIVE DEVICE Filed May l1, 1959 2 Sheets-Sheet 2 FIG. 6
FlG.' 7
l FIG. lo
u I CHIH-TANG sAH F l 8 y INVENTOR.
TORNEYS United States Patent O 3,145,135 F'UR LAYER SEMICNDUCTWE DEVICE Chih-tang Sah, Menlo Park, Calif., assignor, by mesne assignments, to Clevite Corporation, Cleveland, Ohio, a corporation of Ghio Filed May 11, 1959, Ser. No. 812,433 2 Claims. (Cl. 14S- 333) This invention relates generally to a semiconductive device and method of manufacturing the same.
Semiconductive devices including four layers forming three junctions have been described in the prior art. The devices have two stable states: a low impedance high current state, and a high impedance low current state. The devices are switched into the high impedance low current state when the current falls below a predetermined value and are switched into the low impedance high current state when the applied voltage reaches a predetermined breakdown or switching level. Gne application of such devices is in bistable switching circuits.
Une of the difliculties experienced in the fabrication of prior art four layer devices of the type described is that rapidly changing voltages applied across the same cause them to switch at voltages less than the switching or breakdown voltage. Furthermore, an increase in temperature causes rapid degradation of the breakdown voltage level.
The breakdown voltage and holding currents for devices of the character described is usually controlled by controlling the thickness, the sheet resistance, the impurity concentration of the various layers forming the device and the impurity gradients at the junctions. It becomes relatively diilicult to construct devices having relatively low breakdown voltages with predetermined relatively low holding current characteristics due to the heavy doping and high impurity concentration gradients required. Another problem which arises is that ambient conditions elfect the high voltage junctions and deteriorate the devices voltage characteristics.
It is a general object of the present invention to provide an improved semiconductive device and method of manufacturing the same.
It is another object of the present invention to provide a semiconductive device in which the breakdown or switching voltage is relatively independent of the rate of change of the applied voltage.
It is another object of the present invention to provide a four layer semiconductive device which includes a builtin avalanche diode serving to control the breakdown or switching voltage.
It is a further object of the present invention to provide a semiconductive device in which the breakdown or switching voltage can be controlled during manufacture within predetermined limits and in which the breakdown or switching voltage can be made relatively small.
It is another object of the present invention to provide a semiconductive device which has a relatively low breakdown voltage and holding current.
It is another object of the present invention to provide a semiconductive device whose characteristics are relatively immune to ambient conditions,
It is another object of the present invention to provide an improved method of manufacturing semiconductive devices.
These and other objects of the invention will become more clearly apparent from the following description when taken in conjunction with the accompanying drawing.
Referring to the drawing:
FIGURE 1 is a sectional view of a four layer, three terminal semiconductive device in accordance with the invention;
3,146,135 Patented Aug.A 25, 1 964 FIGURE 2 shows typical voltage-current characteristics for a semiconductive device of the type shown in FIGURE 1;
FIGURES SA-I show the steps in manufacturing a four layer semiconductive device in accordance with the present invention;
FIGURE 4 shows a two terminal, four layer semiconductive device in accordance with the present invention;
FIGURE 5 shows a two terminal, two layer semiconductive device manufactured in accordance with the present invention;
FIGURE 6 is a perspective view showing one contiguration of a semiconductive device in accordance with the present invention;
FIGURE 7 shows a semiconductive device in accordance with the present invention which is symmetrical about a line;
FIGURE 8 shows a semiconductive device in accordance with the present invention which is symmetrical about a line;
FIGURE 9 shows a semiconductive device in accordance with the present invention which is symmetrical about an axis; and
FIGURE l0 is a sectional view taken along the line 1tl*1 of FIGURE 9.
The semiconductive device illustrated in FIGURE 1 includes a first layer 11 of one conductivity type. A second layer 12 of opposite conductivity type forms a rectifying junction therewith. The second layer 12 includes a region of low impurity concentration 12a and a region of higher impurity concentration 12b. A third layer 1d of said one conductivity type includes a portion which forms a junction with the region of high impurity concentration 12b and another portion which forms a junction with the region of low impurity concentration 12a. There is formed a junction IC, which has a relatively high impurity concentration gradient and a junction IGZ which has a relatively low impurity concentration gradient. A fourth layer 15 of opposite conductivity type forms a rectifying junction 16 with the third region.
In a two terminal device, ohmic contact 17 is formed with the region 15 and ohmic contact 18 is formed with the region 11. In certain instances it may be desirable to provide a control voltage to the layer 12. For this purpose, ohmic contact 19 may be made to the region 12b.
It is noted that the junction 102 has relatively low concentration gradient; thus, the breakdown voltage across this junction is relatively high. On the other hand, it is noted that the junction I C1 has a relatively high impurity concentration gradient and the breakdown voltage for this junction is relatively low. Thus, the breakdown voltage for the four layer device is controlled by the concentration gradient of the junction I C1. This is controlled by the impurity concentration of the region 12b of layer 12 and of layer 13. It is sometimes preferable to outdifuse slightly after the completion of the diffused slice so that the highest concentration gradient region of the junction I C1 is beneath the surface and the breakdown current Hows more uniformly over the entire area of the junction I c1.
Referring to the voltage-current ditagram of FIGURE 2, the breakdown voltage VB is controlled by controlling the concentration gradient at the junction Jol. It is observed that the curve 21 rises with increasing current. The amount of rise can be controlled by controlling the Width D (FIGURE l) of the N-layer 14 between the two P layers, or by con-trolling the impurity concentraton of the layer 1d, or the width WN (FIGURE 1). Alternatively and additionally, the ditused slice may be outdiffused in high vacuum so that the highest concentration gradient of junction JCI is moved inward from the surface to make the initial breakdown occur over a much larger junction area and thus less resistance (line 21) to the breakdown current can be obtained. In essence, the junction JCI acts as an avalanche diode breakdown at a voltage which is dependent upon the concentration gradient at this junction region.
As soon as the junction I C1 breaks down and avalanche sets in, the breakdown current increases and spreads over the junction 16 and causes the alpha (current amplification ratio of the PN-P- transistor to increase. The junction JC2 and the base layers 12a and 14 then play a predominant role in controlling the holding current IH and the characteristics of the device in the low impedance high current state (the on state). Turn-off of the device occurs at a current slightly less than the holding current IH as shown by the dotted line (FIGURE 2). The reason for slightly lower turn-off current is the fact that in the on condition most of the current flows in the region of low concentration gradient or high breakdown voltage. The magnitude of the current due to recombination in the space charge layer is proportional to the space charge layer width which, in turn, is inversely proportional to the one-third power of the concentration gradient at the junction. Thus, in order to reach the current density corresponding to the total current IH through the area of the junction JC2 which is smaller than the total middle junction area JC1 and IC2, one must reduce the total current to a value below IH to turn the device off.
Referring to FIGURES 3A-I, the steps in forming a device in accordance with the invention are illustrated. A slice of serniconductive material 31 of desired acceptor impurity concentration and thickness is formed by well known processes. For example, a silicon ingot having the desired acceptor impurity concentration is sliced and lapped to form slices of the desired thickness. The slice is then cleaned, such as by burning in an oxygen atmosphere at about 1300 C. for 10 to 15 minutes. This develops a silicon oxide film on the surface of the slice. The silicon oxide film is removed in a hydrouoric acid solution. A donor impurity is predeposited on the surface. The predeposition may be carried out in a furnace having several temperature zones. The slice may be placed in a zone having a temperature of about 800 C. Phosphorus oxide is placed in another zone of the furnace having a lower temperature, for example 200 C. A carrier gas is caused to pass over the P205 into the relatively high temperature zone at a rate of between 150 and 250 cubic centimeters per minute in a typical size furnace. The temperature of the first or high temperature furnace is selected to give the desired four point probe or sheet resistance for the N-type layers. The temperature of the first furnace is dependent on the desired Q, the number of atoms of impurity per centimeter squared which it is desired to diffuse into the slice during preditfusion. The phosphorus prediffuses into the slice a distance indicated by the layer 32. FIGURE 3B. The penetration is controlled largely by the temperature of the high temperature zone and the period of time that the slice is in the furnace. During the prediffusion, a phosphorus silicon glass-like layer 33 is formed on the surface. Loose P205 (not shown) may be dispersed on the surface of this glasslike layer.
If the silicon slice is allowed to remain for thirty minutes in the high temperature zone at 800 C. with the P205 maintained at 230 C., the layer 32 is about 0.05 micron in thickness and the glass-like layer 33 is greater than about 0.1 micron.
The next step in the process is to mask the slice and wash one surface. The unmasked side of the slice is washed in hydrofluoric acid to remove the loose phosphorus and the phosphorus silicate glass-like layer 33 from the selected surface to provide a clean surface 34 (FIG- URE 3C).
The slice is then placed in a furnace and subjected to a diffusion process at a suitable temperature, for example, 1300 C. The phosphorus impurity is diffused further into the slice to a depth which is dependent upon the time the slice is held in the furnace and the temperature of the furnace. The calculation of diffusion times and temperatures is well known in the art. The resulting device is shown in FIGURE 3D.
By removing the glass-like layer on the surface 34, the final thickness of the resulting upper N-type layer 36 is less than the thickness of the lower N-type layer 37. The lower N-type layer has a constant phosphorus surface concentration or infinite phosphorus source from the glasslike layer 33 during the high temperature diffusion step. The upper N-type layer has only a small constant phosphorus source from the prediused N-type layer 32. Consequently, the impurity concentration of the N-type layer 35 is less than the impurity concentration in the lower N-type layer 37.
The slice includes adjacent layers 36, 37 and 3S forming a pair of junctions. The concentration gradient at the junction 39 may be less, equal or more than the concentration gradient at the junction 41 depending on the preditfusion and diffusion schedule due to the concentration dependence of the phosphorus impurity diffusion coefiicient in silicon.
During the diffusion operation the glass-like layer on the lower portion of the slice becomes thicker. A silicon oxide layer is formed on the upper surface.
A step 42, FIGURE 3E, is formed on the upper surface. The step has a depth such that no N-type material or a relatively thin N-type region 43 remains at the bottom of the step. Preferably, for very thin slices this region is less than about three microns in thickness. A step of this type might be formed by mechanical operations such as grinding or lapping, or by chemical means such as etching. l'n the etching process the surface of the slice may be masked with suitable acid resist such as wax, and placed in an acid bath which etches away the upper oxide coating and the underlying N- region to the desired depth to form the step 42.
Wax, acid resist or the like is then removed from the surface of the slice. The upper surface is masked and a longitudinal strip of wax or other resistive material is applied. The slice is then washed in hydrofluoric acid to remove all of the oxide layer with the exception of the strip 44. A structure of the type shown in FIGURE 3F results.
The structure shown in FIGURE 3F is then placed in a furnace and a predeposition and diffusion operation in the presence of acceptors, for example a B203 atmosphere, is carried out in a temperature of approximately 1200" C. for a predetermined period of time. The boron is deposited and diffused into the upper surface of the slice; however, the boron is masked by the oxide strip 44 and the silicate glass-like coating 33. Two spaced P type regions 45 and 46 are formed. The regions are separated by the N- region which extends to the upper surface beneath the strip 44. It is seen that the separation of the P region is controlled by controlling the width of the silicon oxide strip 44 and the depth of diffusion of the boron into the slice. A boron silicate glasslike layer 47 is formed over all of the surfaces of the slice. The rising portion of the step 42, and the surface of the slice in the vicinity of the strip 44 are masked 48, and the slice is etched to remove all of the oxide and glass-like layers except for the portion under the mask 48.
The slice is then nickel plated, FIGURE 3I, to form Ohmic contacts with the exposed surfaces, namely the P regions 45 and 46, and the N region 37. The ends of the slice are chemically removed to form a structure of the type shown in FIGURE 3l. Suitable terminal leads 5l, 52 and 53 may then be connected to the ohmic contacts.
It is seen that the resulting structure is of the type shown and described with reference to FIGURE 1. The length D which controls the resistance between the two P layers may be controlled by controlling the Width of Starting slice:
Thickness 42;*-1 micron. Resistivity 0.47 ohm-cm. Surfaces Lapped with 1950 grit SiC. Material Silicon. Cleaning:
Burn in 02 atmosphere at approx. 1300 C. for
10415 minutes. Dissolve SiO2 in hydroliuoric acid. Predisposition of P205:
High temp. zone (slice) 803 C. Low temp. zone (P205) 211 C. Time 0.50 hour. Four point probe resistance 30- L2 ohms.
Removal of Si02 and P205 glass from one surface:
Apply wax mask. Wash in hydrofluoric acid 20 minutes. Diffusion of donors:
Temperature 1300 C. Time 1.5 hours. V/I 0.24i0.04 ohm-cm. (a+), 4.2i0.3 ohm-cm. (n-). Etch step:
Wax mask.
Etch in concentrated HNOa with by volume of concentrated hydroiluoric acid for 80 seconds. Remove SiO2 and P205 glass to form strip:
Wax mask. Wash in hydrofluoric acid 3 minutes. Diffusion of acceptors (B203):
High temperature zone 1200 C. U Time 30 minutes.
Carrier gas N2. Four point probe resistance 0.66i0-02 ohm. Remove B203 glass, P205 glass, Si03:
Wax mask. Wash in hydrofluoric acid 5 minutes. Ohmic contacts:
Nickel plate. Apply and solder or alloy contacts. Etch on ends with CP-8 etch.
A device was formed having an overall thickness of 42 microns with step of 8 microns. The thickness of the layers was as follows:
Microns N 17.2i0.7 P- 13.0i1.1 N- 6810.4 P 4.1 |0.05
The voltage-current characteristics were as follows:
VB 7.4 volts. IH 2.9 ma. R 200 ohm (line 21, FIGURE 2).
The same device without built-in diode would have a breakdown voltage VB=50 volts.
A two terminal four layer device is illustrated in FIG- URE 4. By suitably masking during the last steps of the process, the step 42 is protected from the nickel plate by the silicon oxide.
A two terminal two layer device is shown in FIGURE 5. The concentration gradient at the junction can be controlled to give the desired breakdown voltage characteristics. A high concentration gradient junction 54 is formed between the P layer 56 and the N layer 57. A low concentration gradient junction is formed between the N layer 57 and the P- layer 58. The lower surface includes a P layer 59 for providing better ohmic contact.
FIGURE 6 shows the device of FIGURE l in a perspective. It is seen that the device, as shown, is a rectangular wafer having a step.
A device similar to thatl of FIGURE 6 but symmetrical about a line through its center is shown in FIGURE 7. The device illustrated is a two terminal device. FIGURE 8 shows another configuration symmetrical about a line.
FIGURE 9 shows a device similar to that shown in FIGURE 1 but which is symmetrical about an axis. FIGURE 10 is a sectional view of the device shown in FIGURE 9. It is to be noted inthe device of FIG- URES 9 and 10 that the oxide layer 44 completely protects the ends of the high voltage junction so that no part of the junction is exposed to ambient conditions.
Thus, it is seen that semiconductive devices having predetermined voltage current characteristics are provided. Improved two and four layer diodes having predetermined low breakdown voltages are provided. The oxide coating formed during diffusion is employed to protect the junctions of the device against the surrounds and ambient conditions.
I claim:
1. A four layer semiconductive device including a wafer of semiconductive material having first and second spaced faces comprising a iirst region of one conductivity type extending to the first surface, a second region of opposite conductivity type forming a junction with said rst region and extending to the second surface, said second region including a portion having a higher impurity concentration of said opposite conductivity type than the remainder of said second region and extending to the second surface, a third region of said one conductivity type forming a junction with the second region including the portion of higher impurity concentration, said third region defining a surface on said second surface in common with the surface of the second region, a fourth region of opposite conductivity type inset into the third region forming a junction with said third region, said fourth region defining a surface on said second surface in common with the surfaces of the second and the third regions, the end of the junctions between said second and fourth regions and the third region extending to said one surface.
2. A device as in claim 1 wherein an oxide layer formed before the formation of junctions between the second and the fourth regions and the third region covers the end of the junctions.
References Cited in the le of this patent UNITED STATES PATENTS 2,816,850 Haring Dec. 17, 1957 2,819,990 Fuller et al Jan. 14, 1958 2,861,018 Fuller et al Nov. 18, 1958 2,879,190 Logan et al Mar. 24, 1959 2,890,142 Kroger et al. June 9, 1959 2,899,344 Atalla et al Aug. 11, 1959 2,911,539 Tanenbaum Nov. 3, 1959 2,915,647 Ebers et al. Dec. 1, 1959 2,930,722 Ligenza Mar. 29, 1960 2,954,307 Shockley Sept. 27, 1960 2,959,504 Ross et al Nov. 8, 1960 2,980,830 Shockley Apr. 18, 1961 3,079,512 Rutz Feb. 26, 1963 OTHER REFERENCES Journal of the Electrochemical Society, May 1959, Aschner et al., relied on; pages 415-417.

Claims (1)

1. A FOUR LAYER SEMICONDUCTIVE DEVICE INCLUDING A WAFER OF SEMICONDUCTIVE MATERIAL HAVING FIRST AND SECOND SPACED FACES COMPRISING A FIRST REGION OF ONE CONDUCTIVITY TYPE EXTENDING TO THE FIRST SURFACE, A SECOND REGION OF OPPOSITE CONDUCTIVITY TYPE FORMING A JUNCTION WITH SAID FIRST REGION AND EXTENDING TO THE SECOND SURFACE, SAID SECOND REGION INCLUDING A PORTION HAVING A HIGHER IMPURITY CONCENTRATION OF SAID OPPOSITE CONDUCTIVITY TYPE THAN THE REMAINDER OF SAID SECOND REGION AND EXTENDING TO THE SECOND SURFACE, A THIRD REGION OF SAID ONE CONDUCTIVITY TYPE FORMING A JUNCTION WITH THE SECOND REGION INCLUDING THE PORTION OF HIGHER IMPURITY CONCENTRATION, SAID THIRD REGION DEFINING A SURFACE ON SAID SECOND SURFACE IN COMMON WITH THE SURFACE OF THE SECOND REGION, A FOURTH REGION OF OPPOSITE CONDUCTIVITY TYPE INSET INTO THE THIRD REGION FORMING A JUNCTION WITH SAID THIRD REGION, SAID FOURTH REGION DEFINING A SURFACE ON SAID SECOND SURFACE IN COMMON WITH THE SURFACES OF THE SECOND AND THE THIRD REGIONS, THE END OF THE JUNCTIONS BETWEEN SAID SECOND AND FOURTH REGIONS AND THE THIRD REGION EXTENDING TO SAID ONE SURFACE.
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260902A (en) * 1962-10-05 1966-07-12 Fairchild Camera Instr Co Monocrystal transistors with region for isolating unit
US3287182A (en) * 1963-09-25 1966-11-22 Licentia Gmbh Semiconductor arrangement
US3298082A (en) * 1963-05-14 1967-01-17 Hitachi Ltd Method of making semiconductors and diffusion thereof
US3328651A (en) * 1963-10-29 1967-06-27 Sylvania Electric Prod Semiconductor switching device and method of manufacture
US3337374A (en) * 1963-11-27 1967-08-22 Int Standard Electric Corp Semiconductor device having p-n junction defined by the boundary between two intersecting semiconductor layers
US3337750A (en) * 1963-05-14 1967-08-22 Comp Generale Electricite Gate-controlled turn-on and turn-off symmetrical semi-conductor switch having single control gate electrode
US3383568A (en) * 1965-02-04 1968-05-14 Texas Instruments Inc Semiconductor device utilizing glass and oxides as an insulator for hermetically sealing the junctions
US3404451A (en) * 1966-06-29 1968-10-08 Fairchild Camera Instr Co Method of manufacturing semiconductor devices
US3476618A (en) * 1963-01-18 1969-11-04 Motorola Inc Semiconductor device
US3491434A (en) * 1965-01-28 1970-01-27 Texas Instruments Inc Junction isolation diffusion
US3664893A (en) * 1964-10-23 1972-05-23 Motorola Inc Fabrication of four-layer switch with controlled breakover voltage
FR2207360A1 (en) * 1972-11-17 1974-06-14 Matsushita Electronics Corp
DE2610942A1 (en) * 1976-03-16 1977-09-29 Licentia Gmbh METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH ELEMENT UNITS MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY
US4062032A (en) * 1973-05-29 1977-12-06 Rca Corporation Gate turn off semiconductor rectifiers
US4109274A (en) * 1975-11-05 1978-08-22 Nikolai Mikhailovich Belenkov Semiconductor switching device with breakdown diode formed in the bottom of a recess
US4329707A (en) * 1978-09-15 1982-05-11 Westinghouse Electric Corp. Glass-sealed power thyristor
US4631561A (en) * 1983-07-29 1986-12-23 Sgs-Ates Componenti Elettronici Spa Semiconductor overvoltage suppressor with accurately determined striking potential
US4698655A (en) * 1983-09-23 1987-10-06 Motorola, Inc. Overvoltage and overtemperature protection circuit
US4742377A (en) * 1985-02-21 1988-05-03 General Instrument Corporation Schottky barrier device with doped composite guard ring

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2816850A (en) * 1953-12-30 1957-12-17 Bell Telephone Labor Inc Semiconductive translator
US2819990A (en) * 1956-04-26 1958-01-14 Bell Telephone Labor Inc Treatment of semiconductive bodies
US2861018A (en) * 1955-06-20 1958-11-18 Bell Telephone Labor Inc Fabrication of semiconductive devices
US2879190A (en) * 1957-03-22 1959-03-24 Bell Telephone Labor Inc Fabrication of silicon devices
US2890142A (en) * 1954-04-01 1959-06-09 Philips Corp Asymmetrically conductive device
US2899344A (en) * 1958-04-30 1959-08-11 Rinse in
US2911539A (en) * 1957-12-18 1959-11-03 Bell Telephone Labor Inc Photocell array
US2915647A (en) * 1955-07-13 1959-12-01 Bell Telephone Labor Inc Semiconductive switch and negative resistance
US2930722A (en) * 1959-02-03 1960-03-29 Bell Telephone Labor Inc Method of treating silicon
US2954307A (en) * 1957-03-18 1960-09-27 Shockley William Grain boundary semiconductor device and method
US2959504A (en) * 1958-05-26 1960-11-08 Western Electric Co Semiconductive current limiters
US2980830A (en) * 1956-08-22 1961-04-18 Shockley William Junction transistor
US3079512A (en) * 1959-08-05 1963-02-26 Ibm Semiconductor devices comprising an esaki diode and conventional diode in a unitary structure

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2816850A (en) * 1953-12-30 1957-12-17 Bell Telephone Labor Inc Semiconductive translator
US2890142A (en) * 1954-04-01 1959-06-09 Philips Corp Asymmetrically conductive device
US2861018A (en) * 1955-06-20 1958-11-18 Bell Telephone Labor Inc Fabrication of semiconductive devices
US2915647A (en) * 1955-07-13 1959-12-01 Bell Telephone Labor Inc Semiconductive switch and negative resistance
US2819990A (en) * 1956-04-26 1958-01-14 Bell Telephone Labor Inc Treatment of semiconductive bodies
US2980830A (en) * 1956-08-22 1961-04-18 Shockley William Junction transistor
US2954307A (en) * 1957-03-18 1960-09-27 Shockley William Grain boundary semiconductor device and method
US2879190A (en) * 1957-03-22 1959-03-24 Bell Telephone Labor Inc Fabrication of silicon devices
US2911539A (en) * 1957-12-18 1959-11-03 Bell Telephone Labor Inc Photocell array
US2899344A (en) * 1958-04-30 1959-08-11 Rinse in
US2959504A (en) * 1958-05-26 1960-11-08 Western Electric Co Semiconductive current limiters
US2930722A (en) * 1959-02-03 1960-03-29 Bell Telephone Labor Inc Method of treating silicon
US3079512A (en) * 1959-08-05 1963-02-26 Ibm Semiconductor devices comprising an esaki diode and conventional diode in a unitary structure

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260902A (en) * 1962-10-05 1966-07-12 Fairchild Camera Instr Co Monocrystal transistors with region for isolating unit
US3476618A (en) * 1963-01-18 1969-11-04 Motorola Inc Semiconductor device
US3298082A (en) * 1963-05-14 1967-01-17 Hitachi Ltd Method of making semiconductors and diffusion thereof
US3337750A (en) * 1963-05-14 1967-08-22 Comp Generale Electricite Gate-controlled turn-on and turn-off symmetrical semi-conductor switch having single control gate electrode
US3287182A (en) * 1963-09-25 1966-11-22 Licentia Gmbh Semiconductor arrangement
US3328651A (en) * 1963-10-29 1967-06-27 Sylvania Electric Prod Semiconductor switching device and method of manufacture
US3337374A (en) * 1963-11-27 1967-08-22 Int Standard Electric Corp Semiconductor device having p-n junction defined by the boundary between two intersecting semiconductor layers
US3664893A (en) * 1964-10-23 1972-05-23 Motorola Inc Fabrication of four-layer switch with controlled breakover voltage
US3491434A (en) * 1965-01-28 1970-01-27 Texas Instruments Inc Junction isolation diffusion
US3383568A (en) * 1965-02-04 1968-05-14 Texas Instruments Inc Semiconductor device utilizing glass and oxides as an insulator for hermetically sealing the junctions
US3404451A (en) * 1966-06-29 1968-10-08 Fairchild Camera Instr Co Method of manufacturing semiconductor devices
FR2207360A1 (en) * 1972-11-17 1974-06-14 Matsushita Electronics Corp
US3961354A (en) * 1972-11-17 1976-06-01 Matsushita Electronics Corporation Mesa type thyristor and its making method
US4062032A (en) * 1973-05-29 1977-12-06 Rca Corporation Gate turn off semiconductor rectifiers
US4109274A (en) * 1975-11-05 1978-08-22 Nikolai Mikhailovich Belenkov Semiconductor switching device with breakdown diode formed in the bottom of a recess
DE2610942A1 (en) * 1976-03-16 1977-09-29 Licentia Gmbh METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH ELEMENT UNITS MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY
US4118257A (en) * 1976-03-16 1978-10-03 Licentia Patent-Verwaltungs-Gmbh Method for producing a semiconductor device having monolithically integrated units in a semiconductor body
US4329707A (en) * 1978-09-15 1982-05-11 Westinghouse Electric Corp. Glass-sealed power thyristor
US4631561A (en) * 1983-07-29 1986-12-23 Sgs-Ates Componenti Elettronici Spa Semiconductor overvoltage suppressor with accurately determined striking potential
US4698655A (en) * 1983-09-23 1987-10-06 Motorola, Inc. Overvoltage and overtemperature protection circuit
US4742377A (en) * 1985-02-21 1988-05-03 General Instrument Corporation Schottky barrier device with doped composite guard ring

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