US3131376A

US3131376A - Security-line-surveillance system

Info

Publication number: US3131376A
Application number: US92483A
Authority: US
Inventors: Vall Wilbur E Du
Original assignee: Electrada Corp
Current assignee: Electrada Corp
Priority date: 1961-03-01
Filing date: 1961-03-01
Publication date: 1964-04-28
Anticipated expiration: 1981-04-28

Description

April 28, 1964 w. E. DU VALL 3,131,376

SECURITY-LINE-SURVEILLANCE SYSTEM Filed March l, 1961 7 Sheets-Sheet l April 28, 1964 w. E. DU VALL sEcURITY-LINE-SURVEILLANCE SYSTEM 7 Sheets-Sheet 2 Filed March l, 1961 arme/V545 April 28, 1964 w. E. DU VALL 3,131,376

SECURITY-LINE-SURVEILLANCE SYSTEM Filed March l, 1961 7 Sheets-Sheet I5 April 28, 1964 w.'E. DU VALL 3,131,376

sEcuRITY-LINE-SURVEILLANCE SYSTEM BY ma April 28, 1964 w. E. DU VALL sEcURITY-LINE-SURVEILLANCE SYSTEM '7 Sheets-Sheet 5 Filed March l, 1961 lNvENToR. M50? z/ WAL www m W. E. DU VALL SECURITY-LINE-SURVEILLANCE SYSTEM Apri-12s, 1964 7 Sheets-Sheet 6 Filed March 1, 1961 April 28, 1964 w. E. DU VALL 3,131,376

SECURITY-LINE-SURVEILLANCE SYSTEM Filed March 1, 1961 'I sheets-sheet 7 u u e0 kw kN gwg United States Patent O 3,131,376 'SECURITY-LINE-SURVEILLANCE SYSTEM Wilbur E. DuVall, Gardena, Calif., assignor, by mesne assignments, to The Electrada Corporation, Los Angeles, Calif., a corporation of Delaware Filed Mar. 1, 1961, Ser. No. 92,483 13 Claims. (Cl. 340-147) This invention relates to electrical circuit arrangements for maintaining the security of desired premises, and, more particularly, for improvements inline supervisor circuits employed therewith.

Many useful devices have been devised to aid in the physical protection of important facilities from tire, trespass, vandalism, sabotage, and other acts, and in the safeguarding of documents and materials from access by unauthorized persons. Other ingenious apparatus has been developed to take the place of guards at points of egress to and from restricted areas, and to provide alarm in the event of their violation. Many of these devices and apparatuses, while in some respects superior to their human counterparts, frequently suffer from a common weakness, namely, theV relative ease with which their alarm circuit can be breached. This is particularly true of those devices which depend on wire lines between a remote site and the central control location. Though numerous schemes using tone patterns, codes, and other arrangements have been tried to protect such lines from the ordinary malefactor, they have not given great pause to the trained A technician.

An object of this invention is the provision of a system for supervising security lines whichrenders such lines inviolable. t

Another object of this invention is to provide a security line supervisory system which is novel and useful.

Yet another object of the present invention is the provision of an improved security line system for transmitting signals to a remote location and for receiving answerback signals from that location.

These and other objects of the invention may be achieved in an arrangement wherein signals are generated randomly at a central location from which supervision of remote locations is desired. These randomly generated signals actuate counters, one of which sets up an interval for transmitting signals. This interval varies ,from transmission cycle to transmission cycle. Pulses oc- .the results of the count into pulses and thereafter into representative sine-wave trains which are sent back to the transmitter, or central location, to be counted and compared with the results of the count which occurred during `the immediately preceding transmitting interval at the central location.

alarm circuit.

To further increase the diiiiculty attendant to trying to break the security of the system, the original count at the Any difference is used to actuate an 4central location is made in Vbinary form. The pulses sent to the remote location arecounted by a binary counter. In the transmission from the remote location, the count of the binary counter is read out in scrambled form, so that the signals being sent back to the central location are further coded. At the central location, the original binary count in the preceding transmitting interval is ice held in a binary counter. The coded binary signals are applied to a combination comparator-and-unscramble gate, which converts them into a binary count for the purposes of comparison with the count at the central location.

The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention itself, both as to its organization and method of operation, as well as additional objects and advantages thereof, will best be understood from the following description when read in connection with the accompanying drawings, in which:

FIGURE l is a block diagram showing a security layout which employs this invention; l Y

FIGURE 2 is a block diagram of centralstation equipment in accordance with this invention;

FIGURE 3 is a block diagram of a remote-station equipment in accordance with this invention;

' FIGURE 4 is a block diagram of a security layout employing this invention which has a plurality of remote locations beingrmonitored;

FIGURE 5 is a circuit diagram of an oscillator amplitude-control circuit and a keyed audio oscillator circuit suitable for use with this invention;

FIGURE 6 is a circuit diagram of a line network and gated audio receiver suitable for use with this invention;

FIGURE 7 is a circuit diagram of a comparator-andunscramble-gate circuit used in a central unit in accordance with this invention;

FIGURE 8 is a circuit diagram of scramble-gate circuits suitable for use in a remote unit in accordance with this invention; and

FIGURE 9 is a circuit diagram of sequence gates and counters suitable for use in a receiving unit in accordance with this invention.

The invention to be described basically consists of a signal-generator transmitter and receiver which is located at security headquarters and which is connected over three lines or over two lines and ground and to a remote unit located at the area to be monitored. 'The remote unit also has a receiver, transmitter, and scrambling device whereby the signals received from the central unit at security headquarters are scrambled and then transmitted back to the device at security headquarters over the connecting wires, where they are' unscrambled and matched with the signals originally transmitted. The feature of this system that makes it tamper-proof is that a break-in or tampering with any portion of thev system, once it has been set into operation, causes an operation of an alarm. The system, however, does require the addition of a detector of a suitable type for monitoring the area to determine whether an unwanted presence, such as a human being, or an object, or smoke is within that area. Such detector isy not a part of this invention. Detectors of this type are well known and can comprise, for example, television cameras, smoke detectors, photocell equipment, etc. Such detector can actuate a remote unit in a manner so that the central unit will actuate the alarm.

Referring now to FIGURE l, there may be seen a block diagram of a security layout which employs this invention. This will comprise a central unit 2 and an alarm device 4, which are located at the security oilce. These are connected eitherl by two wires 6A, 6B and ground, or alternativelyV by three wires to a remote unit 8 which is located at the area desired to be monitored for an unwanted presence. An unwanted presence detector 9, which can be, as previously mentioned, a photoelectric monitoring device, or motion detector, etc., has a relay 9A and relay contacts 9B. Under normal conditions, the contacts 9B are closed by the relay coil 9A, whereby the line 6B connecting the remote unit 8' to the central unit 2 is closed'. When an unwanted presence is detected,

then the relay 9A is rendered inoperative, whereby one of the lines is opened up.

As will become apparent subsequently herein, the opening of one of the lines connecting the remote central Aunit is only one very simple way whereby the unwanted-pres-l ence detector can coact with the apparatus in accodance with this kinvention for actuating an alarm at the security ndice. The unwanted-presence detector can coact in many other ways to cause the remote unit to enable the central lunit to operate the alarm. This may be done, for eX- 'ample, by interrupting the power supply, by inserting a pulse signal on the lines, etc. Those skilled in the electronics art will have no diiculty in recognizing other arrangements.

FIGURE 2 is a block diagram exemplifying apparatus employed at a central station in accordance with this invention. This includes a random-noise generator 10, which emits signals at random. The output of the random-noise generator is applied to the inputs of a nip-flopV circuit 12 and a continuously running blocking oscillator 14. The random-noise generator output serves to successively drive the flip-nop between its set and reset states. The random-noise generator output causes the blocking oscillator output to have some time jitter. The set state Output of the i-lip-op 12 is applied toga iirst gate 16 and to an oscillator amplitude-control circuit 18. The

voutput of the blocking oscillator 14 is applied to a rst gate 16 and to a second gate 20. The iirst gate 16 has a third input, which is an Yinhibit input. This third input is applied from a ilip-op circuit 22 when in its reset state. The second input to the second gate 20 is the output of the flip-hop circuit 22 when in its set state.

The gate 16 will be enabled, or closed, to pass pulses from the blocking oscillator 14 in the presence of a setstate output from the Hip-iiop 12. The output of gate 16 is applied to another flip-flop 24 to successively drive it between its set and reset states. The output of the flipiiop 24, when in its set state, is applied to the oscillator amplitude-control circuit 18. The output of the flip-flop 24, when in its reset state, is applied to a delay flip-nop 26, to a ring counter 28, and also to abinary counter 30. The output of the oscillator amplitude-control circuit 18 is applied to a keyed audio oscillator circuit 32, to control the amplitude of the oscillations thereof as well as the time when oscillations are to occur. The output of the keyed audio oscillator circuit 32 is applied to a line network and set amplifier 34. This network transmits output from the audio oscillator circuit over wires 36A, 36B and also applies any signals received over the two-wire line to a gated audio receiver 38.

The set output of the flip-flop 22 is employed to render the gated audio receiver responsive to pulses received over the line network 34, which otherwise does not respond thereto. The output of the gated audio receiver is applied to a comparator-and-unscramble gate 40 for the purpose of comparing in response to output from a ring counter 42 the received train of signals with the contents of the binary counter 30. A delay flip-flop 44 advances the ring counter 42 in response to each output received from the gate 20. The output of the ring counter 42 when in its sixth or last count condition is applied to reset flip-flop 22. The output of the ring counter V42 when in 'its first count condition resets a ip-op 46. The output of the ring counter 42 when in its fourth count condition may be applied to set this flip-Hop 46 when a momentary switch 48 is actuated. Switch 48 is closed only when this system is initially put into operation.

The output of the ip-op 22 when driven to its set state is applied to a ring counter 48, to advance it one count in response thereto. Each time the ring counter 48 advances one count, the sequence gates 5t) changes the base to which ring counter 28 counts. Alternatively expressed, the function of the ring counter 48 and the sequence gates 50 is to change the count of ring counter 28, at which it will illeach time the ring counter .48

advances one count. The output of ring counter 28 when in its one count condition is applied to gate 52 to enl able it to transmit an outputv of the delay ip-op 26 to the flip-op 22 to drive it to its set state.

Binary counter 30 and ring counter 48 are set to an initial count condition in response to the output'of a delay Hip-flop 54 which is driven by the output of the ip-lop 46 when in its set state. This output of the flip-ilop 46 when driven to its set state, by operation of switch 48, is also applied to the line network and set arnpliiier 34 to be transmitted to a remote station between oneof the lines 36A, 36B and ground, for thepurpose of setting that remote station to an initial operating con-V dition. The lines 36A, 36B correspond to the lines 6A, 6B in FIGURE 1.

An alarm circuit S6, which may either be audible or visible, or both, is actuated by the output of comparator 40 when that output indicates that there is a diierence between the count in the binary counter 30 and the signals being received from a remote sending unit.

A review of the operation of the system is as follows. The random-noise generator 10 successively drives flipilop 12 between its set and reset states, thus effectively providing a random-pulse train from the set output of the ip-op. The blocking oscillator 14 is a continuously running one, whose output pulses, however, are slightly jittered in time as the result of the random-noise generator signals being applied to the blocking oscillator 14 input. Gate 16, which receives the set output of flip-op 12 and the output of blocking oscillator 14, can provide an output only upon the simultaneous occurrence of its inputs. This output, therefore, will also comprise a randompulse train, wherein the leading and trailing edges of the pulses are time-jittered. VFlip-,flop 24 is driven between its set and reset states in response to the output from the gate 16. Thus it, too, is a randomly driven circuit providing random outputs. Y

' The set output of the Hip-flop 12 is applied to the oscillator amplitude-control circuit 18, to be integrated.l The set output of the flip-flop 24 is applied to the oscillator amplitude-control circuit for the purpose of turning on the keyed audio oscillator circuit each time such output is present. The amplitude at which such keyed audio oscillations are emitted is determined by the amplitude to which the set output of nip-flop 12 has been integrated at the time that the set output of the Hip-flop 24 is present. Thus, the output of the keyed audio oscillator circuit will consist of sine-Wave trains having different amplitude and time-jittered beginnings and endings. Each of these sine-wave trains corresponds to a pulse having an arbitrarily varying length or duration, and, furthermore, the occurrence of such sine-Wave train is random, just like the occurrence of the pulse (set output of ip-op 12) from which it is derived. This output of the keyed audio Yoscillator circuit 32 is the one which is applied to the lines 36A, 36B to be transmitted to a remote receiving network.

The output of the nip-flop 24, when in its reset state, is used -to drive a delay flip-flop 26, a ring counter 28, as well as the binary counter 30. Delay flip-flop 26 provides a delay suicient to insure that gate 52 will transmit the signal received from the ring counter 28, which, in response to the same signal, is being driven back to its initial count condition. As previously indicated, the count capacity of ring counter 28 is varied at each cycle of operation, in response to the settings of the sequence gates 50, made previously. The ones of the sequence gates which are selected to control the count of the ring counter 28 are determined by the count of ring counter 48.

Thus, assume by way of illustration, that a sequence of count capacities for ring counter 28 consists of 5-3-4. Ring counter 48 is put in its initial count condition in response to the output of delay flip-flop 54. Thereafter, ring counter 28 will count to tive and then be returned to its initial state. This time the gate 52 is enabled to drive the flip-dop 22 to its set state. This will serve to inhibit the gate 16, whereby the gated audio oscillator circuit 32 will no longer transmit oscillation trains, the ring counter 48 is driven to its second count state, and the gate 20 is enabled to pass pulse outputs from the blocking oscillator 14 to the delay flip-op 44, the output of which is used to advance counter 42. The gated audio receiver 38 is enabled to receive and idetect any incoming sine-wave trains transmitted by a remote station over lines 36A, 36B,'converting them to pulses and applying them to the comparator 40 in the sequence in which they are received. Ring counter 42 is advanced in response to the output of the blocking oscillator 14, which is continuously running and which is received through the now-closed gate 20 and delay flip-flop 44. The delay flip-flop serves the function of compensating for any delays which may occur in the passage of the signals received over the two- Wire line through the gated audio receiver 38.

The comparator-and-unscramble gate 40 has a separate comparing gate for each one of the count states of the binary counter 30 and the ring counter 42, of which there are an equal number. Thus, the output of the gated audio receiver 38 is applied to all of these gates in the comparator 46, while each successive count of the ring counter 42 enables each successive gate to compare successively the pulse pattern presented by the output of the binary counter 30 with the pulse pattern detected by the gated audio receiver 38. Any dilference between the two is applied by the comparator 4t), to actuate the alarm circuit S6.

When the ring counter 42 attains its full count condition, it applies an output to reset hip-hop 22, as the result vof which gate 20 is closed and the inhibit signal is withdrawn from gate 16. Also, the enabling input to the gated audio receiver 3S is removed, whereby the receiver Vis rendered insensitive to any signals applied to its input. The arrangement shown in FIGURE 2 is then in its trans- -mitting mode, whereupon the ring counter 28 and binary -counter 30 are once again actuated and will continue to count as long as the sequence gates 50 permit ring counter 28 to advance. Using the example previously given, ring counter 28 will till when it attains its third count and will then return to its initial count condition. Binary counter 30, however, holds the three count and compares this with the sequence of pulses next received from the remote system.

It would appear from the foregoing description that va predetermined count is established by the structures including the counter 28, sequence gates 59, and the counter 48. The duration of the interval over which this Ypredetermined count occurs is a variable one, since it is determined by the output of the random-noise generator 1t). The predetermined count, however, only determines the number of pulses which occur over a variable interval of time. The width of these pulses, as Well as the .spacing therebetween, is variable within the variable interval of time. In response to these pulses, the oscillator amplitude-control circuit 18 and the keyed audio oscillator 32 are enabled to transmit sine-wave trains having a duration on the order of these pulses, but having an amplitude which is variable.

The transmitted signals are received at a remote receiver, which effectively stores these received signals until the transmitter terminates the transmitting cycle which occurs when the ring counter 28 attains the predetermined count. At this time, the remote receiver transmits back signals representative of the signals received,

-modifed by information stored at the remote location.

These' representative signals are compared when received with the count in the binary counter 30. An identity doesl not operate the alarm circuit. The termination of the receiving interval is indicated by the ring counter 42 attaining its full count. The system then is set into its ,transmit mode.

FIGURE 3 is a block schematic diagram of a remo-te station in accordance with this invention. The output pulse from the reset ilip-llop 46 in FIGURE 2, which can be called a starting pulse, is received by a line network 60, which is identical with a line network 34 and which is connected to the two

Wire lines

32A and 32B and to ground. The line network 60 has its output connected to a detector and amplifier 62, which detects and amplies the starting pulse. The output of the detector and amplier 62 is applied to a ring counter 66, to place it in its initial count condition, to a ip-flop 68, to place it in its initial count condition, to a ring counter 70, to place it in its initial count condition, and, also, to a binary counter 72, to place it in its initial count condition. The receiver circuitry shown in FIGURE 3 and the transmitter circuitry shown in FIGURE 2 are now in identical starting states.

The central station then begins to send the sine-wave trains over the

lines

32A and 32B, and the line network 60 applies these to the gated audio receiver 74. This `receiver is enabled to receive these sine-wave signals and convert them to pulses, and these pulses are applied to the ring counter 66, to the binary counter 72, and to a delay flip-flop 76. The ring counter 66, as well as the binary counter 72, have their counts advanced in response to these pulses, when they occur. The count to which ring counter 66 can count is determined by the sequence gates 78, which, in turn, are controlled by a ring counter 80. The structural combination of ring counter 66, sequence gate 78, and ring counter 80 are identical and operate identically as the combination of the respective ring counter 28, sequence gate 50, and ring counter 48 in FIGURE 2. It is required that the interconnections of these structures. be made identical, so that the count to which ring counter 66 can advance before returning to its initial count state is the same as that to which ring counter 2S can advance for each count of the respective ring counters 80 and 48. Thus, the ring counter 80 and a sequence gate 78 will be interconnected in a manner so that the ring counter 66 will rst attain a live count before being reset; then, on the next receiving interval (for the remote station), it attains a three count before being returned to its initial state; and, thereafter, it attains a four count.

When ring counter 66 attains its initial or rst count state, it applies an output to the gate 82. The delay ip- V ilop 76 delays the pulse, which returns the ring counter 66 to its initial state. The output of the delay flip-flop 7) can pass through the now-open gate 82 to the flip-flop 68, to drive it to its set state. In response thereto, the ring counter is advanced one count, the gated audio receiver 74 is biased oif so it will no longer respond to signals received from the line network, and the gated blocking oscillator 83 is enabled to commence emitting pulses. These pulses are time jittered by the output of a random-noise generator 86, which is applied to the Vgated blocking oscillator 84.

The output of the random-noise generator 86 is also applied to a flip-Hop circuit 88, to successively drive it between its set and reset conditions. Each set output of flip-flop 88 is applied to an oscillator amplitude-control circuit 90, which functions identically to the oscillator amplitude-control circuit 18 in FIGURE 2. The randompulse output of dip-flop 88 is integrated by a circuit in Vcircuits to a coded representation.

the output of the gated audio receiverA 74. Otherwise, no pulse is emitted. Each time a pulse is emitted by one of the scramble-gate circuits, a Schmitt trigger circuit 94 is actuated to shape the emitted pulse and apply it to the oscillator amplitude-control circuit 90. The output of the Schmitt trigger circuit 94 controls, through the oscillator amplitude control, a keyed audio oscillator 96, which serves the same function as the keyed audio oscillator circuit 32 in FIGURE 2. Instead, flip-flop 8S is analogous to llip-op 12 in FIGURE 2. Schmitt trigger 94 is analogous to flip-dop 24 in FIGURE 2 with respect to their operations in controlling the oscillator amplitude-Control circuit 90 and the keyed audio oscillator 96.

The amplitude of the oscillations emitted by the keyed -audio oscillator is determined by the level of the integrated output of the flip-flop 88. Whether or not the keyed audio oscillator is turned on is determined by the presence or absence of an output from the Schmitt trigger circuit 94. The number of times the Schmitt trigger circuit 94 is turned on is determined by the number to which the binary counter 72 is advanced. This, of course, is determined by the number of sine-wave trains which were received. The interval over which these pulses are returned is determined by the frequency of the gated blocking oscillator 84 which is made substantially identical in frequency with the frequency of oscillation of blocking oscillator 14 in FIGURE 2.

It may be pointed out at this time that the scramblegate circuits 92 may be interconnected so that there is no one-to-one corroboration between the ring counter 70 and binary counter 72, in order to further insure security of the system. That is, when ring counter 70 counts to its second count, for example, it need not read out the second stage of binary counter 72, but the last stage, instead; when it counts to its third count, it can read out the first stage of binary counter 72, etc. The important factor to bear in mind is that the readout interval is fixed by the frequency ofthe gated blocking oscillator 84 and the capacity of the ring counter 70. Since the counter 72 is a binary counter, its output is a binary representation of the number of pulses applied to its input. This binary representation is further modified by the scramble-gate Thus, the number of pulses returned from the remote unit to the central unit are not the same.l In this manner, anyone attempting to detect the signals on the line will not know whether pulses are being transmitted from the central location or from the remote location.

When the contents of the binary counter'72 have been read out and transmitted, ring counter 70 has attained its full count condition and drives flip-flop 68 to its reset state. This, again, enables the gated audio receiver to receive pulses being transmitted over the line, and gated blocking oscillator 84 is deactivated. The circuit shown in FIGURE 3 is then in its receiving mode of operation.

At the central unit in FIGURE 2, the comparator-andunscramble gates 40 are interconnected between the binary counter 30 and the ring counter 42 in a manner similar to the scramble-gate circuits 92 to binary counter 72 and ring counter 70, so that the incoming pulses from the receiver will present a proper pulse pattern for comparing sequentially with the pulse pattern of the binary counter, where no tampering with the line has occurred.

FIGURE 4 is a block diagram of an arrangement for a security layout which employs this invention and which has a plurality of remote locations to be monitored. At each remote location, there is required a

remote unit

100, 102, which is shown and described in FIGURE 3. At

vthe security headquarters, however, apparatus of the type .enclosed in the dotted rectangle of FIGURE 4 is required.

8 ble-gate circuit 110. An alarm112 is actuated'by'the comparator whenever it detects a difference between signals received from the remote unit 100 and those which were transmitted to the remote unit in the immediately preceding transmitting cycle. y

For remote unit No. 2, there is also provided a line network 114, which is connected to remote unit 102 over lines 116A, 116B.- The line network output is applied to a gated audio receiver 118. The output of the gated audio receiver is applied to a comparator-and-unscramblegate circuit 120. An alarm 122 is actuated whenever the comparator detects a dilerence between the signals sent to the remote unit 102 and those received in response thereto.

A single central unit 124 is provided for all remote locations. This central unit contains all the apparatus shown in FIGURE 2 exclusive of the additional apparatus shown in FIGURE 4 required for each one of the remote units. The output from the central unit 124 will consist of audio signals during the transmitting interval which are applied over a line 126 to both

line networks

104, 114 for transmission to both

remote units

100, 102. There is also provided a line 12S, which will enable the gated audio receivers 10S, 118 during the receiving interval to receive signals transmitted from the remote unit, respectively 100, 102. Otherwise, as in the description of the operation of the central unit in FIGURE 2, the gated

audio receivers

108, 118 are inoperative.

Another output from the central unit 124 comprises an output on a group of lines designated by 130, which comprise the gate-pulse output from the ring counter 42 in FIGURE 1. The nal required output from the central unit is the output from the binary counter 30 in FIG- URE 2, on a group of lines designated by reference numeral 132. Both of these outputs are applied to the comparator-and-unscramble gates, respectively 110, 120. These outputs Ycomprise the'gating signals and the binarycounter pulse pattern, which is compared with the incoming signals from the respective remote units for the purpose of determining whether something untoward has occurred or whether there is an unwanted presence at the remote unit.

Considering the block diagram of FIGURE 2 again, circuits such as the random-noise generator 10, the

llipllops

12, 22, 24, and 46, the delay flip-

ops

26, 44, and 54,

gates

16, 20, and 52, the ring counter 42, and the binary counter 30 are very well known in the electronic art, their use and connections are known, and they are described in numerous publications, and are commercially purchasable. Accordingly, these circuits will not be described in detail herein, since such description would merely add to the length of this disclosure Without contributing to its clarity.

FIGURE 5 is a circuit diagram of an oscillator ampli- -tude-control circuit, such as represented by the rectangle 18 in FIGURE 2 or 90 in FIGURE 3, and of the keyed vaudio oscillator circuit, such as represented by the rectangle 32 in FIGURE 2 or 96 in FIGURE 3. recalled that the pulse outputs from the flip-flop 12 in It will be FIGURE 2 are integrated by the amplitude-control circuit 18, and, upon the Voccurrence of the set output from the ip-ilop 24, the amplitude level attained by the integrated youtput of flip-flop 12 determines the amplitude of the oscillations which are then permitted to be transmitted over the duration of the set output pulse of the Hip-flop 24. Similarly, for the receiver, the output of flip-flop V88 Yis integrated, but no output is obtained from the keyed audio oscillator 96 until a pulse is received from the Schmitt trigger 94. Atthis time, the level of the integrated signal determines the level of the oscillations which are emitted 'by the keyed audio oscillator over the interval of the pulse from the Schmitt trigger circuit 94.

Terminal serves as the input to the amplitudecontrol circuit from Hip-liep 12 or from ip-flop 88. Terminal 142 serves'as the input to the oscillator amplituale-control circuit from nip-nop 24 or from trigger circuit 94. Any input applied to the terminal 140 is applied through a resistor 142 across a capacitor 144 and also to the base of a transistor 146. The capacitor 144 serves to integrate the input received from either flip-flop 12 or ilip-op S8. Transistor 146 is connected in typical emitter-follower fashion, Thus, the Voltage to which capacitor 144 is charged by the application of a pulse from the preceding liip-iiop is established by transistor 146 across the emitter load resistor 148 and thus is applied to the emitter of transistor 152. A source of operating potential 150 is provided, and the collector of transistor 146 is connected thereto.

The transistor 152 has its emitter connected to the emitter of transistor 146 and its base connected through a capacitor 154 to the terminal 143. The collector of transistor 152 is connected to the collector of a transistor 156. The code-pulse-input terminal 143 is also connected to the base of transistor 156 through a resistor 158, in parallel with the capacitor 160. The collector of transistor 152 and transistor 156 is connected to the base of transistor 162. Transistor 162 has its collector connected to the source of operating potential 156 and its emitter connected to the base of a transistor 164 and through a resistor 166 to the emitter of transistor 164. The collector of transistor 164 is connected to the collector of transistor 162. Two series resistors 168 and 176 serve as the load for the emitter of transistor 164.

Transistors

162 and 164 are connected as emitter-followers and are normally conducting.

It should be noted that transistor 152 is of the NPN type, while

transistors

146, 156, 162, and 164 are of the PNP type. Transistor 156 in the quiescent state of the circuit is also maintained conducting by virtue of a bias potential applied to its base through resistor S (terminal 143 is negative when there is no code pulse-quiescent state). Resistors 172 and 174 form a voltage divider to provide a bias to transistor 156 to insure that transistor 156 will be nonconductive when a positive pulse (code pulse) is applied at terminal 143. A capacitor 176 is connected across resistor 174. A capacitor 178 is connected between the collector and emitter of transistor 166.

A pulse applied to terminal 140 is integrated by capacitor 144. In response to the leading edge of a code pulse applied to terminal 143, transistor 152 is rendered conductive to thereby turn off transistor 156. The level of the voltage across capacitor 144 at the time of arrival of the code-pulse leading edge is transferred to capacitor 178 from the emitter of transistor 146 through transistor 152. In response to this charge on capacitor 178, transistor 162 together with transistor 164 will become increasingly conductive, dependent upon the level to which the capacitor is charged. This, of course, depends upon the level of the voltage which is across capacitor 144. An output from

transistors

162 and 164 is derived from the junction of resistors 168 and 17 0. At the termination of the leading edge of the code pulse, transistor 156 becomes conductive, whereupon the voltage across capacitor 178 is discharged through the collector-emitter path of transistor 156. The circuit is then ready for another operating cycle.

The operation described for the oscillator amplitudecontrol circuit is that the input from the noise flip-liep is integrated, and, upon the occurrence of a code pulse, the amplitude to which the noise iiip-iiop input has been integrated is transferred to the output of the circuit during the interval of the code pulse. The oscillator circuit effectively comprises four

transistors

189, 182, 184, and 196.

vTransistors

182 and 184 are respectively of the NPN and PNP type, and each will amplify the opposite halves of the output received from transistor 180. The collector of transistor 18) is connected to the base of transistor 182 and to the base of transistor 184. A frequency-determining feedback path, consisting of a bridged- T network 19t), is connected from the junction of a resistor 186, which is connected to the emitter of transistor 184, and a second resistor 188, which is connected to the emitter of transistor 182 to the base of transistor 186. A transistor 196 acts as a positive-feedback amplier necessary for oscillation.

The oscillator does not oscillate unless a signal is applied to the collector of transistor 196. The amplitude-control circuit supplies operating potential to the positive-feedback amplifying transistor 196. The amplitude of the oscillations is determined by the amplitude of this signal, and the time over which oscillations occur is determined by the duration of the signal. The output of the oscillator amplitude-control circuit is applied from the resistors 168, 178 to the collector of the transistor 196, providing operating potential for transistor 196 and determining the amplitude of its response to the signal supplied to its base. The circuit commences oscillations in the presence of a positive feedback. These oscillations are applied through a capacitor 204, which is connected to the junction of

resistors

186, 188, and from thence both to the output terminal 266 and to the base of transistor 196 through a resistor 288 and a capacitor 210. Thus, the oscillation intensity of the oscillator, as well as the duration or interval over which it occurs, is determined by the output from the junction of resistors 168 and 178. The oscillator output, which is applied to the terminal 206, is transmitted in the manner and for the purposes described above.

Reference is now made to FIGURE 6, which is a circuit diagram of a line network and a gated audio receiver suitable for use with either the central unit or remote unit of this invention. The line network comprises a transformer 220 having a center-tapped primary winding 220P and a secondary winding 2208. The outer two terminals of the primary winding 2261 are connected to the line wires, respectively 36A, 36B. The center tap connects to the delay ip-iiop 54 in FIGURE 2 and to the detector and amplifier 62 (FIGURE 3) at the remote location. Any incoming signals over the lines are fed from the primary 228? to the secondary winding 2288. The keyed audio oscillator, either in the central or in the remote units, feeds oscillations to the secondary 2288 of the transformer through a resistor 222. In such circumstances the secondary winding acts as a primary Winding, and the primary winding acts as a secondary winding to apply the audio signals to the line.

The output of the secondary winding is applied to the base of a transistor 224 for amplification. The collector vof this transistor is coupled to the base, respectively, of an NPN transistor 226 and a PNP transistor 228 for amplifying both halves of the incoming sine waves further. The emitters of

transistors

226 and 228 are connected together through resistors 230 and 232. The circuitry following the junction of the resistors 230, 232, comprising a capacitor 234 connected in series with a resistor 236, and a magnetic core 238, having a centertapped winding 239 thereon with one end connected to resistors 236, the center tap connected to ground, and the other end connected through an input network to a following transistor 248, all serve to co-operate to provide a sharp spike each time the sine-wave signal applied to the network passes through zero. This spike is applied through

coupling networks

241, 243, respectively, to

transistors

242 and 240. These PNP transistors have their emitters connected together and to gifound'. Their collectors are also connected together and coupled to a following NPN transistor 244. The collector of this transistor 244 is connected to the emitter of a PNP transistor 246, and the emitter of transistor 244 is connected through a resistor to the source of operating potential. The collector of transistor 246 is connected through a load resistor 248 to ground. Accordingly, the emitter-collector path of transistor 246 is in series with the collector of transistor 244. Thus, transistor 246 serves as a gate for transistor 244, which can be controlled by signals applied to the base of transistor I l 1 246 to hold the gate open and then close it or to hold the gate closed and then open it. When the gate transistor 246 is closed, then the signals applied to the base of transistor 244 may be derived from the collector of transistor 246 across the resistor 24S and applied to the base of a succeeding transistor 250.

Transistors

254 and 264 serve as bias voltage stages, supplying a portion or the supply voltage, but with Very low impedance to the

respective transistors

252, 258.

The transistor 252 serves to charge the capacitor 254 at a constant rate. TheY capacitor 254 is connected across the collector-emitter of transistor 250, and thus, when transistor 250 is Vrendered conductive by one of the vampliiied spike signals from the preceding portion of the amplifier, it discharges capacitor 254. A transistor 256, which is connected in emitterfollower fashion, has its base connected to the capacitor 254, and thus its output Vfollows the voltage across capacitor 254. The transistor 256 is connected to a succeeding transistor 25S, which amplies and clips the signals from the emitter-follower transistor 256 and applies them to two

transistors

260, 262, which are connected in Schmitt trigger-circuit fashion.

The circuit described effectively insures that the frequency of the signals applied to the input of the audio receiver must have a predetermined value, that of the keyed audio oscillator; otherwise, the audio receiver will not respond properly to these signals and cause actuation of the alarm at the security headquarters. The introduction of signals at any other audio frequency than that determined previously by the frequency of the oscillator causes malfunctioning of the system. This can be recognized from the fact that the capacitor 254 charges up at a constant rate from the transistor 252. Should audio signals having a higher frequency than that predetermined for the key audio oscillator of the system be introduced, then transistor Y250 will discharge capacitor 254 before it can charge up to a level sufcient to trigger the Schmitt trigger circuit, and no output will be available from the receiver. Should the audio signals applied to the receiver have a frequency lower than that which has been predetermined for the keyed audio oscillator, then the Schmitt trigger circuit at the output of the amplier will not be operated at the proper frequency, and synchronism with therring counter, which operates the comparator and unscramble gates, and the alarm will be actuated.

The output from both sides of the Schmitt trigger circuit is applied to a pair of output terminals 264, 266. YIt will be noted that the output terminal 264 is connected to the collector of transistor 260, and the output terminal 266 is connected to the collector of transistor 262. Thus, these terminals will have one potential value (for example, v-3 and -ll Volts, respectively) when the Schmitt trigger circuit is not actuated, and this potential value will be interchanged when the Schmitt trigger circuit is actuated. The length of time that the Schmitt trigger circuit is actuated, and accordingly the width of its pulse output, is determined by the duration of a given sinewave train applied to the input of the receiver. It will be recalled that each pulse originally generated results in a sine-Wave train having a duration equivalent to the duration of the pulse. Thus, the output of the Schmitt trigger comprises pulses having the same Width as the originally generated pulses which are passed for transmission.

FIGURE 7 is a circuit diagram of a comparator-andunscramble-gate circuit suitable for use with the circuitry shown in FIGURE 2 for a scramble-gate circuit suitable for use with the circuitry shown in FIGURE 3. Considering, first, the arrangement required for the comparator unscramble gate 4t?, it will be seen that the input to the circuit comprises potentials applied to terminals 26S, 270 (FIGURE 7) from the respective terminals 264, 266 (FIGURE 6) which are connected to the outl2 'puts' from the Schmitt trigger circuit. Another input Vcomprises the outputs of the ring counter 42, which, in the example selected, was assumed t0 have four outputs. vThese outputs, indicated by the

numerals

1, 2, 3, 4 in FIGURE 2, are respectively applied to the terminals 271, 272, 273, 274 in FIGURE 7.

A third input applied to the comparator-and-unscramble gate 40 comprises the output of the binary counter 30. To assist in the understanding of the circuit, the binary counter 30 is represented in block diagram form in FIG- vURE 7 by the four flip-flops, respectively 30A, 30B, 30C, and 30D. A reset-pulse input line 276 can reset these ipops to any predetermined state, not necessarily the state in which they all represent a zero count. The input to the binary counter is applied to the iirst nip-flop 30A in the sequence of flip-Hops. Each one of the flip-ops is driven from the preceding Hip-flop from one to the other of its states of stability. Thus, flip-iiop 30A, when driven from its set to its reset state, drives flip-op 30B, which, Vin turn, when driven from its set to its reset state, drives ilip-op 30D. It is believed that the operation of a binary counter is well known and further explanation here is not required. The counter is driven from the output of ipflop 24 in FIGURE 2 or from the output of the receiver 74 in FIGURE 3.

An output may be derived from both stages of each flip-flop. These are designated for the respective flip-

nop circuits

30A, 30B, 30C, 30D by the letters A, A', B, B', C, C', and D, D'. The primed letters represent the outputs taken from the set-representative stage of a flip-flop, and the remaining letters represent the output taken from the reset stage of the flip-llop. These outputs are applied to the correspondingly identied terminals A, A', B, B', C, C', and D, D' of the comparator circuit. It should thus become apparent that whatever count is entered into vthe binary counter 30, the flipflops 30A through 30C assume their respective set and reset stable states representative of that count, and, further, their outputs provide a pulse pattern representative of that count which is applied to the comparator circuit.

Five transistors are associated with each count of the ring counter. It will be seen that terminal 271 connects to the base of a transistor 280A. The emitter of this transistor connects to a common emitter line and through a resistor 282 to a source of negative potential 290. The collector of transistor 280A is connected to the emitters of two transistors, respectively 292A, 294A. The base of transistor 292A is connected through a common line to the terminal 270, and the base of transistor 294A is connected through another common line to the terminal 268. It will be recalled that these terminals receive the outputs from the Schmitt trigger circuit at the output of the audio receiver. The collectors of the respective transistors 292A, 294A are connected to the emitters of transistors 296A, 298A. The junctions made by these collector-emitter connections are connected to the source of operating potential 290. The base of transistor 296A is connected to terminal A; the base of transistor 298A is connected to terminal A. The collector of transistor 296A and the collectorof transistor 298A are connected to a common line, which is connected to the base of anNPN transistor 300. The collector of this transistor is grounded, and its emitter is connected through two series-connected resistors, respectively 302, 304, to the source of negative potential 290. The junction of these two resistors is connected to the control electrode of a silicon-controlled rectifier 306. A source of operating potential is applied across the anode and cathode of the silicon-controlled rectifier 306, and its output is applied to a warning device. A warning signal may also be taken vfrom the emitter of transistor 300 at the terminal 308.

The terminal 272 is connected to a transistor 280B, similarly connected as transistor 230A to transistors 292B, 294B. The transistors 292B and 294B are connected as transistors292A and 294A are connected to transistors 13 2%3, 298B. Transistors 296B and 298B are similarly interconnected as transistors 296A and 298A. However,

terminal D' is connected to the base of transistor 296B, and terminal B is connected to the base of transistor 298B. This connection is made in anticipation of the scrambled binary signal which will be received from the gated audio receiver over the lines connected to the remote unit.

Terminal 273 is connected to the base of a transistor 280C. This transistor together with the transistors 292C, 294C, 296C, and 298C are all identically connected together, as are transistors 289A, 292A, 294A, 296A, and

298A. However, the base of transistor 296C is connected to terminal B', and the base of transistor 298C is connected to terminal C.

Terminal 272 is connected to transistor 289D. Transistor 280D together with transistors 292D, 294D, 296D, and 298D are all identically interconnected, as are transistors 286A, 292A, 296A, and ZSA. However, the base of transistor 296D is connected to terminal C', and the base of transistor 298D is connected to terminal D.

Assume, now, that a binary count has been entered into the counter 3d, as a result of which a voltage pulse pattern is applied to the terminals A, A', B, B', C, C', D, D', representative of that binary count. Assume, further, that the scramble-gate circuits of the remote unit are providing an output which is being received at the central unit. Ring counter 42 counts to its rst state, in response to which an input is applied over terminal 271 to the base of transistor 280A. This transistor can become conductive at this time. If the proper potentials are applied to terminals 26S, 279 from the output of the gated audio receiver in response to the signals received over the lines 36A, 36B, then these signals are applied to the bases of transistors 292A, 294A.

Proper signals must also be applied from the binary counter -to terminals A' and A, such that no conductive path will exi-st, either through series-connected transistors 296A, ZJQA, and 280A, or through series-connected transistors 2813A, 294A, and transistor ZtltlA. If such conductive path exists, then fthe base of transistor 3% is driven positive and it is rendered conductive. VIn response to this, the silicon-controlled rectifier 306 is triggered and actuates the Warning device.

The other sets of tive transistors associated with each count yof the ring counter :and with the binary counter opera-te in a similar manner as that described. The transistor driven from the ring coun-ter is enabled to conduct, |but the pat-tern of the voltages applied to the bases of the `two transistors connected to the terminals driven from the audio receiver and the two transistors connected to the two output terminals of the binary counter must be such that no conducting path is provided.

In an embodiment of the invention which was built, by Way of a specific example, the output of the first sta-ge of the counter 30A was -3 volts at the A-termina-l and ll vol-ts at the A-terminal. At lthis time, with the Schmitt trigger circuit in its actuated state, the voltage applied to the ibase of transistor 292 from terminal 270 was -lfl volts, and that applied tc the base of

transistor

2,94 from terminal 268 was --3 volts. Thus, transistors Q96 and 294 are unable to conduct. The warning device is not triggered. However, should an interchange occur so that 1111 volts is applied to the bases of transistors i292 and 296 or -11 volts is applied to the bases of

transistors

2,4 and 2%, then a currentconduetive path exists through three series-connected transistors lwhereby current is drawn thro/ugh the common collector line and through the co1 mon collector load resistor 3d() connected to the operating- [potential source 290. This causes the base of transistor 38% to rise in poten-tial, whereby transistor 39d is rendered From the foregoing description, it should be apparent how the circuit including the binary counter 30, comparator-and-unscram le .gates 4h, ring counter 4Z, and keyed audio oscillator 32 function to compare the incoming sig- 'nal-s with the sign-al pattern stored in the binary counter,

which is scrambled in anticipation of the manner the incoming signals lare scrambled, whereby decoding in addition to unscrarnbling occurs. If there is a dissimilarity, then, of course, the monitor is actuated.

FIGURE 8 is a circuit diagram of a scramble-gate arrangement suitable lfor use in `a remote unit and which is represented by a rectangle 952, in IFIGURE 3. The purpose of the scramble gate is to provide a pulse for every stage oi the binary counter 72 which is -in its set, or onerepresentative, state, and not to provide a pulse for every stage of the binary counter 72 which is in its rese-t, or zero-representative, state. Thus, it is only necessary to check one of the two sides of each stage in the, binary counter. Accordingly, each terminal 320, 3&2, $24, and 326 is connected to la diiierent one of the flip-liep stages in, the binary counter 72. In order to enable the unscranilbling circuit shown in FIGURE 7 to unscramble the output from the circuit shown in FIGURE 8, terminal -322 would be connected to the irst stage of the bin-ary counter, terminal 324 would be connected t-o the fourth stai-ge oi the binary counter, and terminal-s 324 and $26 would be respectively connected to the second and third stages of the binary counter in the remote unit. Furthermore,

terminals

3120, 324, and 326 are connected to the one-representative sides of their respective sta-ges, and terminal 322 is connected to the Zero-representative side o-f the `fourth stage.

Terminals

32S, 330, 362, and 334, respectively, are connected to the tirs-t, second, third, and fourth `outputs ci the ring counter 7l)l in FIGURE 3.

Tenminal 326 is connected to the base of a transistor '336. Terminal 3&8 is connected -to the base of a transistor 33S. These two transistors are effectively connected in series, so that only in the presence of Ian input to both of their bases can conduction take place through their series-connected collector-emitter paths. Similarly, terminal 322 is connected to the base of transistor- 340; terminral 530 is connected to the base of a transistor 342; terminal 32l4 is connected to the base of `a transistor 344; terminal 3312 is connected to the base of a transistor 34,6; termin-al 32.6 is connected to the Ibase of a transistor 348; and terminal 334 is connected to the base of a transistor 359i.

Transistors I336i, '340, 3414, and 348 have their collectors connected Itogether land to a common-collector load resistor 352. The common-collector connection is also made to the lbase of a transistor 354, which is connected together with a transistor S56 to form a Schmitt trigger circuit. This is a Schmitt trigger circuit 94 in `FIGURE 3.

The emitters of all 'the transistors 33S, 34-2, 346 and 353 are connected together and through a resistor 360 to ground. The oper-ation of the scrambling circuits is extremely simple, as previously indicated, upon the first count output of the ring counter 32,3 and terminal 320 '-being connected to the side of the first stage of the binary counter which is in its set state. Transistors 3138 and 336 are `rende-red conductive, whereupon a signal is applied to the ibase of the transistor 3154-, and the Schmitt trigger circuit is actuated to apply a pulse to the base or" the transistor 362. This transistor iarnpliiies that pulse and applies it to the output terminal 364. This terminal is connected to the oscillator amplitude-control circuit 90.

The ring counter sequentially applies a signal to each one of the

terminals

32,8, 330, 33-2, and 3M. Thus, the transistors, respectively 33-8, 342, 346, and 350, are enabled to become conductive and will conduct, provided that the transistors with which they are in series are enabled to cond-uct. As previously described, this results in the count presentation of the binary counter being scmned and scrambled rand applied to the Schmitt trigger for transmission as oscillation trains back to the central unit.

FIGURE 9 is a circuit diagram of the ring counter and sequence gates, which may be employed in both the remote unit as well as in the central unit. It should be recalled that the operating cycle of one of these ring counters is controlled by the connections made through sequence gates to a second, or controlling, ring counter. In FIGURE 2, the controlling ring counter is represented by a rectangle 48 and the controlled ring counter by rectangle 28, and the sequence gates have the reference numeral 50. In FIGURE 3, the controlling ring counter bears reference numeral 80, the controlled ring counter bears reference numeral 66, and the sequence gate bears reference numeral 78. In FIGURE 9, the controlling ring counter includes an input terminal 370, which receives pulses from either flip-hop 22 in the central unit or from flip-flop 68 in the remote unit. The input terminal is connected to a driving transistor 372, which amplies the input and applies it to drive the following counter.

The controlled and controlling counters, as will become more apparent from the following description, are substantially identical with respect to the construction of each stage thereof. The differences which make for the operation described are achieved by the differences in interconnecting these stages. An input terminal 374, which has pulses applied thereto, either from the iip-flop 24 in the Vcentral unit or from the gated receiver 74 in the remote unit, is connected to an amplifying transistor 376, This transistor applies its output to all the stages of the counter which follow. In the controlling counter, there are two transistors per stage, respectively 378A, 378B, 380A,

380B, 382A, 382B, 384A, 384B, and 336A, 386B. In the controlled counter there are two transistors per stage, re-

vspectively

388A, 388B, 390A, 399B, 392A, 392B, 394A,

394B, 396A, 396B. In both counters, the count is represented by the location of the stage having both its transistors conducting. All other transistors in the counter are turned oit. In the controlled counter, the two conducting transistors provide a bias, so that upon the application of a pulse to be counted to all the stages of the counter, only the succeeding-stage transistors will become conductive, and the transistors which are conductive at that time are turned olf. In the controlled counter, a similar description generally applies; however, it is the effectY of the controlling counter upon the gates which determines whether the count advances or the counter is reset to its initial counting condition.

A description of one stage of the controlling counter follows. It will be apparent that the remaining stages thereof are identical, and thus such description for the initial stage should suice to clarify the circuits of the remainder. The transistor 378A is an NPN transistor, and the transistor 378B is a PNP transistor. The collector of the transistor 378A is connected through a resistor 38 to positive operating potential. The collector is also connected through a resistor 400 to the base of transistor 378B. The base of transistor 373B is also connected to the positive operating-potential source through a resistor 402. A capacitor 404 connects the collector of transistor 378A to the base of transistor 378B. A capacitor 4436 is connected between the collector of transistor 378A and the base of transistor 380A. The emitter of transistor 378A is connected in common with the errritter of

transistors

380A, 382A, and 384A to a resistor 408, and thence to a source of negative-bias potential.

The base of transistor 378A is connected to the source of negative potential through a resistor 410. The base is also connected through a resistor 412 to the collector of transistor 378B. A capacitor 414 connects the base of transistor 378A to the collector of transistor 378B. A capacitor 414 is connected from the collector of transistor 386A to the base of transistor 378A. Effectively, this capacitor 414 connects the last stage of the counter to the rst stage, so that it may operate as a ring counter. The emitter of transistor 378B is connected in common with the emitters 380B, 332B, 384B, and 386B to the collector of transistor 372.Y Thus, the driving pulse from the amplifying transistor 372 is applied to allV these emitters. This driving pulse is negative and thus operates to turn oif conduction of the conducting transistor 378B, whereby a negative pulse is applied through capacitor 414 from the collector of transistor 373B to the base of transistor 378A, tending to drive it off, with the result that a further pulse is applied through capacitor 44 from the collector of transistor 378A to the base of transistor 378B to insure the turn-off. A positive pulse is also applied from the collector of transistor 373A through capacitor 406 to the base of transistor 380A to drive it into conduction. Effectively, the collector base coupling betweenI transistors of the succeeding stage assists in the buildup of conduction in both transistors, just like it assists in the cutoif of conduction in both transistors.

The ve stages of the controlling ring counter are interconnected by capacitors, such as 466, so that in response to each succeeding input pulse, that stage is rendered conductive, which succeeds a preceding stage which is already conductive.

The interconnections within each stage of a controlled counter are identical with those described for the controlling ring counter, and it is therefore believed need not be repeated here. However, the interconnections between each stage of the controlled ring counter are diierent and are etectuated by means of gates which are controlled from the ring counter. Consider, for example, the rst or resting stage of the controlled counter, including transistors 396A and 396B. The collector of transistor 396A is connected to two capacitors, respectively 420A, 420B. The capacitor 426B connects to a junction 422B, to which there is connected a diode 424B and a resistor 426B. The resistor 426B connects to a terminal 428B. The diode 424B connects to a junction 436B. A resistor 432B is connected to this junction, and, also, this junction is connected through a capacitor 434 to the base of the transistor 394A, which is in the succeeding stage of the count- The capacitor 420A connects to a junction 422A. A resistor 426A connects this junction to a terminal 428A. A diode 424A couples this junction to a common line 436, which is connected to all such similarly positioned diodes in the remaining gates. This common line is connected to a capacitor 438, which is coupled to the base of transistor 396A, the transistor Within the initial or resting stage of the counter.

The remaining sequence gates have the same structure and internal connections as the first gate just described. However, of course, a second one of the sequence gates has the junction 440, which corresponds to the junction 430B, coupled through a capacitor 442 to the base of a transistor 392A, which is within the third stage of the counter. A third gate has the junction 444, corresponding to the junction 436B, coupled through a capacitor 446 to the base of transistor 390A, which is within the fourth stage of the counter. A fourth gate has the junction 448, corresponding to the junction 430B, connected through a capacitor 450 to the transistor 388A, which is within the fth stage of the counter. A capacitor 452 is coupled from the collector of the transistor 338A through the bus 436 back to the initial counter stage through capacitor 438. Thus, eifectively, the controlled counter is also a ring counter.

Each gate has two terminals, respectively 428A, 423B, 454A, 454B, 456A, 456B, 458A, 458B, which can be respectively connected to the collectors of the A and B transistors in each stage of the controlling counter, to establish the count in the controlled counter for any given count in the controlling counter. Thus, for the purposes of illustrating the operation of the arrangement shown in FIGURE 9, assume that terminal 456A is connected to the collector of transistor 382A and terminal 456B is connected to the collector of transistor 382B. Assume, further, also, that the

terminals

454A and 454B are respectively connected to the collectors of transistor 384A and transistor 384B, and terminals 428A and 428B are respectively connected to the collectors of transistor 386A and 386B. Assume, further, that the count in the controlling counter has progressed until the third stage, which includes the

transistors

382A and 382B, is conducting. Assume, further, that the counter which is being controlled is in its initial or resting state, wherein conduction exists in transistors 396A and 396B.

Under the above assumptions, since the

stage including transistors

382A and 382B is conducting and the other stages are not conducting, the collector of transistor 382A applies a more negative potential to the anode of the diode 460A than is applied to any of the other diodes correspondingly located within the sequence-gate structures. Furthermore, the collector of transistor 382B will apply a more positive potential to the anode of the diode iB than is applied to the anodes of any of the other diodes correspondingly located within the sequence gates. Thus, the biases applied to the diode anodes connected to a conducting transistor pair are the reverse of the biases applied from a nonconducting transistor pair. Assume, now, that a pulse is applied to terminal 374 to cause the counter to advance. In response thereto, conduction in the first stage, including transistors 396A and 396B, is turned off. This causes a positive pulse to be applied to the capacitors 420A, 42GB from the collector of transistor 396A. Since the biases being applied from the transistors 386A and 385B to the junctions 422A, 422B are such that a more negative potential is applied to the junction 422B than to 422A, the positive pulse applied to capacitors 420A and 420B will be transferred through capacitor 429B, through diode 424B, to junction 430B, and thence through capacitor 434 to transistor 394A, to initiate the process of conduction in the second stage of this counter.

The next pulse applied to the terminal 374 is applied to the emitter of transistor 394B through the amplifying transistor 376 for the purpose of initiating turnoif of the second stage of the counter. As a result, a positive pulse is applied from the collector of transistors 394A to the two

diodes

462A, 462B. Because of the bias applied to the diodes 464A, 464B (corresponding to

diodes

424A, 424B) is similar to that applied by the nonconducting last stage of the controlling counter, a positive pulse will be applied through diode 464B, through capacitor 442, to the base of transistor 392A in the third stage to initiate conduction turnon in that stage.

Upon the application of another pulse to terminal 374, the third stage of the controlled counter is driven into cutoll". As a result, a positive pulse is applied to the two

capacitors

466A, 466B from the collector of transistor 392A. At this time, however, the bias applied to the

diodes

460A, 460B is the opposite of that which was described previously. As a result, this positive pulse will be applied through capacitor 466A, diode 469A, along the line 436, and through capacitor 438, to initiate conduction turnon in the iirst stage of the counter, which includes transistors 396A and 396B. Thus, the counter is reset upon the third input pulse. It should be appreciated that by connecting the pairs of

terminals

428A, 428B, 454A, 454B, 456A, 455B, 458A, 458B to the various stages of the controlling counter in the manner described, any sequence of count capacities can be obtained for the controlled counter as the controlling counter advances through each one of its count states.

There has accordingly been described and shown herein a novel, useful, and, it is believed, inviolate securitylines-supervision system where any attempt to tamper with any of the units at either location, results in an actuation of the alarm at the central location. By the word tamper it is intended to cover not only actual physical manipulation, but also electrical as Well, since both can be detected by this system. Although values of components and types of transistors used in an actual reduction to practice of this invention are shown in the drawings, this is not to be construed as a limitation upon the inl vention, but rather by way of example, since those skilled in the art will readily understand how these may be varied without departing from the spirit and scope of the invention.

I claim:

1. A security-line-supervisory system comprising at a central location means for randomly generating pulses, means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses, means for counting the random pulses occurring during a transmitting interval and establishing a representative voltage pattern, a line connecting said central location to a remote location, means for transmitting the random pulses generated during a transmitting interval to said remote location over said line, means at said remote location for receiving said transmitted pulses, means for counting the received pulses and establishing a representative voltage pattern, means for transmitting signals representative of said voltage pattern over said line to said central location, at said central location, means for receiving said signals and converting them to the voltage pattern represented thereby, means for comparing both received and retained voltage patterns, and means for indicating when a difference between said compared voltage pulse patterns exists.

2. A security-line-supervisory system comprising at a central location means for randomly generating pulses, means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses, means for counting the random pulses occurring during a transmitting interval and establishing a representative voltage pattern, a line connecting said central location to a remote location, means for transmitting the random pulses generated during a transmitting interval to said remote location over said line, means at said remote location for receiving said transmitted pulses, means actuated by said pulses for establishing a limit on the number of signals to be received equal to the number of random pulses generated during the preceding transmitting interval and for disenabling said means for receiving when said limit is reached, means for counting the received pulses and establishing a representative voltage pattern, means for establishing a transmitting interval and emitting a signal at the termination thereof, means for applying said termination signal to said means for receiving signals to enable it to receive signals again, means for converting said voltage pattern to representative signals, means for transmitting said representative signals to said central location over said line, at said central location, means for receiving said signals and converting them to the voltage pattern represented thereby, means for comparing both received and retained voltage patterns, and means for indicating when a difference between said voltage patterns exists.

3. A security-line-supervisory system as recited in claim 2 wherein at said central location said means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses and at said remote location said means actuated by said pulses for establishing a limit on the number of signals to be received equal to the number of random pulses generated during the preceding interval and for disenabling said means for receiving when said limit is reached each includes a first and second counter each having a plurality of stages, a pair of gates for and associated with each stage of said iirst counter, means connecting one of each pair of gates between its associated stage of said counter and the first stage, means connecting the other of each pair of gates between its associated stage and the preceding stage of said first counter, means for applying a ybias from each stage of said second counter not in a Vcount-indicating state to a different pair of said gates for biasing said one gate of a pair closed and said other gate of a pair open and for applying a bias to a pair of said gates from a count-indicating stage of said second counter for biasing said one gate of `said pair open and said other gate of said pair closed whereby the count in said irst counter advances in response to input pulsesV until the stage associated with said pair of gates is reached at which time said irst counter is returned to its initial count condition.

4. A security-line-supervisory system comprising at a central location, means for randomly generating pulses, means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses, means for counting the random pulses occurring during a transmitting interval and establishing a representative voltage pattern, means for converting each of the random pulses occurring during a transmitting interval to a sine-wave train, a line connecting said central location to a remote location, means for applying said sine-wave trains to said line, means at said remote location for receiving said sine-wave trains and converting them back to pulses, means for counting said pulses from said means for receiving and establishing a representative voltage pattern, means for converting said voltage pattern to representative signals, means for applying said representative signals to said line to be transmitted back to said central location, at said central location, means for converting said representative signals back to the voltage pattern represented thereby, means for establishing an interval for comparing both said voltage patterns and emitting a terminal signal at the conclusion thereof, means for comparing both said voltage patterns during said comparing interval and emitting a warning signal indicative of any difference therebetween, and means responsive to said terminal signal to initiate a new transmitting interval.

5. A security-line-supervisory system as recited in claim 4 wherein said means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses comprises a first and second counter each having a plurality of stages, means for applying said random pulses to said lirst counter to be counted, means for preventing further application of said random pulses to said first counter responsive to said first counter being returned to its initial count state, Va pair of gates for and associated with each stage of said first counter, means connecting one of each pair of gates between its associated stage of said counter and the first stage, means connecting the other of each pair of gates between its associated stage and the preceding stage of said first counter, means to apply a pulse to said second counter responsive to said terminal signal to advance the count of said counter from one stage to the next, means for applying a bias from each stage oi said second counter not indicating the count to a different pair of said gates for biasing said one gate of a pair closed and said other gate of a pair open and for applying a bias to a pair of said gates from the stage of said second counter which is indicating the count for biasing said one gate of said pair open and said other gate of said pair closed whereby the count in said first counter advances in response to input pulses until the stage associated with said pair of gates is reached, at which time said iirst counter is returned to its initial count condition.V

6. A security-line-supervisory system as recited in claim '4 wherein said means for converting each of the random pulses occurring during a transmitting interval to a sinewave train includes a means for randomly varying the .amplitude of the sine Waves from sine-wave train to sinewave train.

7. A security-line-supervisory system as recited in claim -4 wherein said means at said central location for counting the random pulses occurring during a transmitting interval and establishing a representative voltage pattern comprises a Ibinary counter, said means at said remote location for counting said pulses from said'nieans for receiving and establishing a representative voltage pattern comprises another binary counter, said means at said rcmote location for converting said voltage pattern torepresentative signals comprises means for successively scanning the voltage pattern output of said another binary counter for producing a pulse each time said voltage pattern represents one type of binary signal, means for converting each said pulse to a sine-wave train, and means for randomly vaiying the amplitude of said sine-wave train.

8. A security-line-supervision system comprising at a central location means for randomly generating pulses, a first, second, and third counter, a iiip-iiop circuit having two stable states, means for driving said'ip-op circuit to one of its stable states responsive to said first counter attaining its first count condition, means for driving said flip-flop circuit to the other of its stable states responsive to said third counter attaining its last count condition, a gate means for applying the output of said flip-flop circuit when in its other stable state to said gate to close said gate, means for applying said randomly generated pulses to said gate input, means for applying output from said gate to said lirst and second counters for advancing the counts therein responsive to randomly generated pulses passing through said closed gate, means connected to the output of said gate for generating signals representative of each pulse passed therethrough, means for transmitting said signals representative of each pulse to a remote location, means actuated each time said liip-iiop attains its one state of stability for changing the count capacity of said iirst counter from what it was in the preceding count cycle, means for applying output from said flip-flop when in its other stable state to Vsaid first gate to open it to prevent the passage therethrough of said randomly generated pulses, at said remote location means for receiving said signals and converting them to pulses, means for counting said received pulses, means for converting the count in said means tfor counting into rep- 'resentative signals, means Ifor transmitting said representative signals to said central location, at said central location, means for receiving said representa-tive signals and converting them into the count which they represent, means for advancing the count of said third counter responsive to said iiip-liop circuit being in its other state of stabiity, means for comparing the count derived from the received signals from said remote location with that in said second counter, and means responsive to a difference in said compared counts to actuate an alarm.

9. A security-linc-supervision system comprising a centrallocation apparatus, a remote-location apparatus, and a line connecting said central-location apparatus with said remote-location apparatus, said central-location apparatus having iirst, second, third, and fourth counters, a flip-ilop circuit having two stable states, means for driving said iiip-ilop circuit to one of its stable states each time said first counter returns to its rst count condition, means for driving said llip-flop circuit to the other of its stable states responsive to said third counter attaining its last count condition, means for opening said gate responsive to the output of said dip-flop when in its one stable state, means for closing said gate responsive to output from said flip-flop circuit when in its other stable state, means for randomly generating pulses, means for applying said randomly generated pulses to said gate input, means for applying output from said gate when closed to said iirst and second counters for advancing the Y .respective counts therein, means connected to the output of said gate for generating signals representative of each pulse passing therethrough, means for transmitting said signals over said line to said remote-station apparatus, gate means coupled between said fourth and iirst counter for establishing the count responsive to the count in said fourth counter from which said irst counter is Yreturned to its initial count condition', means for applying an output from said flip-lop circuit when driven to its one stable state by said first counter to said fourth counter dor advancing the count therein, said remote-location apparatus having means for receiving said signals and converting them to pulses, means actuated by said pulses for establishing a limit on the number of signals to be received equal to the count of said first counter and for disenabling said means for receiving when said limit is reached, means for counting said received pulses, means for converting the count in said means for counting into representative signals, means for establishing a transmitting interval and emitting a signal at the termination thereof, means to apply said termination signal to said means for receiving signals to render it active again, means for transmitting said representative signals on said line to said central-location apparatus, said central-location apparatus further including means for receiving said representative signals and converting them into the count which they represent, means for advancing the count of said third counter responsive to said flip-flop circuit being in its other state of stability, means for comparing the count derived from the signals received from said remote location with that in said second counter, and means responsive to a difference in said counts to actuate an alarm.

10. A security-line-supervisory system as recited in claim 9 wherein said means for randomly generating pulses includes a random-noise generator, a second flipflop circuit, having two states of stability, means for applying output from said random-noise generator to drive said flip-flop circuit from its one to its other state of stability, a blocking oscillator, means for applying said random-noise generator output to said blocking oscillator to provide time jitter for the pulse output of said blocking oscillator, and means for applying output from said second Hip-flop circuit when in its one stable state and said blocking oscillator output to the input of said gate circuit.

l1. A security-line-supervisory system as recited in claim 10 wherein said means connected to the output of said gate for generating signals representative of each pulse passing therethrough includes a third flip-flop circuit having two stable states, said flip-flop circuit being connected to the output of said gate circuit to be driven from one to the other of its stable states in response to output from said gate, means connected to the output of said second liip-op circuit when in its other state of stability to integrate said output, a normally inoperative oscillator circuit, and means for rendering said normally inoperative oscillator circuit operative to produce oscillations responsive to and for the duration of output from said third hip-flop circuit when in its one state of stability and having an amplitude determined by the amplitude of output from said means to integrate.

12. A security-line-supervisory system as recited in claim 9 wherein at said remote-location apparatus said means for converting the count in said means for counting into representative signals includes a random-noise generator, a flip-fiop circuit having two stable states, means for driving said ip-op circuit from one to the other of said two stable states, means for successively scanning the output of said means for counting to provide a pulse train representative thereof, means for integrating the output of said flip-flop circuit when in one of its stable states, a normally inoperative oscillator circuit, and means for applying said pulse train and output of said means for integrating to said oscillator circuit to cause it to emit oscillations having an amplitude determined by the amplitude of the output of said means for integrating and a duration determined by the duration of a pulse in said pulse train.

13. A security-line-supervisory system comprising a central-location apparatus, a remote-location apparatus, and a line connecting said central-location apparatus with said remote-location apparatus, said central-location apparatus having means for randomly generating pulses, means for establishing a transmitting interval having a random duration responsive to said randomly generated pulses, means for counting the random pulses occurring during a transmitting interval and establish a representative voltage pattern, means for converting each of the random pulses occurring during a transmitting interval to representative signals, means for applying said representative signals to said line to be transmitted to said remote-location apparatus, said remote-location apparatus including a rst, second, third, and fourth counter, means rendered operative responsive to said second counter attaining its last count state and inoperative responsive to said third counter attaining its rst count state for receiving said representative signals and converting them to pulses again, means for applying said pulses to said first and third counters to be counted, gate means connected between said third and fourth counters for establishing responsive to the count in said fourth counter the count in said third counter from which it is returned to its initial count condition, means for applying a signal to said fourth counter to advance its count responsive to said second counter attaining its last count condition, means responsive to said third counter returning to its first count condition to apply pulses to said second counter to cause it to complete a count cycle, means for scanning the count in said first counter responsive to output from said second counter to generate a pulse train representative thereof, means for converting said pulse train to representative signals, means for applying said representative signals to said line to be transmitted to` said central-location apparatus, said central-location apparatus further having means for receiving said pulse-train representative signals to a received representive voltage pattern, means for comparing said received representative voltage pattern with the representative voltage pattern previously establish, and means for actuating an alarm in the event of any difference indicated by said means for comparing.

References Cited in the le of this patent UNITED STATES PATENTS 2,798,213 Rowell July 2, 1957 2,800,644 Hines July 23, 1957 2,800,645 Koch July 23, 1957