US3131295A - Counter circuit - Google Patents

Description

April 28, 1 6 H. K. RISING ET AI.

COUNTER CIRCUIT 5 Sheets-Sheet 2 Filed April 20, 1955 INVENTORS HAWLEY K. RISING GEORGE R. BRIGGS ATTORNEY April 23, 1964 H. K. RISING ET A]. 3,131,295

COUNTER CIRCUIT Filed April 20, 1955 5 Sheets-Sheet 5 FIG. 6 +25ov 7 204 "3 CD l 100 f: 240 4 A c i CD 1 FIG. 3

INVENTORS HAWLEY K msms GEORGE R amass D J BY ATTORNEY April 28, 1964 H. K. RISING ET AL COUNTER CIRCUIT 5 Sheets-Sheet 4 Filed April 20, 1955 87 08+ w 8 a $6 o: f 80 WNW x5 :29 m9 mm .wg I 0 I I I ON KP. wN p Edi/ an; mm. 0: m9 3. N9 m9 NB L5? 08+ "w 8M 0s 8 0 E F E H 9.: x mm. 3% Fl! I Illl! lllllllllllllllllllll II L mmkmtwmm .50 04mm OF ATTORNEY United States Patent 3,131,295 COUNTER (IiRCUlT Hartley K. Rising, Lexington, Mass., and George R.

Briggs, Princeton, N.J., assignors, by direct and mesne assignments, to Research Corporation, New York,

N.Y., a corporation of New York Filed Apr. 29, 1955, Ser. No. 32,634 2? Claims. (Cl. 25s 175) This invention relates to a counting device for counting information in digital form and more particularly to a counting system employing bi-stable magnetic elements.

An object of the present invention is to provide an improved counting apparatus which utilizes magnetic cores for registering information at a very rapid rate and which is highly reliable yet simple to construct.

Anot er object of the present invention is to provide an improved counting apparatus which is easy to manufacture and requires comparatively little maintenance.

A still further object of the present invention is to provide an improved counting apparatus which employs a magnetic core type of shift register and circuits for algebraically combined input data, in the form of pulses, with the content of the magnetic core shift register.

Still another object of the present invention is to provide an improved counting apparatus wherein the cores of a magnetic core register are connected to form a closed loop, and circuits algebraically combine serial input data with the count stored in the magnetic core register and shift the result from the magnetic core register without disturbing its content.

Another object of the present invenion is to provide an improved counting apparatus wherein the binary ones complement of zero is established in a magnetic core shift register; any number, represented by a like number of serial pulses, is subtracted from the content of the magnetic core shift register by a subtracter circuit; and signals representing the complement of the content of the magnetic core shift register are produced by a read out register whenever it is desired to obtain the instantaneous count.

Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by way of example, the principle of the invention and the best mode, which has been contemplated, of applying that principle.

In the drawings:

P16. 1 is a Wiring schematic in block form of a counting device constructed in accordance with the principles of this invention.

FIG. 2 illustrates a wiring schematic of a core read out register shown in block form in PEG. 1.

FIG. 3 is a curve illustrating a preferred hysteresis characteristic of the magnetic cores involved.

FIG. 4 illustrates a wiring schematic of the core delay register shown in block form in FIG. 1.

FIG. 5 illustrates a wiring schematic of the core ring counter shown in block form in PEG. 1.

FIG. 6 illustrates a wiring schematic of one type of core driver shown in block form in FIG. 1 and FIG. 7 illustrates a wiring schematic of another type of core driver shown in block form in FIG. 1.

FIG. 8 illustrates a wiring schematic of one type of flip-flop circuit employed in PEG. 1.

Conventions Employed A conventional arrowhead is employed throughout drawings to indicate (1) a circuit connection, (2) energization with positive pulses, and (3) the direction of pulse travel which is also the direction of control; a diamond shaped arrowhead indicates (1) a circuit connection, and (2) energization with a DC. level. The D.C. levels are on the order of 10 volts when positive and 30 volts when negative; whereas pulses are .1 microsecond in duration and on the order of 20 to 40 volts in magnitude and positive unless otherwise indicated. A closed arrowhead which is not blackened indicates pulse duration greater than 0.1 microsecond. The input and output lines for the blocks in FIG. 1 are connected to the most convenient side of the block, including the same side in some cases. The wiring schematic for any block in question, together with the description given hereinafter, is sufficient to render the actual circuit connections unmistakably clear.

Reference is made to FIG. 1 for a description of the binary counter system of the present invention. This system serves to count pulses received on an input line labeled Add One and to deliver the count in response to a pulse on the input line labeled Read Out.

In response to a pulse on the Add One line, a flip-flop it) is set in the ONE state of conduction and the result ing positive signal on the output conductor of the ONE side conditions gates 12 and 13. The first subsequent pulse from a pulse generator 14 is passed by the gate 13 to set a flip-flop 15 in the ONE state of conduction. The flip-flop 15 conditions a gate 16 to pass pulses from the pulse generator 14. The pulses passed by the gate 16 are applied to the gate 12 and to a gate 18. Since the gate 12 is conditioned, it passes a pulse which is applied to the ZERO input side of flip-flop 16; whereupon flip-flop 1i) reverses its conduction state and conditions the gate 13 and deconditions the gate 12. The pulse passed by the gate 12 is also applied to a single-shot multivibrator 2-8 which converts the relatively narrow input pulse from the gate 12 to a relatively wide output pulse. A core driver 22 amplifies this wide output pulse and applies it to the Add One input line of a core ring counter.

Pulses from the gate 16 are passed by the gate 18 to a single-shot multivibrator 26 which generates an output pulse having a much greater width than the Width of the input pulse. This wide pulse undergoes power amplification in a cathode follower 28 before being applied to core drivers 3t), 32 and 34. The core drivers 39 and 32 supply shift pulses to the core ring counter 24. The core ring counter 24 is reset by momentarily closing a switch 35 which may be any suitable switching device.

The number of shift pulses required to effect the addition of a binary one to the core ring counter 24 is equal to the number of binary bits of this counter, and a core delay register 36 is provided to insure that only the required number of shift pulses is supplied to the core ring counter 24. As pointed out more specifically hereinafter, the core delay register 36 receives a signal on its Reset line which sets all cores in the core delay register to ZERO prior to the receipt of a pulse on its Add One line; while the Add One pulse causes the first core of the core delay register 36 to be set in the ONE state prior to the receipt of shift pulses on the shift input line. Whenever a binary one in the first core of the core delay register 36 has been shifted through the register and from the last stage in response to shift pulses on the shift input line, a negative signal is established on line 38 which sets the flip-flop 15 in the ZERO state in a manner pointed out in the basic circuit description hereinafter. Once the gate 16 is deconditioned by the flip-flop 15, no further pulses are passed to the core drivers 30, 32 and 34. As the fliptop 15 assumes the Zero state of conduction, core driver 4i) receives a positive signal level which is applied to the reset line of the core delay register 36 to set all cores in the ZERO state. From the foregoing it is seen that the core delay register 36 serves to control the exact is number of shift pulses applied to the core ring counter 24.

If it is desired to read the contents from the core ring counter 24, a pulse is applied to a line labeled Read Out. A pulse on this line sets a flip-flop 50 in the ONE state which conditions a gate 52. The first succeeding pulse from the pulse generator 14 is passed by the gate 52 and sets a flip-flop 54 in the ONE state, thereby conditioning a gate 56. When the next Add One pulse is received, the flip-flop ll) and a flip-flop 58 are set in the ONE state of conduction. The next pulse passed by the gate 12, in addition to being applied to the flip-flop it) and the single-shot multivibrator 29 as above described, is applied to the gate 56 which passes this pulse to the ZERO input side of a flip-flop 58. The ZERO output side of this flip-flop is applied as one of two inputs to a two-input AND circuit 60 which has as its other input a signal level from the ONE output side of the flip-flop 15. The flipfiop 15, as previously pointed out, is set on the ONE side immediately after the Add One pulse is received. The ZERO output signal level of the ilip-flop 58 is also applied to an AND circuit 62. Shift pulses then applied to the AND circuit 62 from the cathode follower 28 are passed since flip-flop 58 is in the ZERO state of conduction. These shift pulses undergo power amplification in cathode follower 54 and core driver 66 before being applied to the shift input of the core read out register 68. Information shifted serially from the core ring counter 24 is conveyed on a conductor labeled Data to the core read out register 68. The content of the core ring counter 24 is serially shifted into the core read out register 68 as shift pulses are applied simultaneously to both devices.

The output of the AND circuit 60 is applied to the ONE input side of a flip-flop 70 which in turn conditions a gate 72. The flip-flop 70 is set in the ONE state in response to a falling D.C. level from the AND circuit 69. How this operation is obtained is explained in the subsequent discussion on basic circuits. The next pulse from the pulse generator 14 is passed by the gate '72 and sets flip-flop 76 back in the ZERO state of conduction which deconditions the gate 72. The pulse passed by the gate 72 is applied also to a single-shot multivibrator 74 which converts the narrow input pulse to a wide pulse. This wide pulse is applied through a cathode follower 78 and a core driver 79 to an input conductor of the core read out register 68 labeled Parallel Read Out. A pulse on this conductor causes parallel read out of information which was previously shifted serially into the core read out register 68.

Reference is made to FIG. 2 for a description of the core read out register 68. An eight stage core read out register is herein employed since the core ring counter 24 is an eight stage counter. The cores employed in the apparatus of the present invention are made of commercially obtainable magnetic materials having a hysteresis loop substantially as illustrated in FIG. 3. Since points A and E on the curve in FIG. 3 are representative of stable remanent magnetic states, they may be considered representative of binary information stored in a magnetic core. The cores of the present invention may be driven to either of these magnetic states by the application of a positive or a negative magnetomotive force, respectively. If the state of remanence of a core made of such material is that indicated by the point A, application of a positive magnetomotive force greater than the coercive force causes the core to traverse the hysteresis curve to point C, and upon relaxation of this positive force, revert to point A. Application of a negative magnetomotive force greater than the coercive force causes the state of remanence to follow the curve to point D, and when the force is terminated, to traverse to point E. Similarly with the remanent state of a core standing at point B, the application of a negative magnetomotive force causes the curve to be traversed to point D and returned to point E when the negative force is relaxed; while a positive force greater than the coercive force causes a traversal of the curve from point E to point C and return to point A when the force is terminated. With the state of remanence indicated at point A arbitrarily selected as representing a binary ONE and the state of remanence indicated at point E as representing a binary ZERO, application of a negative magnetomotive force by pulsing a shift winding on a core simultaneously causes a voltage to be induced in an output sense winding if the core was previously in the ONE state; while a negligible voltage is induced in the output winding if the core was previously in the ZERO state. In order to indicate how the turns of a winding are placed on a core, the dot convention is employed to indicate that a positive voltage exists at the dotted end whenever a shift pulse is applied.

Referring again to FIG. 2, a pulse applied to the input conductor labeled Shift causes all the cores to be driven to the ZERO magnetic state indicated by the point B on the curve in FIG. 3. Information previously contained in the cores is serially transferred to the succeeding core, from left to right, by means of transfer circuits coupled between cores and labeled TR. Prior to each shift pulse the input line labeled Data is pulsed or not pulsed depending on whether a ONE or a ZERO, respectively, was applied. Once filled with serial information, the core read out register 68 is emptied by a pulse on the line labeled Parallel Read Out which drives all cores to the ONE state. Terminals 8h, 32, 34 and 86 are energized with a voltage pulse having substantial magnitude if a ZERO was previously stored in the associated core or a negligible voltage if a ONE was previously stored in the associated core. This operation of changing Zeros to Ones and vice versa is termed complementing.

Referring now to FIG. 4, the core delay register 35 is made 8 bits in size since the core ring counter 24 (FIG. 1) is also 8 bits in size. A pulse on the conductor labeled Reset causes all cores in this register to assume the ZERO magnetic state indicated by the point E on the curve in FIG. 3. A pulse on the conductor labeled ADD One causes the 2' core to be set in the ONE state, and subsequent pulses on the conductor labeled Shift causes the ONE state to be shifted to succeeding cores from left to right. An output pulse derived from the 2 core is negative when it changes from the ONE state to the ZERO state. This is indicated by the dot on the lower side of the output winding which signifies a polarity opposite to that indicated by the dot on the upper side of the preceding output Winding. The negative pulse serves to set flip-flop 15 (FIG. 1) in the ZERO state of conduction.

Referring now to FIG. 5, the core ring counter 24 is shown with cores 2 through 2 connected to form a closed loop. Whenever a pulse is applied to the input line labeled Reset, cores 2 through 2" and a core labeled T are set to the ONE state of magnetization represented by point A on the curve in FIG. 3 and a core labeled B is set to the ZERO state represented by point B on the curve in FIG. 3. Windings 100, 192, 104, 106, 198, 119 and 111 are termed reset windings. In response to a pulse on the line lebeled Add One, a winding 112 sets a core labeled A in the ONE state represented by the point A on the curve in FIG. 3. The two input lines labeled Shift are employed to divide the load and permit the use of core drivers having lower power outputs. These shift lines are pulsed simultaneously by core drivers 30 and 32 in FIG. 1. A shift pulse on line 114 applies a magnetomotive force on cores A, B, 2, 2' and 2 by means of respective windings 116, 118, 120, 122 and 124 to set these cores in the ZERO state represented by the point E on the curve in FIG. 3. A pulse on the shift line 126 changes cores 2 through 2 and core T to the ZERO state represented by point B on the curve in FIG. 3 by means of respective windings 128, 130 and 132 respectively. Each of the cores 2 through 2 has an input winding and an output Winding thereon. On

core 2' for example, winding 134 is the input winding and winding 136 is the output winding. If core 2 is in the ONE state of magnetization represented by the point A on the curve in FIG. 3 whenever a shift pulse having sufficient magnitude to exceed the coercive force is applied on the winding 122, this core is driven to that state indicated by point D on the curve in FIG. 3, and upon termination of this pulse, the core proceeds to the ZERO magnetic state represented by the point E on the curve in FIG. 3. This induces a substantial voltage across the output winding 136 which is passed by a diode 133 and charges a condenser 14%. As soon as the voltage across the winding 136 commences to decay, the diode 133 ceases to conduct and ofiers a high impedance which prevents the condenser 14% from discharging through the diode 138 and the winding 13d; whereupon the condenser 140 discharges through a circuit including an inductance 142, a resistor 1-14 and an input winding 146 of the 2 core. The discharge current through winding 146 is sufiicient in magnitude to develop a magnetomotive force greater than the coercive force and thereby set core 2 in the ONE state of magnetization represented by the point A on the curve in FIG. 3. The circuit components connected between the output winding 136 on core 2 and the input line 146 on core 2 constitute a transfer circuit shown throughout the drawings in block form and labeled TR. Thus it is seen that information in cores 2 through 2 may be shifted serially around the loop in response to shift pulses.

An additional winding 148 on core 2 is coupled through a transfer circuit 151) to a core labeled T. Since winding 152, an output winding on the 2 core, is coupled through a transfer circuit 154 to core 2, it is seen that the same information is stored in both the T core and the 2 core. The transfer circuit 154 serves to close the loop and thereby form a ring circuit; while transfer circuit 154) serves as a means to obtain information from the ring circuit. The output from core T is supplied through a transfer circuit 156 to an output line labeled Data. This data line is connected to the core read out register 68 shown in FIGS. 1 and 2.

The core B in FIG. has an output winding 16% connected through a diode 162 to the non-grounded plate of the condenser 14% and through a diode 164 to the non-grounded plate of a condenser 1%. Whenever the winding 16$) has an induced voltage as core B changes its magnetic state from a ONE to a ZERO, diodes 162 and 164 permit charging current to flow in condensers 144i and 166. When the charging current terminates, these condensers discharge. Condenser 144 discharges in the manner previously pointed out, and condenser 166 discharges through an inductance 168, a resistor 17%, a winding 172 on core 2 and a winding 174 on core B. The discharge current through winding 172 establishes a magnetomotive force in a direction to write a ZERO in the 2 core; whereas the discharge current through winding 17d establishes a magnetomotive force on core B to write a ONE.

Whenever the 2 core changes its magnetic state from ONE to ZERO, the resulting discharge current from a transfer circuit 176 establishes a magnetomotive force around winding 134 which is in a direction to write a ONE in the 2 core and establishes a magnetomotive force around winding 17% on core B in a direction to write a ZERO. It is noted that winding 172 is poled opposite to the winding 134 on the 2 core, and the winding 174 is poled opposite to the winding 178 on the core B.

Whenever an Add One pulse is applied to the winding 112 on core A, this core is set in the ONE state. A subequent shift pulse on winding 116 changes the A core to the ZERO state and induces a voltage on winding 180. The resulting current passed by diode 182' charges the condenser 166 which, upon discharge, tends to write a ZERO in the 2 and a ONE in the B core.

Because of the increased load to be driven by the output winding 16% on the B core, the shift winding 118 on this core may have approximately twice as many turns as the other shift windings. It may be desirable in the interest of better reliability to increase the shift winding 12?. on the 2 core by about five turns since opposing magnetomotive forces might tend to reduce the voltage across the output winding 136.

Although the A and B cores together with their associated circuits in FIG. 5 perform the function of a subtracter, the term Add One pulse is consistently employed throughout the description of the preferred embodiment since the overall function of the apparatus disclosed is to count.

From the foregoing discussion of the core ring counter 24 the following rules may be stated:

(1) If the core A is in the ONE state when a shift pulse is applied, then the 2' core which is set in the ZERO state by the shift pulse will remain in the ZERO state irrespective of the contents of the 2 core. This is true because the discharged current from condenser 166 through winding 172 inhibits the writing of a ONE in the 2' core.

(2) If core A is in the ONE state when a shift pulse is applied, the B core will be set to the ONE state if the 2 core previously contained a ZERO. This is true because the discharge current from condenser 166 through the winding 174- writes a ONE in the B core and there is no magnetomotive force established by the winding 178 to oppose the magnetomotive force of the winding 174.

(3) Whenever the core B is in the ONE state and a shift pulse is applied, the 2 core will be set to the ONE state because the winding 16% of the core B supplies a current to charge condenser 14% which, on discharge, sets the 2 core to the ONE state.

(4) Whenever both the 2 and the B core are in the ONE state and a shift pulse is applied, the 2 core will be set to the ZERO state by the shift pulse and will remain there. This follows since the windings 134 and 172 on the 2" core oppose each other.

(5) Whenever the 2 core contains a ZERO and the B core contains a ONE as a shift pulse is applied, the 2' core will be set to ZERO and the B core will be set again to the ONE state. This is true because transfer circuit 176 supplies a negligible voltage to associated input windings 134 and 178; consequently the discharge current from the condenser 166 through the windings 172 and 174 sets a ONE in the B core and tends to set a ZERO in the 2 core which was set to ZERO by the shift pulse.

(6) If the A core and the B core are in the ZERO state when a shift pulse is applied, information in the ring circuit, composed of cores 2 through 2' is not affected except to make a straightforward shift one position to the right.

In operation, the counter is initially reset by closing switch 35 in FIG. 1 which energizes the reset line in FIG. 5. This sets the 2 through 2" cores in the ONE state and the B core in the ZERO state. After an Add One pulse is applied to the A core in FIG. 5, eight shift pulses are simultaneously applied to both shift lines 114 and 126. In the preferred embodiment the Add One pulses and the shift pulses are 2.5 microseconds wide when applied to the core ring counter 24-. The shift pulses preferably occur at a constant rate 20 microseconds apart; while the Add One pulses may occur at a random rate with a minimum interval of about 250 microseconds. Read out from the core ring counter 24 can occur without interrupting the counting operation as will now be described.

Serial transfer of information from the core ring counter 24 to the core read out register 63 can occur without interrupting the operation of the core ring counter. To illustrate the read out operation, assume the Read Out line in FIG. 1 is pulsed. This pulse causes the AND circuit 62 to be conditioned in a manner previ- 7 ously described. The AND circuit 62 is not conditioned, however, until the next Add One pulse is received and a pulse is passed by the gates 12 and 56 to set the flipfiop 58 in the ZERO state. As shift pulses are supplied by cathode follower 28 through the core drivers 39} and 32' to the core ring counter 24, these shift pulses are applied also through the AND circuit 62, when conditioned, to the core read out register 68. Information from the T core of the core ring counter 24- (FIG. is serially shifted into the core read out register 68 (FTGS. 1 and 2) as shift pulses are simultaneously applied to both devices. It is recalled that the T core contains the same information as the 2 core of the core ring counter 24; consequently the information shifted from the T core represents the count, in complement form, contained in the core ring counter prior to the last received Add One pulse.

As the last or eighth shift pulse is applied to the core ring counter 24 and the core read out register 68 completes the above serial transfer of information, a nega tive pulse on conductor 33 causes the flip-flop 15 to decondition the AND circuit 6! The deconditioning of this AND circuit sets the flip-flop 711 in the ONE state and permits the gate 72 to pass a pulse to the Parallel Read Out line. As set forth in the discussion of FIG. 2, this pulse causes information in the core read out register 63 to be complemented as it is read out in parallel. It is pointed out that the information read from the core read out register 68 represents the count contained in the core ring counter 2d at the time the Read Out pulse was received.

In order to illustrate the operation of the core ring counter 24-, assume that a pulse is applied to the reset line in FIG. 5. Cores 2 through 2 are set to the ONE state and core B is set to the ZERO state. Now assume that the first Add One pulse is applied to the core A which sets it in the ONE state. As noted in the discussion of FIG. 1, eight shift pulses on lines 114 and 126 automatically follow each Add One pulse. The first shift pulse following an Add One pulse causes capacitor 166 to be charged since the A core changes from the ONE to the ZERO state. This condenser discharges through windings 172 and 174 as the transfer circuit 176 is discharging through the windings 134 and 178. Because the magnetomotive force around the winding 172 opposes the magnetomotive force around the winding 134, the two magnetomotive forces neutralize each other and the 2 core remains in the ZERO state established therein by the shift pulse. Since the magnetomotive force around winding 178 which is in a direction to set the B core to the ZERO state opposes the magnetomotive force of winding 1'74- which tends to set the B core in the ONE state, the magnetomotive forces of these windings are neutralized, and core B remains in the ZERO state established by the shift pulse. Since t..e A and B cores are now in the ZERO state, they will not affect the information in the 2 through 2 cores during the subsequent seven shift pulses. These seven shift pulses cause information in the ping circuit to be advanced successively seven times to the right. Reference is made to Table 1 below which shows grapically the contents of each core following the first Add One pulse and the subsequent eight shift pulses.

TABLE 1 1st Add One Operation A B 2 2 2 2 2 2 2 2 T 1 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 8th shift 0 0 1 1 1 1 1 1 1 0 0 If a second Add One pulse is appl ed to core A, it is again set to the ONE state. The first shift pulse which automatically follows the Add One pulse causes the B core to be set to the ONE state and the 2 core to be set to the ZERO state because the magnetomotive forces on windings 172 and 174 are unopposed by the magnetornotive forces on the windings 134 and 178 respectively. Following the first shift pulse, the B core is in the ONE state; while the 2 and A cores are in the ZERO state. Upon recepit of the second shift pulse, the B core causes a ONE to be established in the 2 core as the B core is changed to the ZERO state. More specifically, the second shift pulse causes condensers 149 and 166 to be charged. The magnetomotive forces established around windings 172 and 174 by the discharge current of condenser 166 are opposed by the magnetomotive forces on windings 134 and 178 respectively since the 2 core was previously in the ONE state. Since the 2" core was previously in the ZERO state, condenser receives no charging current from the output winding 136 on the 2 core; however, condenser Mil does receive charging current from the winding 16a? of the B core which causes the 2 core to be changed to the ONE state. Since the B core is changed to the ZERO state following the second shift pulse and since the A core is in the ZERO state after the first shift pulse, no change is made in the information contained in the ring circuit for the succeeding six shift pulses except six straightworward shifts successively to the right. Table 2 below illustrates graphically the contents of each core following each of the pulses.

TABLE 2 2nd Add One Operation 1 O 1 1 l l 1 l 1 0 O 0 1 0 l 1 1 1 1 1 1 1 0 0 0 l 1 1 1 1 1 l 1 0 0 1 0 1 1 1 l l l 1 0 O 1 l 0 1 1 l 1 l 1 O O 1 1 1 0 1 l 1 l 1 0 0 l l l 1 0 1 1 1 1 O 0 1 1 l 1 1 0 1 1 1 8th Shift 0 0 1 1 1 l 1 1 O l 1 The A core is set to the ONE state upon receipt of the third Add One pulse. The A core is set to ZERO by the first shift pulse which automatically follows the Add One pulse; while the B core and the 2' core remain in the ZERO states following this first shift because the 2 core contained a ONE. The second and subsequent shift pulses cause information in the ring circuit to be advanced successively to the right. Table 3 below shows graphically the content of each core after each of th pulses. i

TABLE 3 3rd Add One Operation A B 27 25 25 )4 23 22 91 20 T 1 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 r 0 0 1 1 1 1 0 o 1 1 1 0 0 1 1 1 1 1 0 0 1 1 8th shift 0 0 1 1 1 1 1 1 0 0 0 The fourth Add One pulse again sets the A core to the One state. The B core is in the ONE state and the 2 core is in the ZERO state after the first shift pulse because the 2 core previously contained a ZERO. The second shift pulse causes the B core to write a ONE in the 2 core. Also a ONE is rewritten in the B core because the 2 core previously was ZERO. The third shift pulse causes a ONE to be set in the 2 core. The B core is set TABLE 4 4th Add One Operation The application of further Add One pulses causes the core ring counter to advance the count in a manner similar to that pointed out above. The content of the counter must be read out before or at the time it is full; otherwise the true count is lost. In the preferred embodiment which illustrates an eight stage counter, the counter is full when 256 Add One pulses are received. The 257th Add One pulse and the eight shift pulses which automatically follow cause all cores in the ring circuit to be set in the ONE state which is the reset condition. Although an eight stage core ring counter is illustra ed and described in the preferred embodiment it is understood that the number of stages employed can be increased or diminished as desired. Hence a novel binary counter system is provided which can receive pulses at a random rate and accomplish the counting by means of a core ring counter. Moreover, the count can be read out without interrupting the counting operation or destroying the content of the counter.

The mathematics involved in the counting system in the present invention may be stated as follows: If a number X is subtracted from the complement of zero of any number, the complement of the result gives the positive value of X. This proposition is true for any radix. For example the following illustration in binary numbers is given:

Complement of Zero 1111 X -11 Result 1100 Complenment of result which is -{X 0011 In the preferred embodiment of the present invention the complement of zero is set in the core ring counter by a pulse on the Reset line. The quantity of X is set in the counter by successively subtracting ones in the form of pulses applied to the Add One line. The result at any instant is the content of the core ring counter after it has completed its automatic shifts following the Add One pulse. After the result is transferred from the core ring counter 24 in FIG. 1 to the core read out register 68, the result is complemented. Thus the core read out register 68 supplies +X on output lines 89 through 86 with ones being represented by a pulse and zeros by the absence of a pulse.

BASIC CIRCUITS Reference is made to FIG. 6 for a description of one of the two types of core drivers employed. A first type of core driver 2% of FIG. 6 receives a pulse on input conductor 2M and delivers a pulse on output conductor 2634 of substantially the same shape having increased power. A tetrode-connected pentode 286 has its suppressor grid 298 connected to an anode 219 through resistors 212 and 214. The resistor 214 is connected between the anode 212 and the output conductor 204. Control grid 216 is connected to a bias source of -30 volts by resistors 218 iii and 229. An input pulse on a line 202 is applied through resistor 218 to the control grid 216. A decoupling network comprising a resistor 222 and a condenser 224 is connected through a resistor 226 to a screen grid 228. This decoupling network serves to minimize voltage variations on the screen grid 223 and the volt source from affecting each other. Cathode 230 is connected to ground through a resistor 232. The 47 ohm resistors connected to the electrodes of the type 7AK7 vacuum tube 206 serve to suppress parasitic voltages. The anode circuit of the vacuum tube 2% is completed through the various elements shown in dotted line form which include core windings represented by an inductance 234, a resistor 236, a resistor 23S serially connected to a source of positive 250 volts. The junction point of resistors 236 and 233 is connected to ground through a condenser 240. The resistor 238 and the condenser 240 serve as a decoupling network while the resistor 236 serves as a current limiting resistor. Since the core driver 2% delivers a substantial amount of power, it is employed in each of the core drivers 39, 32, 34, 4t 66 and 79 shown in block form in FIG. 1. It is noted that these core drivers supply shift pulses to a plurality of cores.

Referring now to FIG. 7 a second type of core driver 259 receives a pulse on input conductor 252 and delivers a pulse on output conductor 254 which has substantially the same wave shape with increased power. The power output from the core driver 250 is substantially less than the power output of the core driver 260 since it is merely required to supply sufficient pulse power to set two cores. This circuit is employed in the core driver labeled 22 and shown in block form in FIG. 1.

A vacuum tube 256 of the core driver 259 in FIG. 7 has its grid 258 connected through resistors 26B and 262 to a bias source of negative 30 volts. A pulse on the input conductor 252 is applied through the resistor 260 to the control grid 258. A cathode 264 is connected through a resistor 266 to a negative source of 15 volts. An anode 263 is connected through a resistor 270 to the output conductor 254. The anode circuit of the vacuum tube 256 includes the resistor 27 ii and additional elements shown in dotted form which include a core winding represented by an inductance 272, diode 274, resistor 276, capacitor 230 and a source of positive 150 volts. The resistor 276 and a condenser 28%, connected as shown, serve as a decoupling network to prevent voltage variations of the anode 268 and a positive 150 volts source from substantially afiecting each other. The vacuum tube 256 is preferably one half of a type 5965 twin triode vacuum tube.

While the gates and AND circuits shown in block form throughout FIG. 1 may be conventional circuits, they are preferably of the type illustrated and described in copending US. application Serial Number 414,459, filed March 4, 1954, by B. L. Sarahan et al. The type B cathode follower may be of the type shown and described in the above mentioned copending application wherein the cathode resistance value R is 17.15 kilo-ohms. The pulse generator 14 in FIG. 1 may be any conventional freerunning pulse generator which is capable of generating pulses 0.1 microsecond in width and 20 microseconds apart. While the single shot multivibrators 20, 26 and 7 4 shown in block form in FIG. 1 may be any conventional single-shot multivibrator which will yield an output pulse approximately 2.5 microseconds in width, they are preferably of the type shown and described in copending US. application Serial Number 474,346, filed on December 10, 1954, by W. L. Jackman. Although the type C flip-flop shown in block form throughout FIG. 1 may be one of many conventional varieties it is preferably of the type shown and described in copending US. application Serial Number 494,982, filed on March 17, 1955, by Robert R. Everett et al., now Patent No. 2,988,735.

The flip-flop circuit 76 in FIG. 1 is shown in detail in FIG. 8. A 0.1 microsecond pulse on conductor 300 establishes a positive D.C. level on output conductor 302 while a negative going signal level on conductor 304 establishes a positive 110. level on output conductor 306. The flipiiop 70, a bi-stable electronic circuit, includes two amplifying vacuum tubes 310 and 311 which may be the respec tive halves of a 5965 twin triode. Anodes 312 and 313 of the vacuum tubes 31% and 311 are cross-coupled to con trol grids 314 and 315 as shown. If one of the amplifying tubes 310 or 311 is conducting, the other is nonconducting except during a transition in state when both tubes may be non-conducting momentarily.

Operating DC. potential is supplied to the anode 312 through series connected resistors 317 and 318 while operating DC. potential is supplied through series connected resistors 319 and 320 to the anode 313.

A voltage divider network which constitutes part of the load circuit for anode 312 includes resistors 322, 323 and 324 connected serially between the anode 312 and a source of 300 volts. The resistor 324 and a condenser 325 serve as a decoupling network which prevents voltage fluctuations in the 300 volts source from materially affecting the potential across the voltage divider network; also, voltage fluctuations across the voltage divider network are substantially prevented from affecting the -300 'volts source. Control voltage for the grid 314 of the vacuum tube 311 is obtained from the junction point of the resistors 322 and 323 of the voltage divider network through a resistor 326. A condenser 327, connected in parallel with the resistor 322, serves as a compensating capacitor which helps to insure that the voltage wave at the anode 312 during a change of state is applied with suflicient amplitude and proper shape to the grid 314. This condenser serves also as a memory capacitor to insure that the vacuum tube 311 is rendered conductive whenever both tubes are momentarily rendered non-conducting during a change of state in which vacuum tube 311 was previously non conductive.

A voltage divider network which constitutes part of the load circuit for the anode 313, includes resistors 328, 329 and 324 serially connected between the anode 313 and the source of 300 volts. Control voltage for the grid 315 of the vacuum tube 310 is obtained from the junction point of the resistors 328 and 329 through a resistor 333. A condenser 332, connected in parallel with the resistor 323, serves as a compensating capacitor which helps to insure that the voltage wave at the anode 313 during a change or" state is applied with suflicient amplitude and proper shape to the grid 315. This condenser serves also as a memory capacitor to insure that the vacuum tube 310 is rendered conductive whenever both tubes are momentarily non-conductive during a change of state where vacuum tube 310 was previously non-conductive.

A resistor 334, connected between the resistor 324 and the common connection point of the cathodes 335 and 336,

provides cathode degeneration for the two amplifying tubes 310 and 311. The charge on a by-pass condenser 337, connected across the resistor 334, is little affected by a short duration input pulse, and the effect of this condenser is to hold the cathodes 335 and 336 at substantially the same potential at all times. Thus a negative pulse applied across the grid-cathode circuit of the conducting tube creates no appreciable change in potential at the cathodes 335 and 336.

A positive input pulse to a primary winding 340 of a transformer 341 establishes a negative pulse on a secondary winding 342. The secondary winding 342 is serially connected with a diode 343 and the resistor 326 between the grid 314 and the cathode 336. A negative pulse on the secondary winding 342 is passed by the diode 343 provided the potential on its anode 344 is positive relative to the potential at its cathode 345. When the vacuum tube 311 is non-conducting, its grid potential is at or below cut oil, and a negative pulse, whether passed by diode 343 or not, does not aifect the non-conducting state of this vacuum tube. If the vacuum tube 311 is conducting, howwhich occur on the upper side of the secondary winding 342 as a result of the decay of a positive pulse on the primary winding 340.

A negative going signal applied to input terminal 304 is coupled through a series circuit including a condenser 350, a diode 351 and the resistor 333 to the grid 315 of the vacuum tube 310. A resistor 352 is connected between the cathode 335 and the junction point of the diode 351 and the condenser 350. The resistor 352 and the condenser 350 serve as a differentiating circuit which helps to make the leading edge of the negative going input signal more steep and consequently reduce the fall time of the leading edge. A negative going input signal on the input terminal 304, when sufiiciently negative, drives the grid 315 below cutoff and prevents current conduction through the vacuum tube 310.

The input terminal 304 in FIG. 8 is connected to the output terminal of the AND circuit in FIG. 1. When the output signal level of the AND circuit 60 changes from positive 10 volts to negative 30 volts, the negative going level is coupled to the grid 315 (FIG. 8), and the vacuum tube 310 is rendered non-conductive. It is noted that flip-flop 7 0 is normally in the ZERO state, i.e. vacuum tube 312 is conducting and output terminal 306 is at a negative D.C. level. Diodes 353 and 354 clip their 3550-. ciated output terminals at positive 10 volts; whereas diodes 355 and 356 clip their associated output terminals at negative 30 volts.

In order to illustrate the operation of the flip-flop 9, assume a positive pulse is applied to the primary winding 340 of the transformer 341 when the vacuum tube 311 is conducting. The diode 343, which is at the threshold of conduction because the grid bias of the vacuum tube 311 is zero or slightly positive, passes the resulting negative pulse produced across the secondary winding 342 to the grid 314. As the grid 314 goes negative beyond cutoif, the potential at the anode 313 of the vacuum tube 311 rises 'llOW-flld volts but is clamped at +10 volts by diode 354. This positive going potential is coupled through the resistor 328 and the condenser 332 to the grid 314 and initiates conduction in the vacuum tube 312 as soon as its grid potential rises above the cutoff potential. As conduction commences in the vacuum tube 310, its anode potential starts decreasing from +10 volts until at full conduction it reaches 30 volts. This decreasing potential at the anode 312 is coupled through the resistor 322 and the condenser 327 to the grid 314 and maintains the grid 314 below the cutoff potential. In this condition with the vacuum tube 310 conducting and the vacuum tube 311 non-conducting, the flip-lop circuit is said to be in the ZERO state of conduction.

If a negative going signal level is now applied to the input terminal 304, the negative pulse is passed by the diode 351 and applied to the grid 315. As the grid 315 goes negative beyond cutoff, the potential at the anode 312 of the vacuum tube 310 rises toward +90 volts but is clamped at +10 volts by diode 353. This positive going potential is coupled through the resistor 322 and the condenser 327 to the grid 314 and initiates conduction in the vacuum tube 311 as soon as its grid potential rises above the cutolf potential. As conduction commences in the vacuum tube 311, its anode potential starts decreasing from +10 vol-ts until at full conduction it reaches -30 volts. This decreasing potential at anode 313 is coupled through the resistor 32% and the condenser 332 to the grid 315 and maintains the grid 315 below the cutoif potential. In this 13 condition with the vacuum tube 315 non-conducting and the vacuum tube 313 conducting, the flip-flop circuit is said to be in the ONE state. It is noted that in each case above, pulses are applied to the input terminal of the conducting tube to drive the conducting tube to the non conducting condition.

The above described flip-flop circuit is also used for the flip-flop in PEG. 1 except the value of condenser 3% is changed to 82 micro-micro-farads.

While there has been shown and described and pointed out the fundamental novel features of the invention as applied to a preferred embodiment, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art Without departing from the spirit of the invention. It is the intention therefore, to be limited only as indicated by the scope of the following claims.

What -is claimed is:

1. A subtracter including at least first, second and third magnetic elements, first circuit means coupled to said first, second and third magnetic elements for writing a One in said first and third magnetic element and a Zero in said second magnetic element, second means coupling said second magnetic element to said first means and adapted to write a One in said third magnetic element, third means coupled to said first and second magnetic elements for writing a One in said second magnetic element and a Zero in said first magnetic element, shift means coupled to said first, second and third magnetic elements, and fourth means coupled .to said first means for supplying input signals representative of a number.

2. The apparatus of claim 1 wherein said first means in cludes .a first and second transfer circuit each having an input side and an output side, an output winding on said first magnetic element coupled to the input side of said first and second transfer circuits, an output winding on said second magnetic element coupled to the input side of said second transfer circuit, an input Winding on said third magnetic element coupled to the output side of said second transfer circuit, an input winding on said first magnetic element and an input winding on said second magnetic element coupled to the output side of said first transfer circuit, said input windings of said first and third magnetic elements being poled to write a One and said input Winding of said second magnetic element being poled to write a Zero, said second means including an output winding on said second magnetic element coupled to the input side of said second transfer circuit, and said fourth means being coupled to said input side of said first transfer means.

3. The apparatus of claim 1 wherein said third means includes a third transfer circuit having an input side and an output side, an output winding on said third magnetic element coupled to the input side of said third transfer circuit, an additional input winding on said second magnetic element, and an additional input Winding on said first magnetic element, said additional input windings being coupled to the output side of said th rd transfer circuit, said additional input Winding on said second magnetic element being poled to write a One and said additional input win-ding on said first magnetic element being poled to Write a Zero.

4. A subtracter circuit comprising first, second and third magnetic elements; first, second and third transfer means each having an input side and an output side; a first winding on said first magnetic element, first means coupling said first magnetic element to the input side of said fist transfer means and the input side of said second transfer means, second means coupled to the input side of said first transfer means for coupling pulses representative of a subtrahend, third means coupled to the output of said first transfer means for writing a One in said first magnetic element and a Zero in said second magnetic element, fourth means coupling said second magnetic element to the input side of said second transfer means, fifth means coupling said third magnetic element to the output side of said second transfer means, sixth means coupling said third magnetic element to the input side of said third transfer means, seventh means coupled to the output side of said third transfer means for writing a One in said second magnetic element and a Zero in said first magnetic element, shift means coupled to said first, second and third magnetic elements, and means for controlling the magnetic state of said second and third magnetic elements to represent a minuend.

5. A magnetic core device comprising in combination, a magnetic core shift register and a magnetic core subtracter circuit; said magnetic core shift register having 2 through 2 stages Where n is any positive integer greater than Zero, each stage including at least a magnetic element and transfer means for trmsferring information to a succeeding magnetic element and for receiving information from a preceding magnetic element, said stages of said magnetic core shift register being connected to form a. closed ring, and means for controlling the magnetic state of said magnetic elements for representing a number in said stages; said subtracter circuit including at least one magnetic element, a first means coupled to said one magnetic element, said 2 stage and said 2 stage for writing a One in the magnetic element of said 2 stage and said one magnetic element and a Zero in the magnetic element of said 2 stage, a second means coupled to the output of said transfer means in said 2 stage and coupled to said one magnetic element for writing a Zero in said one magnetic element, and third means coupled to said first means for supplying input pulses representative of a number.

6. The apparatus of claim 5 wherein said first means includes a transfer circuit, a first input winding on the magnetic element in said 2 stage poled to Write a Zero and a second input winding on said one magnetic element poled to write a One, said first and second input windings being connected to the output of said transfer circuit, an output winding on said one magnetic core coupled to the input of said transfer circuit and the input of said transfer means positioned between the magnetic element of said 2 stage and the magnetic element of said Z stage, and said third means is coupled to the input of said transfer circuit.

7. The apparatus of claim 5 wherein said second means includes a third input winding on said one magnetic element pole dto write a Zero, said third winding being coupled to the output of said transfer means located between the magnetic element in said 2 stage and the magnetic element in said 2 stage.

8. A magnetic core device for performing subtraction comprising a magnetic core shift register having 2 through 2 stages, where n is any integer greater than zero, each stage including a magnetic core having an input winding, an output Winding, a reset winding and a shift winding, first pulsing means coupled to said reset windings for pulsing said reset windings, second pulsing means coupled to said shift windings for pulsing said shift windings, transfer means for each stage, said transfer means being coupled between the output winding of its associated stage and the input winding of the adjacent succeeding stage, an A core and a B core, said A core having an input winding, said A core and said B core each having an output winding and a shift winding, said shift windings of said A and B cores being coupled to said second pulsing means, said B core having a reset winding coupled to said first pulsing means, an additional transfer circuit having an input side and an output side, said output winding of said 13 core being connected to the input side of said additional transfer circuit, a first unilateral conducting device connected between the output winding of said A core and the input side of said additional transfer circuit so that said output windings of said A and B cores are electrically isolated, a second unilateral conducting device connected between the output winding of said B core and the input side of said transfer circuit located between the magnetic cores in the 2 stage and the 2 stage so that said output windings of said 2 stage and said B core are electrically isolated, a second input winding on the magnetic core in said 2 stage, a first and a second input winding on said B core, said second input winding on the magnetic core in said 2 stage and said first input winding of said B core being connected in series across the output side of said additional transfer circuit, said input winding of the magnetic core in said 2 stage and said second input winding of said B core being connected in series across the output of said transfer circuit located between the magnetic core in the 2 stage and the magnetic core in the 2, stage, said input winding of the magnetic core in said 2 stage being poled opposite to said second input winding of said 2 stage, said first and second input windings of said B core being oppositely poled,

said second input winding of the magnetic core in said u 2 stage tending to establish a magnetic state representative of a Zero and said first input Winding of the B core tending to establish a magnetic state representative of a One when energized by said additional transfer circuit.

9. A counting device comprising in combination, a register having a plurality of digit stages connected to form a ring circuit, and means for supplying information to said circuit and for shifting such information around said circuit to change the count, said last named means including control means effective when it contains one type of information to inhibit advance of the same information from the lowest order digit and to cause said information to be written in the next to the highest order digit.

10. A counting evice as claimed in claim 9 wherein said digit stages are bi-stahle magnetic cores, said information supplying and shifting means comprise pulse supply and transfer windings on said cores and said one type of information is one of the two numbers or" the binary system.

11. A counting device as claimed in claim 10 wherein said control means includes a bi-stable magnetic core additional to the digit stage cores coupled to said lowest order and next to highest order digit stage cores.

12. An exclusive OR logical device comprising a pair of field-sustaining elements, each having input, output and inhibit windings, a first input circuit including the input winding of the first field-sustaining element, a second input circuit including the input winding of the second field-sustaining element, and means for crossconnecting said second and first inhibit windings in series with said first and second input windings, respectively, to prevent any change in either of said field-sustaining elements when both said input circuits carry input current simultaneously.

13. An exclusive OR logical device for performing the function of partial subtraction comprising a pair of field-sustaining elements, each having input, canceliation and output windings, a first circuit including the input winding of the first field-sustaining element connected in series with the cancellation winding of the second field-sustaining element, a second circuit including the input winding of the second field-sustaining element connected in series with the cancellation Winding of the first field-sustaining element, means for buffering the outputs of said two output windings to a common field-sustaining element, and means including said cancellation windings in said first and second circuits for registering in said common field-sustaining element a signal transmitted by either of said circuits, only when said signal transmitting circuit is acting exclusively of the other.

14. In a signal control system, a pair of signal storing elements, a first conducting means for entering a 16 signal in the first of said elements, a second conducting means for entering a signal in the second of said elements, a third conducting means connected in series with said first conducting means for inhibiting the entrance of a signal in the second of said elements, a fourth conducting means connected in series with said second conducting means for inhibiting the entrance of a signal in said first of said elements, and means for registering the operation of either of said first or second I conductin means only when such operation occurs exclusively of operation of the other of said first or second conducting means.

15. A device for registering a partial algebraic sum comprising a pair of signal storing elements, an output circuit, input windings for entering digital values in each of said signal storing elements, means responsive to energization of one of said input windings for producing in said output circuit a signal representing the partial producing in said output circuit a signal representing the partial algebraic sum constituted by the entered digital value, and cross-inhibiting means including a cancellation winding connected in series with each of said input winding means responsive to operation of both said input winding means for preventing any change insaid signal storing element and production of a signal in said output circuit.

17. In a signal control system, a pair of field-sustaining signal storing elements, an output circuit, means including input windings on said elements for entering igital values in each of said signal storing elements, and means including cancellation windings cross-con nected in series with said input windings for inhibiting. simultaneous input signals from entering said signal storing elements, said latter means responsive to current flow in one, but not both, said input windings, to produce a signal in said output circuit.

18. In a signal control system, a pair of field-sustain. ing signal storing elements, an output circuit, means including input windings on said elements for reversing the polar direction of their respective fields, and means. including cancellation windings cross-connected in series with said input windings for inhibiting simultaneous in-. put signals from entering said signal storing elements, said latter means responsive to current flow in one, but not both, said input windings, to produce a signal in said output circuit.

19. In a signal control system, a pair of field-sustaining signal storing elements, an output circuit, means in! cluding input windings on said elements for reversing the polar direction of their respective fields, means including cancellation windings cross-connected in series with said input windings for inhibiting simultaneous in-. put signals from entering said signal storing elements and means including output windings on said elements for generating a signal in said output circuit in response to. current flow in one, but not both, of said input windings.

20. In a signal control system, a pair of field-sustaining elements, means including input windings on said elements for reversing the polar direction of their respective fields, means for energizing said input windings, a cancellation winding connected in series With each of said input windings for rendering either one of said direction reversing means ineffective to produce a change 17 in the respective field-sustaining element when the other input winding is activated by said energizing means.

21. In a magnetic control system a saturable magnetic core of material having high magnetic retentivity and having an output winding, means for reversing the direction of flux saturation in said core, and thereby generating a current in said output winding, eans operated by said generated current for immediately restoring said core to its preexisting direction of flux saturation, and winding means on said saturable magnetic core for selectively inhibiting said restoring means.

22. In a magnetic control system, a saturable magnetic core of material having high magnetic retentivity and having an input winding, an actuation winding, and an output winding in which current is generated in response to the magnetic field reversal produced by delivery of current to said actuation winding, means for directly feeding back to said input Winding the current generated in said output winding, to cause a second reversal of the magnetic field embracing said core, and winding means on said saturable magnetic core for selectively inhibiting said second reversal of said magnetic field.

23. in a magnetic control system, a magnetic flux-sustaining eiement having an output circuit associated therewith, means for producing a flux change in said element and thereby causing current flow in said output circuit at the beginning of an operative cycle, means responsive to said current flow for producing a second flux change in said flux-sustaining element before termination of said operative cycle, and winding means on said magnetic fluxsustaining element for selectively inhibiting said second flux change.

24. In a magnetic control system, a magnetic fluxsustaining element, and means responsive to a first flux change in said element for producing a second flux change therein, and winding means on said magnetic flux-sustaining element for selectively inhibiting said second flux change.

25. In a magnetic control system, a magnetic fluxsustaining element, looped-circuit means responsive to a first flux change in said element for producing a second flux change therein at the completion of the first flux change, and winding means on said magnetic flux-sustaining element for selectively inhibiting said second flux change.

26. In a magnetic control system, first and second magnetic flux-sustaining elements having input, feedback, inhibit and output windings associated therewith, means for producing a flux change in said first magnetic fluxsustaining element and thereby causing current flow in said first output winding, means for directing said current flow back to said feedback winding of said first fluxsustaining element to produce a second flux change in said first flux-sustaining element, said first inhibit winding connected in series with said input winding of said second flux-sustaining element for inhibiting the magnetic eifect of feedback current in said first flux-sustaining element when and only when said input winding of said second flux-sustaining element is energized, and means for directing current flow in said second input winding.

27. In a magnetic control system, a plurality of magnetic flux-sustaining elements having input and output windings associated therewith, means including a third winding associated with said flux-sustaining elements for producing a flux change in said elements thereby causing current flow in said output windings, the output winding of each magnetic flux-sustaining element connected to the input winding of the succeeding magnetic flux-sustaining element, and means in circuit with the output winding of said first magnetic flux-sustaining element for directing said current flow back to said input winding of said first of said magnetic flux-sustaining elements to produce a second flux change in said flux-sustaining element during the operative cycle initiated by a flux change in said input winding.

28. In a magnetic control system, a magnetic fluxsustaining element having input and output windings associated therewith, means for producing a flux change in said element and thereby causing current flow in said output winding, means for directing said current flow back to said input winding to produce a second flux change in said flux-sustaining element, and winding means on said fluxsustaining element for selectively inhibiting said second flux change.

29. In a magnetic control system, a magnetic fluxsustaining element of material having high magnetic retentivity, means for entering a signal in said magnetic flux-sustaining element, means for applying signal shifting energy to said magnetic flux-sustaining element, means directly co-acting with said signal shifting means for reentering the storage of an entered signal in said magnetic flux-sustaining element notwithstanding operation of said signal shitting means, and separate inhibit means for terminating the storage of said entered signal.

References Cited in the file of this patent UNITED STATES PATENTS 2,500,294 Phelps Mar. 14, 1950 2,640,164 Giel et a1. May 26, 1953 2,681,181 Spencer June 15, 1954 2,686,632 Wilkinson Aug. 17, 1954 2,703,202 Cartwright Mar. 1, 1955 2,778,006 Guterman Jan. 15, 1957 2,844,310 Cartwright July 22, 1958 OTHER REFERENCES Ramey: The Single-Core Magnetic Amplifier as a Computer Element, A.I.E.E. Transactions, vol. 71, part I (1952), pages 442 to 446.

Guterman: Magnetic Core Ring Counter, Proceedings of the National Electrical Conference (February 1954) (pages 665669).

Claims (1)

1. A SUBTRACTER INCLUDING AT LEAST FIRST, SECOND AND THIRD MAGNETIC ELEMENTS, FIRST CIRCUIT MEANS COUPLED TO SAID FIRST, SECOND AND THIRD MAGNETIC ELEMENTS FOR WRITING A ONE IN SAID FIRST AND THIRD MAGNETIC ELEMENT AND A ZERO IN SAID SECOND MAGNETIC ELEMENT, SECOND MEANS COUPLING SAID SECOND MAGNETIC ELEMENT TO SAID FIRST MEANS AND ADAPTED TO WRITE A ONE IN SAID THIRD MAGNETIC ELEMENT, THIRD MEANS COUPLED TO SAID FIRST AND SECOND MAGNETIC ELEMENTS FOR WRITING A ONE IN SAID SECOND MAGNETIC ELEMENT AND A ZERO IN SAID FIRST MAGNETIC ELEMENT, SHIFT MEANS COUPLED TO SAID FIRST, SECOND AND THIRD MAGNETIC ELEMENTS, AND FOURTH MEANS COUPLED TO SAID FIRST MEANS FOR SUPPLYING INPUT SIGNALS REPRESENTATIVE OF A NUMBER.

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