US3099826A - Static logic annunciator - Google Patents

Description

July 30, 1963 D. H. NOREEN ETAL sTATc LOGIC ANNUNCIATOR Filed Jan. 2, 1958 '7 Sheets-Sheet 1 C by R nz, GJJ 2 no H ...#5 ..5 2 2 a O 2 G 7 7 4 M M 1J 2 m 2 2 5 5 3 l f 94. 7 l 5 m s J f an n ,Mw m l l b 4 2 1111 3 4 3 2 am 2 7 7 4 bzl. B zov J 2 5 n M 4- im N 4 1 9 6 .l 6 A rl 6 6 7 6 9 2 r new .w A S H l./l .U S 1 SRL f 4 6 7 4 @s n 6 i ,w\ nlv\ 7 5 3% O nw. 1:52 560 f l 5 l 5 J 8 9 8 73987 6 5 7 CCCLL 54 I 2 7 6 7 7 4 N L 5 l W 7 1 3 S d f 7 Q A 4 3 4 W. 4 h H H 5 8 k o 2 3 3 m l.. 3 5 uw 5 f 5 4 4 9 I|| Fvrrm 6 4 7 2 1 4 o I. 2 O H 1 3 8 .m O M 2 mw 2 7 l 8 I l 0 3 2 E f 3 w M 2 l 4 l a .D E. M M I C 3 Wr n 9 5 8 Mv D I w. z m mi M 4 A: I 5 M. a \|C\b 5 D 7C 7 .Lv 2 C R 45 2 M d nl. 3 0 BN. m... 2 2

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INVENTORS Donald H. Noreen und \(/slc|ler F. Guenther.

' ATToR Y wlTNEssEs @wy Mw July 30, 1963 D. H. NOREEN ETAL 3,099,826

sTATIc LOGIC ANNUNCIATR Filed Jan. 2, 1958 7 sheets-sheet 2 als '4711. |85 I :o

50e |84 34 40g A ORB Ga f a l |82] 30750- FlClShr FH12- AN2 d Bu--LOB- Buzzer Buzzer July 30, 1963 Filed Jan. 2. 195s D. H. NOREEN ETAL STATIC LOGIC ANNUNGIATOR '7 Sheets-Sheet 3 Flasher Buzzer ANI6 ORIO

July 30, 1963 D. H. Nom-:EN ETAL sTATIc LOGIC ANNUNCIATOR Filed Jem.` 2, 1958 zlsb I DCI July 30, 1963 D, H, NQREEN ETAL 3,099,826

STTIC LOGIC ANNUNCIATOR 'T Sheets-Sheet 5 Filed Jan* 2, 1958 July 30, 1963 D. H. NoREEN ETAL sTATIc LOGIC mummcnworaA '7 Sheets-Sheet 6 Filed Jan. 2, 1958 alecm alarm United States Patent O 3,099,826 STATIC LOGIC ANNUNCIATOR Donald I-I. Noreen, Pittsburgh, and Walter F. Guenther, Penn Township, Allegheny County, Pa., assignors to Westinghouse Electric Corporation, East Pittsburgh, Pa., a corporation of Pennsylvania Filed Jan. 2, 1958, Ser. No. 706,688 4 Claims. (Cl. 340-226) This invention relates to annunciators of the type which embody saturable core elements or other static devices lto perform the various annunciator logic functions.

An object of -th-is invention is to provide in a static element annu-nciator a static element means tor actuating an alarm .in response to the operation of a condition responsive device and lincluding means -for continuing actua- .tion of the alarm even `att-ter termination of operation of the condition responsive device.

Another object of this invention is to provide in an annunciato-r, sta-tic logic means for energizing an indicator in response to the operation of a signal initiating device and includ-ing static logic means for energizing an alarm in response to .the termination of operation of the signal device.

A further object of this invention is to provide in a static logic an-nunciator, static logic means which responds to an abnormal signal -to sound a iirst alarm and energize an indicator, then responds to an acknowledge signaly to deenergize the alarm and cha-nge the energized -condition of the indicator, and then responds to the termination ot the abnormal condition to again change the energized condition of the indicator and at .the same time to energize a second alarm and finally to respond to a second acknowledge signal to deenergize both the indicator and the second alarm.

It is also an object ot .this invention to provide in a static element plug-in unit a static element means having circuit terminals releasably plugged in .to connector means in a power track or bus :arrangement which connects the static elements to alarms, an indicator, signal devices and a power supply to thus provide a complete annunciator.

Another object of this invention is .to provide in a plug-in unit a static element circuit having circuit terminals Ifor connecting to each of an indicator, one or more alarm-s, a power supply, a plurality of switch means, and a ilashcr to provide a complete annunciator.

lt is also an object of this invention to provide in an annunciator system a plurality of static element annunciators each `adapted to actuate an individual alarm in response to an individual signal initiating device `and each adapted to respond to a single test means connected in common to all annunciators to test all the annunciator circuits and indicators.

It is a further object of this invention to provide in an annunciator system a plurality of static element plugin units each releasably connected to a power track or bus unit which connects each plug-in unit to a common power supply, common alarms and common signal switches.

lt is a yfurther obj-ect of -this invention to provide a stat-ic asher unit having an oscillator stage comprised of static elements and having a buffer stage comprised of static elements.

Other objects of the invention will in part be obvious and will in part appear hereinafter.

This static logic annunciator is :of the type which employs static elements to provide various logic `functions which actuate audio ala-rrns and visual indicators in response to predetermined conditions at monitored points. In this annunciator the magnetic amplifiers provide the basic logic functions AND, OR, AND-NOT and IN- HIBITED AND-NOT.

3,099,826 Patented July 30, 1963 ice As used in this application, a static logic AND is an element which provides an output signal only when all o-f a given number ci input signals are present.

As used in this application, a static logic OR is an element which provides an output signal when any one of a plurality of input signals are present.

A static logic AND-NOT is an element which provides an output signal in response to one input signal, but only in the event that a second input signal is absent.

A static logic INHIBITED AND-NOT is an element which provides an output Isignal when a first input signal is present and when a second input signal is not present or when the rst and second input signals are present and when a .third input signal is present.

This annunciator is designed to respond to digital monitors of conventional types including pressure switches, ratio switches, temperature switches, limit switches and proximity switches, all of which operate to close a contact to thus provide an input signal to the annunciator.

The basic annu-nciator is comprised of an audio alarm system, a visual indicator system and an acknowledge system. When an abnorm-al condition is signalled by the monitor device, the alarm system actuates an audio alarm such as a bell, and the visual system ilashes a lamp. When the operator closes a momentary switch to actuate the acknowledge system, the bell is deactuated .and the flashing lamp signal is changed to a steady signal. When the abnormal con-dition is corrected, the lamp is turned off. In the abnormal condition is corrected before the acknowledge system is actuated, the annunciator returns to normal to thus silence the alarm and extinguish the indicator. It is seen that a transitory abnormal condition would produce transitory alarm signals and indicator signals. If desired, the visual indicator system may be modified to canse the lamp to glow steady in response to the abnormal condition as well yas in response to the acknowledge signal.

A lock-in system can be added to the basic system hereinbefore described. The lock-in system provides for continuous actuation of the audio alarm and continuous ashing of the lamp even though the fanlt or abnormal condition is only transitory. The operation of the combined basic system `and lock-in system is otherwise identical to the basic system alone `as hereinbeiiore described.

A ringback system can be added to the basic system or to the combined basic system `.and lock-in system. The ringback system provides for actuation of a dierent audio signal when the abnormal condition has been eliminated. When the ringback system is included in the annunciator, an `abnormal condition is indicated by fa ilashing visual indicator rand a sounding audio alarm 'as` in the annunciator hereinbefore described. Similarly, when the abnormal condition is acknowledged, the audio `alarm is silenced and the ashing signal is changed to a steady signal Ialso as hereinbefore described. When the abnormal condition is eliminated, the ringback system causes the visual indicator to return to the ilashing condition and simultaneously actnates a different -audio alarm, such as a buzzer. There-after, when the openator aga-in actuates the saine momentary -acknowledge switch, the buzzer is turned oit and the lamp is extinguished.

A composite iannunciator system may be constructed comprising a plurality of annunciators of different types as hereinbefore described, each annunciator responding to one particular point or monitored Variable and each having its individual visual indicator. The annunciato-rs may otherwise be connected to a common power supply to energize the static elements, a common buzzer, a common bell, a common acknowledge switch and a common flasher unit tor flashing the visual signal as described above. In addition, the annunciators may be connected in common to a single test switch for applying a test signal to duplicate a fault or abnormal condition signal. In such a test circuit, 4a rectifier is connected to each annunciator to isolate each point and its monitor 'from all the other points but at the same time allows simultaneous testing of all the logic, indicators and `alarms at all points.

Each of the logic functions `of the individual annunciators in the herein-before described composite annunciator may be arranged, fixed, and encapsulated in a compact manner in a relatively small container unit having plugin terminals at yone end 'and additional terminals at the other end. The plug-in terminals at the one end extend internally of the unit to serve -as power inputs for energizing the vlarious static elements, to serve as signal inputs from the flasher, `acknowledge switch, and test switch, and to serve as signal outputs to the bell and buzzer. Thus, the terminals at the one end are related to common characteristics of all the annunci-atom. The terminals at the other end of each container unit serve as inputs from a monitor device and as an output to a visual indicator. Thus, the terminals at the other end of each plug-in container are related to characteristics individual to each annunciator. The plug-in terminals at the one end of each container are adapted to be received in a power track having a socket connector means for each annunciator container, with the sockets connected to a plurality of bus bars for connecting the annunciator-s in common to the buzzer, bell, test switch, acknowledge switch and power supply as described above. A single flasher unit is encapsulated ina separate container unit having appropriate plug-in terminals on one end for insertion in one of the channel sockets to connect to appropriate power bus blars and to connect to a flasher input bus bar common to all annunciators.

For la more complete understanding of the nature and scope of our invention, reference may be made to the following detailed description which mlay be read in connection with -the accompanying drawings, in which:

FIGURE 1 is a schematic diagram of an annunciator embodying the invention in lone of its forms;

FIG. 2 -is Aa symbolic schematic circuit of the annunciator of FIG. 1;

FIG. 3 is a symbolic schematic circuit of a modification of the annunciator of FIG. l and FIG. 2;

FIG. 4 is a symbolic schematic circuit of another modification ofthe Iannunciator of FIG. 1 and FIG. 2;

FIG. 5 is a symbolic schematic circuit of another modification of the annunciator of FIG. 1 land FIG.2;

FIG. 6 is a symbolic schematic circuit of another annunciator embodying the invention;

FIG. 7 is a top plan view of a plug-in annunciator static logic container;

FIG. 8 is an end view lof the plug-in container yof FIG. 7;

FIG. 9' is a bottom plan View of the printed circuit board;

FIG. 10 is a schematic diagram of an annunciator system; and

FIG. 11 is -a schematic diagram 'of a flasher.

Static Logic Elements The static elements which perfo-rm the hereinbefore described logic functions will be individually described in order to facilitate a better understanding of the annu-nciator. Thereafter, the annunciator and its modifications will be `described in terms of interrelationships between and 4among the static elements.

Referring now to FIG. l, there is disclosed a static logic AND element A10 including a toroid SL2, a gate circuit and a reset circuit. The toroid SL2 is comprised of a saturable core 11, gate winding 12 and lreset winding 17. The gate winding is energized from a voltage supply tap Ga of secondary winding 14 of transformer 13 (FIG. 10) through an appropriate one of bus bars 210, to connect to annunciator power input terminal 14Ga (FIG.

l) in a manner hereinafter explained, terminal 14, conductor 15, terminal 16, winding 12, and rectifier 19, all taken in conjunction with a non-linear impedance including transformer supply tap Gb, one of bus lines 210, annunciator input terminal 20Gb, terminal 21, conductor 22, terminal 23, conductor 24, terminal 25, resistor 26, output terminal 18, `conductor 27, terminal 28, rectifier 29 of a pair of rectiliers 30, terminal 31, conductor 32, annunciator common terminal 33Cb, a bus bar 210, and transformer common tap Ca.

In FIG. l and in FIG. 1l, the terminal reference numerals ending with given letters are connected to transformer power taps in FIG. 10 having the same letters as reference indicia. For example, `annunciator terminal 41Ca is connected to transformer tap Ca. The reset winding 17 of AND element A10 is energized from FIG. l0 through transformer terminal Rb, a bus bar 210, annunciator power input termina-l 34Rb, conductor 35, terminal 36, conductor 37, winding 17, and rectifier 39 of pair of rectifiers 40 taken in conjunction with a non-linear impedance including transformer common tap Ca, a bus bar 210, annunciator common terminal 41Ca, terminal 42, conductor 43, terminal 44, conductor 45, terminal 46, conductor 47, terminal 48, rectifier 49, terminal 50, conductor 51, terminal 52, terminal 53, rectifier 54 of pair of rectifiers 40, terminal 55, resistor 56, terminal 57, conductor 58, terminal 59, conductor 60, terminal 61, conductor 62, terminal 14, annunciator terminal 14Ga, a bus bar 210, and transformer terminal Ga. The manner in which particular and appropriate ones of bus bars 210 are connected to provide power for energizing the static elements will be explained more fully hereinafter in the description of the annunciator. The function of the nonlinear impedance will be explained more fully hereinafter in conjunction with a description of the transformer 13.

When transformer 13 is energized, the gate winding 12 of static AND element A10 will be energized from tap Go on alternate half cycles to produce positive saturation of the core 11. On successive half cycles following such positive saturation, the reset winding 17 is energized from tap Rb to produce negative saturation to thus establish a reset condition for the core 11. Accordingly, all the voltage from the transformer winding through tap Ga will appear across winding 12 and no effective output will appear at the output terminal 18. lf a signal having the same phase as the reset voltage and having a voltage equal to or greater than the reset voltage is applied to the A10 input terminal 55 to thus oppose the reset voltage, the flow of reset current will be blocked at terminal 55, and accordingly gating will result to provide an output through terminal 18 to yconductors 27 and 63. In a system involving cascaded static elements as in the annunciators hereinafter described, the gating output of one static element provides the input voltage or driving voltage to oppose the reset voltage of another static element.

The function of the non-linear impedance in the reset circuit is to provide a low impedance in series with the reset voltage to thus allow the transformer voltage to completely reset the core when an opposing blocking voltage is absent, Ibut at the same time present a high impedance to provide the least loading of the preceding driving static element when the driving static element is gating an output. The function of the non-linear impedance in the gating circuit is to assure that the output of a static element is never positive with respect to common during any gating half cycle when the core is unsaturated and subject to exciting current only. To achieve these functions, the non-linear impedance in the reset circuit is negative biased with respect to the reset voltage on each reset cycle while the non-linear impedance in the gate circuit is negative biased with respect to the gate voltage during a gating half cycle. For a detailed description of the function and operation of the non-linear impedance, reference is made to copending application Serial Number 640,006, filed February 13, 1957, which issued lune 19, 1962, as U.S. Patent 3,040,242.

Ra, a reset voltage tap, is negative going with respect t0 common. Thus, these two taps provide the alternate gate and reset half `cycles for a given static element. The tap Ga is a gate voltage tap 180 degrees out of phase with the first-mentioned gate tap Gb and may be used to provide the 180 degree out of phase relationship between a gate voltage from tap Gb and its associated fnon-linear impedance or may be used in association with the reset tap Rb to operate a different static element having `different phasing.

Inasmuch as the hereinafter described annunciator systems require a plurality of static elements to be arranged so that one drives another, it is necessary that an in-phase relationship exist lbetween the gating voltage o-f the driving saturable core device and the reset voltage of the driven saturable core device to provide the desired blocking action. The various taps of the transformer 13 as described above provide means for accomplishing this type of phase relationship as is seen in comparing the circuits of the individual static elements as hereinafter described. Practical values which may be used are volts for the gate taps Ga and Gb and 8 volts for the reset taps Ra and Rb. The transformer 13 steps down the conventional 115 volts and 60 cycles to these gate and reset voltage values. The taps Rc and Rd provide reset voltages of 8 Volts to the amplifier only.

The reset taps Rb and Ra of transformer 13 cooperate with a saturable reactor SR to provide distorted reset voltages for the various static element reset circuits. The distorted reset voltage is necessary to compensate for the distorted output voltages which result because of the failure of practical magnetic core materials to produce the theoretically desirable perfectly square hysteresis loop. This distortion is cumulative through a plurality of cascaded elements and 4may eventually cause the system to cease operation. The saturable reactor SR produces a reset voltage distortion similar to the gate voltage distortion to thus provide a signal which can he completely block-ed by the distorted -gate voltage of the preceding static element. For a detailed description of the structure and operation of this saturable reactor in a transformer of the type disclosed herein, reference is again made to copending application Serial Number 640,006, entitled Magnetic Amplifier Systems, filed February 13, 1957, and assigned to the same assignee as this application.

Also in FIG. l there is disclosed a static logic AND- NOT element AN2 including a toroid SL4, a gate circuit and two reset circuits. The toroid SL4 is comprised of a saturable core 65, gate winding 66, reset Winding 67 and reset winding 68. The gate winding 66 is energized from a transformer supply tap Ga, a bus bar 210, through annunciator power input terminal 14Ga, terminal 14, conductor 15, terminal 116, conductor 69, Winding 66 and rectifier 7-1, all taken in conjunction with a non-linear impedance including transformer common tap Ca, a bus Ibar 210, annunciator terminal 41Ca, terminal 4'2, conductor 43, terminal 44, rectifier 72, terminal 73, resistor 74, terminal 23, conductor 22, terminals 21 and 20Gb through a bus bar 210 to transformer power tap Gb. The

`reset winding 67 is connected in circuit with transformer ,tap Rb, a 1bus bar 210, annunciator terminal 34Rb, terminal 36, winding 67 through rectifier 75 of a pair of rectifiers 76 to AND input terminal 82 through a nonlinear impedance including transformer common tap Ca, a bus har 210, annunciator terminal 41Ca, terminal 42,

conductor 43, terminal 44, conductor 45, terminal 46, conductor 47, terminal 48, rectifier 49, terminal 50, rectier 83 of pair of rectitiers 76, resistor 84, terminal 80, conductor 87, terminal 16, conductor A15, terminal 14, annunciator terminal 14Ga, afbus lbar 210v and transformer tap Ga. The reset winding 68 is connected to a NOT input terminal 88 through conductor 89 in circuit with a rectifier 90 of pair of rectifiers 78 and in circuit with a non-linear impedance circuit including transformer common tap Ca, a bus har 210, annunciator terminal -41Ca, terminal 42, conductor `43, terminal 44, conductor 45, terminal 46, rectifier 77 of pair of rectifiers 78, resistor 79, terminal 80, conductor 87, terminal 16, conductor 15, terminal 14, anuunciator terminal 14Ga, a bus par 210, and transformer tap Ga.

With the transformer 13 energized, the -gate winding 66 will Ibe energized on alternate half cycles to produce positive saturation of core 65. The reset Iwinding 67 Will be energized on successive half cycles following positive saturation to produce negative saturation of core 65 to thus effect reset. Accordingly, all the voltage through tap 14Ga will appear across the gate winding 66 and no effective output voltage will appear at the output terminal 73. If a signal having the same phase and voltage as the reset voltage across winding 67, as may :he provided the gating output from another static element, be applied to the AND' terminal 82 through rectifier 83, the iiow of reset lwill be blocked land gating will result with the transformer voltage appearing yacross the output through terminal 73 and rectifier 82. If a like opposing voltage be applied to the NOT terminal 88, reset winding 68 is energized to produce negative saturation of core 65 causing reset of core 65 whether or not an input is present at AND terminal 82, thus terminating the output from the gate circuit of ANZ.

The static logic AND-NOT element AN3l is structurally and operatively identical to AND-NOT element ANZ previously described and includes a toroid SL7 having a saturable core, a gate winding 113 and two reset windings .114 and 115. The gate winding 113 is energized through transformer tap Gb, a `bus bar 2-10, terminal 20Gb, conductors 22, 24, `115, -116 and 117, winding 113, rectifier 118 through a non-linear impedance including transformer tap Cb, conductors v32, and 1119, terminal 102, rectifier 103, resistor 104, conductor 62, terminal 14Ga, -a bus fbar 210, and transformer tap Ga. The reset winding circuit includes NOT input conductor 121, winding `115 and a non-linear impedance including tap Cb, terminal 33Cb, conductors 32 and 100', terminal 101, rectifier 122, resistor 123, conductors 117, 116, 1115, 24 and 22, terminal 20Gb, a bus =bar 210 and tap Gb. The reset winding 114 is energized from transformer tap Ra, a Ibus bar 210, terminal 122Ra, conductor 1'20, winding 114, rectifier 301, all taken in conjunction with a nonlinear impedance including tap 41Ca, rectifier 125 of rectifier pair l12.6, conductor 127, rectifier 128, resistor 129, conductors 117, 116, 115, 24 and 22, terminal 20Gb, a |bus bar 210 and tap Gb.

The static logic INHIBITED AND-NOT element IANI includes a toroid SL3, agate circuit and two reset circuits. The toroid SL4 is comprised of a saturable core 91, gate Winding 92 land reset windings 93 and 94. The gate winding 92 is energized from transformer ytap Ga, a bus bar 210, Fanmlnciator terminal 14Ga, terminal 14, conductor 62, conductor 60Windinfg 92, rectifier 38, to output terminal 94, conductor 181 and a non-linear impedance including transformer tap Ca, `a bus bar 210, annunciator terminal 41Ca, rectifier 125, conductor 181, resistor 228, conductor 154, terminal 20Gb, a bus bar 210 and transformer Gb. The reset winding 93 is energized from transformer terminal Rb, a bus bar 210, terminal 34Rb, conductors 35 and 37, conductor 95, reset winding 93, rectifier 96 of pair of rectifiers 98, to AND input terminal 99, through a non-linear impedance including transformer tap Ca, a bus bar 210, annunciator common input terminal 33Cb, conductors 32 and 100, terminal 101, terminal 102, rectifier 103, rectifier 105, resistor 106, conductor 62 to terminal 14Ga, a bus bar 210 and transformer tap Ga. Rectifiers 105 and 177 comprise the two inputs of OR element OR4 having an output coinciding with AND input terminal 99. The reset winding 94 is energized through NOT input conduct-or 107, winding 94, rectifier 108 of pair of rectiers 109 and a non-linear `impedance including common tap Cb, annunciator terminal 33Cb, conductors 32, 100, 119, rectifier 110 of rectifier pair 109, resistor 111, and conductor 62 connected to terminal 14Ga, a bus bar 210, and transformer tap Ga. The INHlBlTED AND-NOT element IAN1 4as described thus far is structurally and operationally the same -as AND-NOT elements ANZ or AN3 previously described. However, INHIBITED AND-NOT element IAN1 is provided with an input rectifier 112 for passing an input signal having the same phase land voltage as that across reset winding 94 to oppose the reset voltage through reset rectifier 108, as previously described, to thus oppose and inhibit the function of the NOT reset circuit. Accordingly, if ian INHIBIT signal from the gating output of another static element is provided in opposition to a NOT signal at the same time the AND signal is present, core 91 is not reset and on the next half cycle of the transformer an output signal is gated through rectifier 38.

The static logic INHIBITED AND-NOT element IAN2 is structurally and operationally identical with the element IAN1 described immediately above and includes a toroid SLl having a saturable core 130, a gate winding 131, land two reset windings 132 and 303. The gate winding is energized from tap Gb, a bus bar 210, terminal Gb, conductors 22, 24 and 115, winding 131, through rectifier 300 in conjunction with a non-linear impedance including tap Ca, a bus bar 210', terminal 41Ca, conductors 43, 45 and 47, rectifier 49, conductor 51, resistor 133, conductors 58, 60 and 62 Ito terminal 14Ga, 'a bus bar 210 land tap Ga. The reset Winding 303 is energized from NOT input conductor 134, winding 303, rectifier 302 of rectifier pair 13'5 and is connected to INHIBIT terminal 136 through a non-linear impedance including tap Ca, a bus bar 210, terminal 41Ca, conductors, 43, 45, 47, bridge rectifier 137, conductors 138, 139 and 140, rectifier 141 of rectifier pair 135, resistor 142, conductors 116, 115, 24, 22 -to terminal 20Gb, a bus bar 210 and tap Gb Tihe reset winding 132 is energized from tap Ra, a bus bar 210, terminal 122Ra, winding 132, rectifier 143 of rectifier pair 144 and is connected to the AND input terminal 145 in conjunction with a nonlinear impedance including common tap Cc, bridge rectifier 146 (FIG. l0), a bus bar 210, annunciator terminal 215, rectifier 148 of pair of rectifiers 144, resistor 149, conductors 116, 115, 24 and 22 to terminal 20Gb, a bus bar 210iV and tap Gb. Rectifiers 148 and 150 comprise the two inputs of OR element ORS which provides the input to AND terminal 145.

The static element amplifier A11 is oper-ationally ident-ical to the prevously described AND element A10. Amplier A11 differs thereover only in respect to obvious changes such as a decrease in the number o-f windings on the core to change the power output. Amplifier A11 includes a toroid SLS having a saturable core 151, a gate winding 152 yand a reset winding 153. The reset winding is energized from tap Gb, a bus bar 210', terminal 20Gb, conductor 154, winding 152, and rectifier 155 and is connected to output terminal 212. The reset winding 153 is energized from tap Rc, a bus bar 210, terminal 156Rc, through winding 153 and is connected to each of three AND input terminals 157, 158 and 159l through a rectifier individual to each input, with each rectifier taken in conjunction with a non-linear impedance individual -to each input terminal. Rectifier 160 of rectifier pair 161 connects winding 153 t0 AND input terminal 157 in conjunction with a non-linear impedance including 8 common tap Cb, terminal 33Cb, conductor 32, rectifier 29, conductor 27, conductor 63, sign-al input rectifier 162 of pair of rectifiers 161, resistor 163, terminal 25, conductors 24 and 22 to terminal 20Gb, a bus bar 210, and tap Gb. Rectifiers 162 and 169 constiute static OR element OR1 having an output coinciding with AND input terminal 157. Rectifier 164 of pair of rectifiers 165 connects winding 154 to AND input terminal 158 through a non-linear impedance including rectifier 29, conductors 27 and 63, rectifier 166 of pair of rectifiers 167, resistor 168, conductors 24 and 22 and terminal 20Gb, a bus bar 210 `to tap Gb. Rectifiers 166 and 170 comprise static OR2 having an output coinciding with AND input terminal 158. Rectifier 171 of rectifier pair 165 connects winding 153 to AND input terminal 159 through a nonlinear impedance including tap Ca, a bus bar 210, terminal 41Ca, conductors 43, 45, 47, bridge rectifier 137, conductors 138, 139, 172, rectifier 173 of rectifier pair 174, resistor 175, conductors 24 and 22, terminal 20Gb, a bus bar 210 and tap Gb. Rectifiers 176 and 173 comprise OR3 having -an output coinciding with AND input terminal 159.

The Annuncator The khereinbefore described static logic elements are interconnected with each other and are connected with various signal switches, alarms, and indicators so as to provide the hereinbefore described annunciator functions.

Referring now to FIG. l and to FIG. 2 and to the plug-in arrangement and power supply 13 of FIG. 10 to be taken in conjunction therewith, there is disclosed such an annunciator having both lock-in and ringback. It will be seen that an abnormal condition at a monitored point will cause normally open contact 176 to close to thus provide an input signal from source 305 to the annunciator. A direct current source DCl including a transformer 304 in conjunction wtih resistor 225 and a rectifier 137 may be used to step-down the voltage to one suitable for operation of the static logic elements. For example, a conventional l15 volt, 60 cycle signal may be stepped-down to l5 volts whereafter the bridge rectifier 137, comprised of a first pair of rectifiers 226 and a second pair of rectifiers 227, provides a full wave rectified positive input through signal conductors .138, 139 and 172 through rectifier 177 of OR4 to block reset of core 91 through winding 93 of INHIBITED AND-NOT IAN1 which then gates an output through conductors 178 and 179* through rectifier 180 to sound the bell alarm. The output from IAN1 also provides a signal through conductor 181 and rectifier 169 of ORI to AND input terminal 157 of amplifier A11. A flasher, hereinafter described in detail, provides a pulsing output signal through terminal 213, signal conductor 182, and rectifier 176 of OR3 to AND input termin-al 159 of A11 and further provides a signal through conductor 182 and rectifier 170 of OR2 to AND input terminal 158 of A11. The input signal through contact 176 also is provided through conductor 172 and rectifier 173 of OR3 to AND terminal 159 of A11. Thus, the combined steady input signals to AND 157 and AND 159 and the pulsing input to AND 158 provides a pulsing or fiashling output signal from A11 to the lamp.

The output signal from IAN1 also provides a signal through signal conductors 178 and 1,27 to AND input terminal 124 of AND-NOT element AN3 which blocks reset of its saturable core to cause it to gate an output through rectifier of OR4 to AND input terminal 99 of IAN1 to thus provide IAN1 with an input even if the fault signal should disappear. Thus, it is seen that AN3 with its INHIBIT connection to IAN-1, its OR4 connection to IAN1 and its feedback connection from the output of IAN1 provides the lock-n system.

The input signal through contact 176 also provides an input signal through signal conductor to INHIBIT terminal 136 of INHIBITED AND-NOT element IAN2 and provides an input signal through signal conductor 89 9 to the NOT input of AND-NOT element ANZ, neither of which signals have any immediate effect because the lack of signal inputs at their respective AND inputs permits reset of their respective cores.

When the acknowledge switch 147 is momentarily closed, a direct current source DCS including transformer 18S (FIG. 10) steps-down the 115 volt signal to 15 volts whereafter bridge rectifier 146 provides a full wave rectified input acknowledge signal to signal conductor 184. The acknowledge signal is provided through a bus bar 210 to acknowledge input terminal Z15`, signal conductor 134 as a NOT input to IANZ and through signal conductor 185 `and rectifier 148 of ORS to AND lterminal 145 of IANZ. Since the input signal through contact 176 is providing an input to the INHIBIT input of IANZ, the NOT signal will be inhibited and IANZ will gate an output through rectifier 132 to provide an input to AND terminal 55 of AND element A10. The ANDy element A10 then gates an output through signal conductor Z7 which provides a feedback through rectifier 150 of ORS to AND terminal 145 of IANZ to permit TANZ and yA10 to continue gating an output signal after the acknowledge signal is removed. Static elements IANZ and A10 thus constitute an AND-MEMORY- The output of A10 through rectifier 19` provides a steady input to AND terminal 157 of A111 through rectifier 162 of OR1. The output of A10 also provides a steady signal to AND terminal 158 through rectifier 166 of ORZ. These two input signals in conjunction with the previously described steady input signal to AND terminal 159 through rectifier 17S of ORS block reset of A11, causing it to change its flashing output signal to a steady output signal for the lamp. The acknowledge signal provides an input to the NOT reset winding of ANS through signal conductor 1211 to reset its core and termin-ate its output to IAN1. At the same time, the output of IANZ provides a NOT signal through signal conductor 107 to IAN1 to thus reset its core and eliminate its output to silence the bell. The output of IANZ also provides a signal through signal conductor 51 to AND terminal 82 of ANZ, but since the abnormal signal is still providing a NOT input to ANZ to reset its core, no output is gated.

When the abnormal condition is eliminated, contact 176 reopens to terminate its output signal. When this occurs, the input signal is removed from the AND terminal of 'lANl which has no effect because its core was previously reset by an output from IANZ, the INHIBIT signal is removed from TANZ having no immediate effect, the steady AND input signal is removed from AND terminal 159 through ORS, causing the lamp to resume its flashing condition, and the NOT input is removed from ANZ, thus permitting the AND input through conductor 51 to block reset of ANZ which then gates an output through rectifier StZ to actuate the buzzer, thus providing the ringback system.

When the acknowledge momentary switch 147 is again closed, a signal is applied through conductor 184 to the NOT input of IANZ, thus causing reset of lits core since the abnormal signal is no longer present at INHIBIT terminal 136 to inhibit the NOT signal. Thus TANZ ceases to gate an output to A10 and, accordingly, A10 likewise ceases gating an output to the two -AND input terminals 157 and 158 of A11 through ORI and ORZ respectively, thus causing the lamp to go ofi. Since the termination of an output from IANZ eliminates an input to AND terminal 82 of ANZ, the output signal from ANZ is terminated to silence the buzzer. lThe system is thus returned to normal.

To substitute a steady visual condition for the aforesaid flashing visual condition, a signal of the same phase as the reset voltage of amplifier A11 and having a voltage equal to or greater than the reset voltage thereof is substituted for the flasher input signal at flasher input terminal Z13. This is achieved through a two-way throw switch S07 which may connect either the flasher or an 10 appropriate transformer tap Ga for energizing OR elements ORZ and ORB. Thus the flasher may be entirely omitted if desired. It is to be understood that such an arrangement may be included in any of the annunciator systems disclosed in this application.

A test switch 186 is provided to duplicate an abnormal condition to thus test all -the logic elements, alarms and indicators of the 'annunciaton The test switch 186 is closed to provide a full wave rectified signal of 15 volts from a direct current source DC4 (FIG. 10) including a step-down transformer 187 (FIG. 10) and bridge rectifier 188, and a rectifier device 189 to signal conductor 138 leading from and connected to the contact 176 so as to duplicate an abnormal signal through the same annunciator input signal conductor 138 which provides an abnormal signal in response to the closing of contact 176.

Referring now to FIG. 3, there is disclosed a symbolic diagram of an annunciator having the same type of basic system and ringback system as that disclosed in F'IG. 1 and FIG. Z but showing modifications to be made when the lock-in system is removed. When an abnormal condition occurs, contact 17f6a closes to provide a signal to the AND input of AND-NOT element AN4, causing it to gate an output signal through rectifier a to energize the bell and also to provide an input signal through OR7 to output amplifier A13. At the same time the abnormal signal contact 176a provides an inhibit signal to INHIB- ITED AND-NOT element IANS, provides another AND input signal through OR9 to AN1S, and provides a NOT signal to AND-NOT element ANS. 'Ihese signals to IANS and AN5 have no immediate effect; but since A13 now is provided with two steady input signals through OR7 and DR9 and a flashing input signal through ORS from the flasher unit, A13 will gate a flashing output to the lamp. When the momentary acknowledge switch 147a is momentarily closed, a signal is provided to both the AND input and the NOT input of IANS and since the abnormal signal inhibits the NOT signal, IANS gates an output signal to AND element A12, which in turn gates an output thatis fed back through ORG to the AND input of IANS to thus complete the memory loop causing IANIS and A12 to continue gating an output even after the acknowledge signal is removed. The output signal of IANS provides a NOT signal to AN4 to eliminate its output and thus silence the bell. The output signal of IANS also provides an AND input signal to ANS, but the abnormal signal to the NOT input of ANS prevents an output signal from being gated to the buzzer. The output signal of A1Z provides two steady inputs to A13 through OR7 and ORS which cooperate with the abnormal signal through OR9 to cause A13 to gate a steady output to the lamp. The correction of the abnormal condition removes the steady input through OR9, causing the lamp` to resume its flashing condition, and also removes the NOT input signal to ANS', permitting it to gate an output to sound Ithe buzzer. When the acknowledge switch 147a is again closed, a NOT signal is provided to IANS, causing it to cease gating an output since the abnormal signal is no longer present to inhibit the NOT signal. A12 ceases gating an output to OR7 and to ORS to thus extinguish the lamp. AN5 ceases gating an output to thus silence the buzzer.

Comparing the annunciator of FIG. 3 with that of FIG. 1 and FIG. 2, it will be noted that INHIBITED AND-NOT element IANl of FIG. 1 and FIG. 2 has been changed to an AND-NOT element AN4 and that AND- NOT element ANS of FIGS. 1 and 2 and its associated signal conductors have been completely eliminated.

It is `considered to be obvious to those skilled in the art how the schematic diagram of FIG. 1 may be modified to eliminate the look-in system as disclosed in the modified symbolic diagram of lFIG. 3.

LReferring now to FIG. 4, there is disclosed an annunciator having the same basic system combined with lock-in and ringback as disclosed in FIG. 1 and FIG. 2 but showing modifications to be made when the ringback system is removed. When yan abnormal condition occurs, contact 176i: closes to provide an abnormal signal through R10 to the AND input of IAN17, causing it to gate an output to energize the bell and also to provide a feedback signal to the AND input of AN16. Since a NOT input signal `does not exist at the NOT terminal of AN16, it gates an output which provides an input signal through 0R10 to the AND terminal of `IAN17 so that IAN17 will continue to gate an output even though the abnormal signal is terminated. The output of IAN17 also provides an input through 0R12 to one AND input of A19 while a flasher unit provides a pulsing input signal through 0R13 which causes the lamp to flash. When the acknowledge switch 147b is closed, an acknowledge signal is provided to the NOT input of AN16` to reset its core and terminates its output which in turn removes the input through 0R10' to `IAN17 since the abnormal signal has terminated. 'Ihus IAN17 ceases gating an output to thus silence the bell and to terminate the input through 0R12 to A19 to thus extinguish the light.

Comparing FIG. 4 with FIGS. l and 2, it will be noted that the element AN2 of FIGS. 1 and 2 with its attending buzzer and signal conductors has been completely eliminated, that a two-input AND element A has been substituted for the INHIBITED AND-NOT element -IAN2 of FIGS. 1 and 2, that the abnormal signal input is connected to provide an INHIBIT signal to INHIBITED AND-NOT element IANZ, that the two-input AND preamplifier A19 has been substituted for the three-input AND preamplifier A11 of FIGS. l and 2, and the ilasher provides an input signal to only one of two OR units in F-IG. l4, while in FIGS. l and 2 the flasher provides an input signal to two of three OR elements connected to a three-input AND amplifier A11.

The hereinbefore .described feedback cooperation between AND-NOT element AN 16l and INHIBITED AND- NOT element lIAN17 of FIG. 4 and 4between elements ANS and IANl of FIGS. 1 and 2, provides a MEMORY circuit having a retentive memory. For example, in FIG. 4 the INHIBIT signal input to AN17 as provided by the output of A-N1-6- provides this retentive memory in the event lof polwer failure. It is possi-ble that reapplication of power after a power ffailure will cause A15 to gate an output when momentary acknowledge switch 147b has not been closed to thus provide a false or superfluous acknowledge signal to the -NOT terminal of IAN17 to turn on the MEMORY when .it should stay on. 'Phe output from AN16 to the INHIBIT terminal of IAN17 will block and nullify the effect of such an output from A15.

Referring now to FIG. 5, there is disclosed an annunciator comprised of the basic system such as that disclosed in FIG. l and IFIG. 2, ibut Without the ringback system and Without the lock-in system. When an abnormal condition occurs, contact 176c closes to provide an input signal to the AND terminal of AN21 which causes it to gate an output to actuate the bell and also to provide a signal through 0R22 to one AND input of amplier A24. A flasher unit provides a pulsing signal through 0R23 to the other AND input of A24, causing it to gate a pulsing output to flash a lamp. The abnormal signal is also provided to one AND input of A18. When the acknowledge switch 147e -is closed, an acknowledge signal is provided at the other AND input of A18, causing it to gate an output t-o the NOT terminal of AN21 to rest its core and terminate its output to thus silence the bell. The output signal from A13 provides an input signal to A20, causing it to gate an output signal which is fed back through 0R19 to one of the AND inputs of A18 to maintain the MEMORY loop signal even when the acknowledge signal is removed. The output signal from A20 also provides a steady input through 0R22 to one input of A24 and through 0R23 to l2 the other input of A24 so that it will now gate a steady output signal to the lamp. When the abnormal condition is eliminated, the Contact 176C reopens to terminate an input signal to A18. Therefore, A18 gates no output to A20, which then gates no output to A24 to thus extinguish the light.

The basic annunciiator system of FIG. 5 discloses means for interconnecting a plurality of annunciators in such fashion that each may be actuated by its individual contact for signalling an abnormal condition, and each may actuate its individual visual indicator, but at the same time all annunciators may be connected in common to a single flasher, la single bell, a single buzzer and a single test system. The additional rectifiers 180e and 18de represent audio alarm outputs from other annunciators identical to that shown in detail in FIG. 5. Thus, rectifiers `180C, ltld and 180e comprise an OR element 0R50 connecting the audio alarm systems of plural annunciators to a single bell. The addition flasher output conductors lZd and 182e lead to the other annunciator systems, thus connecting a single flasher in common with all annunciators. The additional conductors 184e and 184d lead to said other annunciators to conect the acknowledge switch 147e in common with all annunciators. The additional reotiers 189e' and 189e lead to the :other annunciators (not shown) where each additional rectifier is associated with an abnormal signal contact in the the same manner that rectifier 189e is associated with contact 176C. The reotifiers thus arranged provide for a single test switch to simultaneously provide a test signal to actuate all the logic systems, alarms and indicators in all annunciators, but at the same time provide isolation of each contact from all others so that each annunciator will respond only to an abnormal signal provided by its individual contact. It is to be understood that the aforementioned annunciator connector means may be used to couple annunciators of the type shown in any of FIGS. 2 through 6. The annunciators may be all the same or mixed indiscriminately.

Referring now to FIG. 6, there is disclosed a symbolic diagram of an annunciator not hereinbefore disclosed but which performs the same functions las the previously described annuncia-tor having a lock-in system and -a ringback system. The symbolic elements of FIG. 6 represent static magnetic elements of the type disclosed in FIG. l. It will be obvious to one skilled in the art how these static elements of the type shown in FIG. l may be inter- Iconnected to provide the logic functions disclosed in FIG. I6 and described in the following subject matter relating thereto.

`In FIG. 6, an abnormal condition causes a monitor device (not shown) to close normally open contact 30S which provides an input signal through 0R25 to the AND input of AND-NOT element AN26, causing it to gate an output signal to the AND input of AND-NOT element AN27 which then gates an output signal to actuate the bell. The output signal from AN27 also provides an input signal through 0R28 to an AND input of amplier A29 to cooperate with a pulsing input signal from the flasher through 0R30 to provide a pulsing or flashing output to the other AND input of A29. The output signal from AN27 also feeds back through 0R25 to the AND input of AN26 to provide a lock-in system. The output signal from AN26 also provides a signal to an AND input of AND element A31, which input is temporarily ineffective since no input signal is provided at the other AND input of A31. The input signal through contact 308 also provides a signal through 0R32 to the NOT input of AND-NOT element AN33, which signal is temporarily ineffective since no signal is provided to the AND input of AN33. When momentary acknowledge switch 309 is closed, an acknowledge signal is provided through OR34 to the NOT input of AN27 which causes AN27 to cease gating an output to thus silence the bell. The acknowledge switch also provides a signal through OR320 to the other AND input of A31, thus causing A31 to gate lan output through 0R30 to an AND input of A29, which output cooperates with a steady output signal through contact 308 and R28 to A29 to change the -iiashing lamp signal to a steady lamp signal. The output signal from A31 also feeds back through 0R35 to the AND input of AND-NOT element AN36 which responds to gate an output through OR320 to an AND input of A31, thus providing a MEMORY to persist in gating a steady output through 0R30 to A29 even after the acknowledge signal ceases. AN36 `also provides a signal through 0R34 to continue a signal to the NOT input of AN27 to maintain the bell in a silenced condition after the acknowledge signal h-as terminated. When the abnormal condition is eliminated, contact 308 reopens to terminate the signal through 0R25 to AN26 which responds to cease gating an output signal to an AND input tof A31. Accordingly, A31 no longer gates an output signal through 0R30 to A29, the abnormal signal no longer is provided through 0R28 to A29. Also with the removal of the abnormal signal through 0R32 to the NOT input of AN33, an output signal is gated from AN33 to the buzzer and through 0R28 to an AND input of A29 to cooperate with the flasher input signal through 0R30 to again ilash the lamp. When the output signal from A31 is terminated because of a lack of input from A26 as described above, the memory loop including A31 to AN36 is destroyed simultaneously with the forming of another MEMORY loop including AN36 `an-d AN33. 'The output from AN33 through 0R35 causes AN36 to gate an output signal to the AND input of AN33. When the acknowledge switch 309 is again closed, an acknowledge signal is provided through `0R32 to the NOT input of AN33 to terminate the output from AN33, which termination silences the buzzer, disrupts the MEMORY loop through 0R35 to AN36, and terminates the Signal through 0R28 to A29, thus causing the lamp to be extinguished. The function of capacitor 310 and the NOT input of AN36 is described below.

When the annunciator of FIG. 6 is operating at low voltage, due to normal iiuctuations in the power supply system, the hereinbefore described MEMORY loop comprised of AN36 and AN33 may not be formed as the other MEMORY loop is being terminated, because the two MEMORY loops coexist for only one gating pulse from AN36. At low voltage, one pulse is insufficient to lock-in MEMORY AN36 .and AN33 because the saturable magnetic cores in the magnetic devices are wound for maximum voltage. Accordingly, at low voltage a single pulse is insufficient to gate an output from AN33 which requires two input pulses to gate its iirst output pulse at half maximum voltage. Tol operate the annunciator at voltages as low as one-half normal, a capacitor 310 is provided and connected as sh-own in the output of A31. This capacitor is charged when A31 is gating an output through 0R30 in the manner hereinbefore described. When the abnormal signal terminates to cause AN26 to cease gating, an input to A31 thus causing A31 to terminate its output signal, capacitor 310l discharges through the feedback MEMORY loop through 0R35 to AN36 to thus effectively delay removal of the output from A31 and to thus cause AN36 to provide several output pulses to assure lock-in of the MEMORY comprised of AN36 and AN33 when the abnormal signal is removed.

The NOT input to AN36 from the output of AN27 is provided to compensate for the capacitor in the event of a power failure. If a power failure should occur after an abnormal condition occurred, but prior to acknowledgement of such abnormal condition, a reapplication of power normally should cause the lamp to flash and the bell to ring. The addition of the capacitor as above described gives rise to thepossibility of its discharge upon The output signal from' 14 reapplication of power to form MEMORY loop AN36 and A3l1 which would then operate in the manner hereinbefore described to provide false acknowledge output signals. Therefore, inasmuch as AN27 gates an output until there is an acknowledgement signal, AN27 provides a NOT input signal to AN36 to thus prevent the occurrence of the false acknowledge signal resulting from operation of the capacitor 310.

Plug-in Units As herein-before described, the `static logic elements of any of the annunciators of FIGS. 2 through 6 may be arranged, fixed and encapsulated in a compact manner in Ia relatively small container unit having suitable plug-in terminals Iat both ends. The plug-in terminals extend internally of the unit to be connected to the logic elements therein, and extend externally of the unit for connection to an appropriate power supply and other devices to thus complete the -annunciator system.

Referring now to FIGS. 7, 8 and 9, there is disclosed a static element plug-in unit 200* with the cover (not shown) removed. The unit 200 is rectangular in form and is comprised of two sides 201 and 202, two ends 203 and 204, and a bottom 205. The sides, ends and bottom may be rigidly connected to each other in any suitable manner. Within the container 200 are arranged a plurality of elements representative of conventional toroids, rectifier boxes and resistors which are interconnected with each other through a printed circuit board 206 of convenrtional type and having a plurality of conductors 207 thereon. The printed circuit board 206, shown in a top plan view in FIG. 7, may be fixed in the container unit in any suitable manner. FIG. 9 shows the printed circuit board in bottom plan view.

The various toroids, rectier boxes, resistors and conductors in container 200 correspond to the comparable toroids, single rectitiers, rectifier pairs, resistors and conductors as disclosed in the schematic diagram of FIG. l as modified by the teachings of the symbolic diagram of FIG. 3 showing the lock-in feature omitted. The toroids, resistors, rectiiiers and rectifier pairs in the container 200 have been given the same reference numerals as their comparable elements of FIG. l. The individual conductors of FIG. l have not been identified in the circuit board of FIG. 9 to avoid confusion in reading the drawing; however, the individual toroids, resistors, rectiiiers and rectifier pairs of FIG. 7 have been superimposed in outline form on the printed circuit 206 to clearly illustrate the relative positioning thereof with respect to the printed circuitry.

It will be obvious that the omission of the lock-in system yfrom FIG. l eliminates toroid SL7, conductors 121, 120, 117 and 127, rectiiers i122, 208, 123, 128, 118, 103, 112 and 177, resistors 129, i123 l'and 104, and requires that conductor 172 be disconnected from point 99 and reconnected to provide an input through rectiiier adjacent point 99.

In View of the foregoing, it fis considered obvious how other plug-i-n containers may be provided with appropriate printed circuit boards and associated static elements to provide the basic annunciator logic system of FIG. 5, lthe basic logic system with lock-in of FIG. 4, the basic logic system with ringback and lock-in of FIGS. l and 2, and the annunciator of FIG. 6.

A plurality of plug-fin terminals 209 extend internally and externally of end 203 of container 200 t-o serve as means for connecting the encapsulated static elements to a plurality of bus bars '210 (FIG. l0) which carry power inputs to the container 200 and which provide outputs to the various yalarm devices. In FIG. 9 the plug-in terminals 209 are shown connected to their respective annunciator terminals having the same reference numerals as the corresponding input or output terminals of the annunciator circuit of FIG. 1 and thus the function of each of the plug-in terminals 209 is obvious. It should be noted that though 'the internal circuitry of each of the annunciators hereinbefore described is different from the others, the input and loutput terminals are identical. Thus, it is seen that terminal A is the bell output terminal, terminal B is Ithe test input terminal, terminal C is the flasher input terminal, terminals D, E, F, H, I, J, and K are power terminals, terminals G and L are blank terminals, terminal M is the acknowledge input terminal, and terminal N is the buzzer output terminal.

A plurality of terminals 216 extend internally and externally of end 284 :of container 200. The terminals 216a and 216b are connected internally to terminals 217 and 218 of the logic system of FIG. 1 to provide external connections to the contact 176 (FIG. l0) and to a power source 30S to provide the abnormal input signal. If desired, the contact `176 may be connected across the power source of transformer 13. The terminal 216e connects internally to light terminal 212 (FIG. l) to provide an output terminal for connection to its individual lampy (JFIG. 10).

Referring now to FIG. l0, there is disclosed a complete annunciator system of the type her-einbefore described including the static logic plug-in unit 200 positioned so that its plug-in connector terminals 209 may be inserted into a `group of mating connector terminals 219 comprising a connector position in a power track '2.20y which includes ra plurality of such positions and a plurality of bus bars 210 with each bus bar connected internally of the power track in any suitable manner to one terminal of every posi-tion and with no terminal connected to more than one bus bar. The power track 220 may be comprised of two laterally connected power tracks of the type disclosed in detail in copending application Serial No. 651,085, filed April 5, 1957, to thus provide a single power track having sixteen bus bars therein and having sixteen plug-in mating connector terminals for each plugin connector position. Inasmuch as the disclosed plugin container unit 200 utilizes only 14 terminals 209, some of the bus bars will be unused as signal carriers but their mating terminals may be used as base supports for the hereinbefore described yblank container terminals G and L of FIG. 9. The bus bars 210 extend from the power track 221i and are connected to appropriate terminals of the power supply, the bell, the buzzer, the acknowledge signal switch 147 and the test switch 186, in the manner disclosed, to provide the hereinbefore described annunciator functions. The unused bus bars are shown extended from the power track and unconnected to other devices. It is obvious, if desired, to eliminate 'all unused bus bars and blank terminals. Thus, it is seen that bell output terminal A is connected through corresponding bus bar AA to the bell, test output terminal B is connected through corresponding bus bar BB to the test switch 186, and flasher input terminal C is connected to corresponding liasher 'output bus bar CC. It is seen :that the remaining terminals C through N are connected through corresponding bus bars CC through NN respectively to the appropriate power supply taps of transformer 13, to the acknowledge switch 147, and to the buzzer. It is obvious that additional plug-in container units 204m may be plugged in to the power track 220 at other plug-in connector positions to thus provide a composite annunciator system for monitoring plural points as hereinbefore described. The additional plug-in containers may be identical to plug-in container 201) in internal static logic elements or they may be different therefrom to provide the basic annunciator logic system alone or in combination with either the lock-in system or the ringback system as hereinbeforc described. A plug-in liasher unit 221, to be hereinafter described in detail, is provided in its own plug-in container unit having appropriate plug-in connector terminals to connect to appropriate transformer power supply bus bars in the vpower track 220, and to connect to bus bar 16 LL to provide a pulsing output signal to each of the flasher input terminals of the individual plug-in container units 200 and 20021.

A second power track 220a, identical in structure to power track 220, is provided to operate additional plugin u-nits (not shown) of the same structure as units 200 and 200a. Lt will be noted that bus bars AA through NN leading from track 221i are connected to correspondingly arranged bus bars in power track 220@ with the exception of the power input Ibus bars and other changes described below. Thus, the bus bars EE and JJ leading .to lopposed gate supply voltages have been interchanged in their connection to power track 2202: wh-ile bus bars FF and II leading to opposed reset supply voltages also have been interchanged in their connections to power track 221m. This linterchanging of bus connections reverses the operating phase of the annunciator units and asher unit in power track 220:1 with respect to the units and flasher of power track 220, thus permitting `a single transformer 13 to utilize the full cycle of each tap to operate all the units and iiashers in the two power tracks. In keeping with this phase reversal, the fiasher output bus bar of track 220a is connected through a two-way throw switch 310 to the power tap Gb, having a phase opposite that of rtap Ga. Also, in keeping with this phase reversal, the bus bar for driving the reset circuit [of the amplifier is connected to tap Rd, having a phase opposite that of tap Rc.

Flasher The fiasher disclosed in FIG. ll provides the pulsating signal to the lamp preamplifier in the manner hereinbefore described and is comprised -of a static element oscillator stage 222 and 'a static element buffer stage 223. The oscillator stage 222 is comprised of two static magnetic NOT elements N224 and N225 interconnected with each other and a pair of resistor-capacitor circuits to provide regenerative feedback to sustain oscillation. The buffer stage 223 is comprised of two static magnetic IN- HIBITED NOT elements IN273 and IN275 interconnected with each other and connected to the oscillator to provide high output power, to isolate the oscillator from its load, and to provide la fast switching action.

In :the oscillator stage 222, the rst NOT element N224 is comprised of a magnetic core 226 having a gating winding 227 which may be energized from transformer terminal Ga (FIG. l0) which may ibe connected to fiasher terminal 228Ga, conductor 229, winding 227, rectifier 230, rectifier '2311 of non-linear impedance 232, common conductor 233 and iiasher terminal 234Ca which may be connected to transformer common terminal Ca. The nonlinear impedance includes transformer terminal Gb, iiasher terminal 235Gb, conductors 236 and 236:1, resistor 237, rectifier 231, conductor 233, terminal 234Ca, a bus bar 210 and transformer terminal Ca. Rectifier 230 and nonlinear irnpedance 232 connect gate winding 237 to output terminal 240. It is to be understood that appropriate conductors such as bus bars `210 (FIG. l0) may interconnect the transformer terminals with their respective iiasher terminals. The NOT reset winding 228 is connected to a NOT input terminal 238 in circuit with a rectifier 239, rectifier 241 of non-linear impedance 242, conductor 233, terminal 234Ca, and transformer terminal Ca. Thus winding 228 is energized in response to a positive signal applied to NOT input terminal 238. The nonlinear impedance includes transformer terminal Ca, flasher terminal 23'4Ca, conductor 233, rectifier 241, resistor 311, conductor 229, fiasher terminal 228Ga and transformer terminal Ga.

The NOT element N225 of oscillator 222 is comprised of a magnetic core 312 having a gating winding 243 which may be energized -from transformer terminal Gb, through fiasher terminal 235Gb, conductor 236, winding 243, rectifier 244, rectifier 245 of non-linear impedance 246, common conductor 23351, ilasher terminal 234Ca 17 and transformer terminal Ca. The lnon-linear impedance A246 includes transformerk terminal Ca, flasher terminal 234Ca, conductor 233a, rectifier 245, resistor 247, conductors 229a and 229, flasher terminal 228Ga and transformer terminal Ga. Rectifier 244 and impedance 246 connect gate Winding 243 to output terminal 253. The magnetic core 3112 is also provided with a NOT reset winding 247 connected to NOT input terminal 248, rectifier 249, rectifier 2511 of non-linear impedance 250, conductor 23311, flasher terminal 234Ca, and transformer terminal Ca. Thus, reset lwinding 247 is connected to respond to a positive input applied at NOT terminal 248. The non-linear impedance 250 includes transformer terminal Ca, iiasher terminal 234Ca, conductor 233a, rectifie-r 251, resistor 252, conductor 236, terminal 23'5Gb and transformer terminal Gb.

The output terminal 240 of NOT'element N224 is connected through a capacitor 254 to the NOT input 248 of NOT element N225. The capacitor 254 is also connected in circuit with a resistor 255 and rectifers 256 and 259 which complete a hereinafter described discharge circuit lfor capacitor 254. Similarly, the output terminal 253 of NOT element N225 is connected through a capacitor 257 to the NOT input 238 `of NOT element N224. Capacitor 257 is also connected in circuit with a resistor 258 and rectiiiers 259 and 256 'which complete a hereinafter described discharge circuit for capacitor 257. The output terminal 240 of NOT element N224 and the output terminal 253 of NOT element 224 are each connected to an input of the buffer stage 223 in a manner hereinafter described.

In the buffer stage 223, the first static INHIBITED- NOT element IN273 is comprised Vof a magnetic core 260 having a gate w-inding `261 and a reset Winding 262. The gate Winding `261 may be energized from transformer terminal Gb, through flasher terminal 235Gb, conductors 236 yand 23611, Winding 261, rectifier 263, rectifier 264, of non-linear impedance 265, conductor 236, flasher terminal 234Ca to transformer terminal Ca. The non-linear impedance 265 includes transformer terminal Ca, flasher terminal 234Ca, conductor 233, rectifier 264, resistor 266, conductor 229, flasher terminal 228Ga and transformer terminal Ga. Rectifier 263 and non-linear impedance 265 connect gate lWind-ing 261 to output -terminal 267. The reset Winding is connected to NOT input terminal 268 through rectifier 269, reset Winding 262, =INHIBIT input terminal 270, rectifier 27,1 of non-linear impedance 272, conductor 233, flasher terminal 234Ca to transformer -terminal Ca. The non-linear impedance 27.2 includes transformer terminal Ca, flasher terminal 234Ca, conductor 233, rectifier 271, resistor 274, conductors 236:1 and 236, flasher terminal 235Gb and transformer terminal Gb.

The other INH'IBIT'ED-NOT element l-N275 is comprised of a magnetic core 276, a gate winding 277 and a reset Winding 278. 'Ihe gate Winding 277 is energized from transformer terminal Ga, flasher terminal 228Ga, conductors 229 and 229e, winding 277, rectifier 279, rectifier 288 yof non-linear impedance 281, conductor 233a, flasher terminal 234Ca, to transformer terminal Ca. 'The non-linear impedance i-ncludes transformer terminal Ca, flasher terminal 234Ca, conductor 233e, rectifier 280, resistor 282, conductor 236, flasher terminal 235 and transformer terminal Gb. The rectifier 279 and nonlinear impedance 281 connect gate winding 277 to output terminal 267. The reset winding 278 is connected to NOT input terminal 268 through rectifier 283, :and is connected through INHIBIT input terminal 284, rectifier 285 of non-linear impedance 286, conductor 23311, and terminal 234Ca to transformer terminal Ca. The nonlinear impedance includes transformer terminal Ca, flasher terminal 234Ca, conductor 233a, rectifier 285, resistor 289, conductors 229e `and 229, flasher terminal 228 and transformer termina-l Ga.

The output terminal 240 of the oscillator 222 is connected through rectifier 287 to the INHIBIT input terminal 270 of the buffer stage 223. Similarly, the output terminal 253 of the oscillator 222 is connected through rectifier 288 to the INHIBIT input terminal of the buffer stage 223'.

In describing the operation of the flasher 221 as hereinhefore described, it is assumed that as a prime condition, NOT element N224 is gating an output signal through loutput terminal 240 to NOT element N225 to reset its core 312 to thus prevent an output from :being gated through output terminal 253. 'The output through terminal 248 also charges capacitor 254 with a charging current which is determined by the coercive force of the core 3.12, the resistor 252 and the winding 247. As capacitor 254 continues to be charged with each additional gating pulse through terminal 240, the other capacitor 257 is discharging through Output terminal 253, rectifier 288, resistors 247 and 289, conductors 22911 and 229, rectifier 259, and resistor 258 back to the capacitor 257. Additionally, capacitor 257 may discharge through rectifier 256 through the transformer Winding connected across terminals 228Ga and 234Ca. The NOT element N224 thus receives no effective input to reset its core 226 and accordingly continues to gate an output to capacitor 254. As capacitor 254 continues to charge, it eventually blocks the reset signal to NOT input terminal 248 and rat the same time reduces its own charging rate. The termination of the NOT input to reset winding 247 causes NOT element N225 to begin gating an output through its output terminal 253 to begin charging capacitor 257 and to cause reset of core 226 through NOT input terminal 238. The NOT element N224 now ceases gating an output through 240, thus permitting charged capacitor 254 to discharge through terminal 240, rectifier 287, resistors 237 and 274, conductors 23611 and 236, rectifier 256 and resistor 255 -back to capacitor 254. Additionally, capacitor 254 may discharge through rectifier 259 through terminals 228Go and 23-5Gb connected across the transformer. The NOT element N225 thus receives no effective input to reset its core and accordingly continues to gate an output to reset core 226 of NOT element N224 and to continue charging capacitor 257. As capacitor 257 continues to charge, it eventually blocks .the reset signal to NOT input terminal 238 and at the same time reduces its own charging rate. The NOT element N224 begins gating an output to begin a new cycle lof operation and thus N224 and N225 cooperate to provide the desired oscillations.

As the NOT element N224 is gating an output signal through terminal 240 to charge its associated capacitor 254 and reset core 312 of NOT element N225, all in the manner hereinbefore described, the output through terminal 240 also is providing a signal through rectifier 287 to INHIBIT terminal 278 of INHlBlTED-NOT element lN27 3 in the buffer sta-ge 223. This INHIBIT input voltage signal is the same phase and opposite in direction to the reset voltage across reset Winding 262. This input signal 270 increases as capacitor 257 charges to prevent full reset of core 226. When the INHIBIT signal reaches a predetermined level, reset of core 260` is blocked, causing it to gate an output through terminal 265-, 267 and flasher output terminal 290. The output signal from lN273 is provided through NOT input terminal `268 and rectifier 283 to reset winding 278 of INHIBITED-NOT element IN275 to thus reset core 276 which prevents gating Winding 277 from gating :an output Ithrough rectifier 279 to output terminal 267 and flasher output 290. The lNH'lBlTED-NOT element IN273 continues gating an output to flasher terminal 290 so long as the NOT element N224 of the oscillator stage 222 is gating an output. While NOT element N224 is gating an output, capacitor 257 is discharging to provide a signal through output terminal 253 and rectifier 288 to INHIBIT input terminal 284 `in the manner previously described. But,

the NO-T input signal is not blocked, as the voltage level on the capacitor is too low at this time, and thus the capacitor 257 discharge signal to INHIBIT terminal 284 is insufficient to inhibit INHIBITED-NOT element I-N 275. in a similar fashion, when NOT element N225 is gating an output signal to charge capacitor 257 `and reset the NOT element N224 in the manner previously described, the output signal from N225 .through output terminal 253 is provid-ing an input signal through rectifier 288 to IN- HIBIT terminal 284 of INHIBlTED-NOT element IN275. This INHIBIT signal opposes the NOT signal to reset winding 278, thus blocking reset of core ,276' which then gates an output through rectifier 279, and output terminal 267 to asher output terminal 290. At the same time, the output [from IN275 provides a signal through NOT terminal 269 to reset winding 262 causing reset of core 260 to thus terminate its output signal to asher output terminal 290.

Thus, it is seen that the buffer stage 223 responds to oscillations of lthe oscillator stage 222 to alternately provide signals of .opposite phase to Ithe flasher output terminal 290. Accordingly, if the output tenminal 290 is connected to an input terminal of a static element such as preamplifier A13 of FIG. 5 or any of the preamplifiers as hereinbefore described, the output signal lfrom 290 will periodically be in phase with the reset voltage of said static element `thus providing la pulsing on input signal.

It is obvious that appropriate toroids, rectifier boxes, resistors and a printed circuit board representing a flasher 221 of FIG. 1l may be encapsulated in a plug-in container in a manner clearly taught by the plug-in container 290 of FIG. 7. Accordingly, the details of the particular plug-.in container for the flasher are not shown. It is clear Ithat such a plug-in container would have a plug-in terminal for connecting terminal 228Ga to bus line I I a plug-in terminal connecting terminal 290 to bus line CC, a plug-in terminal connecting terminal 224Ca to bus line KK, yand a plug-in terminal connecting terminal 235 to bus line EE. The flasher unit 221 is shown in a container unit 313 and plugged in to power track 220 in FIG. to provide a flasher output signal to each of the plug-in containers 200 and 200:1 through -bus bar 2Min connected in common to the flasher input terminal of each plug-in container.

vinasmuch as the annunciator embodying the #features of this invention is comprised of static logic elements having no moving parts, the annunciator is highly reliable in operation `and requires substantially no maintenance.

Since certain of `the above-described `features may be changed without departing from the spirit `and scope of this invention, it is intended that all the rnatter contained in the above description and shown in the accompanying drawings should be considered as illustrative only.

We claim as our invention:

l. In an annunciator: a static AND-NOT element having an output connected to an alarm and to an input of a first static OR element, said first static OR element having an output connected to one AND input of a two input AND amplifier having an output for controlling an indicator; an output from a signal device connected to the AND input of said static AND-NOT element and connected to one AND input of a static MEMORY; said static MEMORY having an output connected to one input of said first static OR element and connected to an input of a second static OR element; said second static OR element connected to the second AND input of said AND amplifier; an output from a pulse producing means for altering said control signal and connected to an` input of said second static OR element; an output from an acknowledge signal means connected to the second E@ input of said static MEMORY; and an output from said MEMORY connected to the NOT input of said static AND-NOT element.

2. In an annunciator: a first static AND-NOT element having an output connected to an alarm and connected to one AND input of a three input AND amplifier having an output for connection to an indicator; a static three input AND-MEMORY having a first output connected to one AND amplifier input and connected to a second AND input of said AND amplifier, and having a second output connected to the NOT input of said first static AND-NOT element and connected to an AND input of `a second static AND-NOT element; said second static AND-NOT element having an output for controlling an additional alarm; a flasher having an output connected to the second and third AND inputs of said AND amplifier; means for providing an abnormal signal and having an output connected to the AND input of said first static AND-NOT element, to a first input of said AND-MEMORY, to the NOT input of said second static AND-NOT element and to the third AND input of said AND amplifier; means for providing an acknowledge signal and having :an output connected to the second and third inputs of said static AND-MEMORY.

3. `In an annunciator: a static INHIBITED AND-NOT element having an output connected to a plurality of inputs including an alarm input, a first input of a two input AND amplifier, and the AND input of la static AND-NOT element; said static AND-NOT element having an output connected to the AND input and the IN- HIBIT input of said INHIBITED AND-NOT element; a static AND-MEMORY element having two inputs and two outputs with one of said outputs connected to both inputs of said static AND amplifier and with the second output connected to the NOT input of said INHIBITED AND-NOT element; la fiasher element having an output connected t-o one input of said AND amplifier; means for providing an abnormal signal and having 4an output connected to the AND input of said static INHIBITED AND-NOT element and to one input of said static AND- MEMORY; means for providing an acknowledge signal and having an .output connected to the other input of said static AND-MEMORY.

4. In an annunciator: a static INHIBITED AND-NOT element having an output connected to a plurality of inputs including an ialarm input, a first input of a threeinput AND amplifier, and the AND input of a lfirst static AND-NOT element; said static AND-NOT element having an output connected to the AND input and the IN- HIBIT input of said INHIBITED AND-NOT element; a second INHIBITED AND-NOT element having an output connected to the NOT input of the first INHIBITED AND-NOT element, the single input of a static AND element, and the AND input of a second static AND- NOT element, said second AND-NOT element having an output connected to a second alarm; said single input AND element having an output connected to the first and second AND inputs of said three-input AND amplier, and to the AND input of the second INHIBITED AND- NOT element; a fiasher having van output connected to second and third AND inputs of said three-input AND amplifier; means for providing an abnormal signal and having an `output connected to the A'ND input of the `first INHIBITED AND-NOT element, to the INHIBIT input of the second lINI-IIBITED AND-NOT element, to the NOT input of the second AND-NOT element, and to the third AND input of the three-input AND amplifier; and means lfor providing ian acknowledge signal and having an output connected to the NOT input of the first AND-NOT element, and to the AND input and the NOT input of the second INHIBITED AND-NOT element.

(References ou following page) 21 References Cited in the ille of this patent 2,867,734

UNITED STATES PATENTS 2,209,883 GOhOICl July 30', 1940 2,942,250 2,324,912 Cragoy July 20, 1943 5 219433,04 2,325,902 Baller Allg. 3, 1943 29691532 2,376,659 Chireix May 2.2, 1945 2,478,689 Fouchaux Aug. 9, 1949 2,757,286 Wanlass Iuly 3'1, 1956 2,779,936 Loudon Ian. 24, 1957 2,780,797 Gooding Feb. 5, 1957 2,847,074 Eauumer Dec. 17, 1957 241 and 2U 2,820,217 Sperry Ian. 14, 1958 2,832,947 Patchell Apr. 29, 1958 2,832,948 Derr et al. Apr. 29, 1958 15 2,839,741 Kratvivlle June y17, 1958 2,863,956 Schmidt Dec. 9, 1958 22 Steed Ian. 6, 1959 Arrasmith May 19, 1959 Hubbard Aug. 25, 1959 Sinninger June 21, 1960 Schmidt June 28, 1960 Ebel Ian. 2A, 1961 OTHER REFERENCES Universal Panalarm 50, publication published by 10 Panalarm Products, Inc., Chicago, Ill., 1952 (pp. 3, 4, 8,

Booth, A. B., et al.: Automatic Digita-1 Calculators, 2nd ed., London, Buttenworths Scientific Publication, 1956 (pp. 78, 79, 90-93).

Brown, R. B., et lal.: Transistors: A New Class of Relays in Control Engineering, December 1956 (pp. 70-76).

Claims (1)

1. 4. IN A ANNUNCIATOR: A STATIC INHIBITED AND-NOT ELEMENT HAVING AN OUTPUT CONNCETED TO A PLURALITY OF INPUTS INCLUDING AN ALARM INPUT, A FIRST INPUT OF A THREEINPUT AND AMPLIFIER, AND THE AND INPUT OF A FIRST STATIC AND-NOT ELEMENT; SAID STATIC AND-NOT ELEMENT HAVING AN OUTPUT CONNECTED TO THE AND INPUT AND THE INHIBIT INPUT OF SAID INHIBITED AND-NOT ELEMENT; A SECOND INHIBITED AND-NOT ELEMENT HAVING AN OUTPUT CONNECTED TO THE NOT INPUT OF THE FIRST INHIBITED AND-NOT ELEMENT, THE SINGLE INPUT OF A STATIC AND ELEMENT, AND THE AND INPUT OF A SECOND STATIC ANDNOT ELEMENT, SAID SECOND AND-NOT ELEMENT HAVING AN OUTPUT CONNECTED TO A SECOND ALARM; SAID SINGLE INPUT AND ELEMENT HAVING AN OUTPUT CONNECTED TO THE FIRST AND SECOND AND INPUTS OF SAID THREE-INPUT AND AMPLIFIER, AND TO THE AND INPUT OF THE SECOND INHIBITED ANDNOT ELEMENT; A FLASHER HAVING AN OUTPUT CONNECTED TO SECOND THIRD AND INPUTS OF SAID THREE-INPUT AND AMPLIFIER; MEANS FOR PROVIDING AN ABNORMAL SIGNAL AND HAVING AN OUTPUT CONNECTED TO THE AND INPUT OF THE FIRST INHIBITED AND-NOT ELEMENT, TO THE INHIBIT INPUT OF THE SECOND INHIBITED AND-NOT ELEMENT, TO THE NOT INPUT OF THE SECOND AND-NOT ELEMENT, AND TO THE THIRD AND INPUT OF THE THREE-INPUT AND AMPLIFIER; AND MEANS FOR PROVIDING AN ACKNOWLEDGE SIGNAL AND HAVING AN OUTPUT CONNECTED TO THE NOT INPUT OF THE FIRST AND-NOT ELEMENT, AND TO THE AND INPUT AND THE NOT INPUT OF SECOND INHIBITED AND-NOT ELEMENT.

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