US3091391A - Method and arrangement for checking the conformity of signals with a code system - Google Patents

Description

May 28, 1963 H. REICHERT METHOD AND ARRANGEMENT FOR CHECKING THE CONFORMI 0F SIGNALS WITH A 000E SYSTEM Filed April 10, 1961 LULOLOLOLO LUULLOOLLO OLLLLOOOOL LLl-LLOOOOO LLLLLOUUOO OOOOOLLLLL 123 5678 LULOLOLOLO LUOLLOOLLO LLLLUOOUL UODOOLLLLL 0 23456789 QQQ N Jib 1N United States Patent 3,091,391 METHOD AND ARRANGEMENT FGR CHECKENG THE CONFORMITY OF SIGNALS WITH A CODE SYSTEM Hugo Reichert, Wilhelmsiiaven, Germany, assignor to Olympia Werke AG, Wilhelmshaven, Germany Filed Apr. 10, 1961, Ser. No. 101,827 Claims priority, application Germany Apr. 11, 1960 9 Claims. (Cl. 235-153) The present invention concerns a method and a circuit arrangement for the purpose of checking, in the course of processing coded digital information, whether the various signal combinations which are being introduced are in conformity with the terms of a selected portion of the particular code system. More particularly, the invention applies to the processing of information represented by signal combinations in terms of e.g. a binary code, wherein digital information is represented by a binary-decimal eX- cess-code.

It is to be understood that a binary-decimal code system represents each of the digits in the different decimal orders of a multi-order decimal number by a separate binary bit combination. The characteristics of an excess-code system will be explained further below in reference to the drawing.

In the development of electronic calculating machines it is often desirable to provide for a method and for a circuit arrangement which makes it possible to check on digital information being processed by the machine, and particularly to check whether at certain points within the network of the machine the coded information appearing at such points is composed of bit combinations representing certain information in conformity with the particular code system. It is further desirable that upon the appearance of a bit combination which is not one of the bit combinations which represent according to the code system such specific information, a suitable indication or error signal is produced and/or some corresponding operational function of a machine component is effected. Such a checking on the coded information introduced into a data processing machine is of particular importance where the information is of alphanumeric character because under such circumstances it is necessary to differentiate clearly between bit combinations representing, according to the particular code system, digits that are further to be processed in the machine and represented by the respective excess code, and, on the other hand, similarly coded alphabetical information which could not be processed in the same manner and is not to be processed in the same way by the machine or by the calculating portion of the machine.

It would be possible to provide for checking means which comprise e.g. a separate checking channel for every one of the ten bit-combinations which according to the code system represent respectively the digits ranging from 0 to 9. However such an arrangement would call for an excessively large number of lines and control elements, particularly in the case of a code system providing for every one of the digits a great number of code elements, as for instance in the case of a 6-element code, an 8-element code, etc. It would be also possible to add to every one of the various bit combinations of the code a separate check-bit. The relation of such check-bit to the other bits of each bit combination, if tested by the checking means, would indicate whether the particular processed bit combinations are in conformity with the code system or not. However, also such a method and checking arrangement would entail a substantial number of additional components or channels for the machine, or would, at least, slow down the operation of the machine.

It is therefore a main object of this invention to pro- 3,091,391 Patented May 28, 1963' vide for a method and for an arrangement for checking in a simple and time-saving manner whether bit combinations introduced into or processed by a machine of the type set forth are in conformity with a selected portion of a binary-decimal code system.

It is a further object of this invention to provide for an arrangement of the above purpose which requires a comparatively small number of channels, connections and control means for carrying out the checking operation.

With the above objects in View, the invention provides for a method of checking, in a circuit arrangement for processing digital information represented by signal combinations in terms of a binary-decimal excess-code, and including checking means, the conformity with such code of individual signal combinations to be processed, comprising the steps of introducing such coded digital information into the checking means, and checking on the presence of only those signal combinations contained in said introduced coded information which are needed to indicate by their presence that the respective checked inform ation-representing signal combination is in conformity with the particular code.

In another aspect the invention provides in a circuit arrangement for processing digital information represented respectively by bit combinations in terms of a binarydecimal excess code of n code elements, in combination, input means for receiving digital information and comprising n input elements respectively assigned to the 11 code elements, each of said input elements having a first and a second output for delivering, respectively, the two different bits alternatively adapted to constitute the particular code element; a plurality of AND-circuit rneans respectively assigned to diiferent bit combinations selected from the binary-decimal excess-code, said AND- circuit means having each a plurality of inputs respectively connected with those of said outputs of said input elements which are assigned to deliver the bits constituting the selected bit combination assigned to the respective AND-circuit means, each of said plurality of AND-circuit means, delivering at its output a signal only when from said input means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; and output means connected with the outputs of said plurality of AND-circuit means for delivering an output signal Whenever any one of said AND-circuit means delivers a signal, so that the delivery of said output signal indicates that a bit combination representing digital information in terms of a code of n code elements and applied to said input means contains the selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with the particular n-element binary-decimal excess code.

The novel features which are considered as characteristic for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing, in which:

FIG. 1 illustrates diagrammatically a 3-excess code system with 4 code elements per hit combination and shows which digits between 0 and 9 are represented by the various bit combinations;

FIG. 2 illustrates in a similar manner a 27-excess code system composed of bit combinations of 6 code elements, showing also which of the digits between 0 and 9 are represented by the various bit combinations; and

FIG. 3 illustrates diagrammatically a circuit arrangement according to the invention for carrying out the i 3 method according to the invention in connection with the use of a code system according to FIG. 2.

The code system illustrated by FIG. 1 is generally known and is a 3-excess code system with tour code elements per bit combination. It is derived from a standard 4-element binary code in which 0000 represents by eliminating the first three lines of such a code and by using the bit combinations which in the regular code would represent the digits from 3 to 13 to represent, respectively, the digits ranging from 0 to 9.

The code system according to FIG. 2 is a 6-element binary code which is similarly derived from a standard 6-element binary code by eliminating the first 27 lines of the code and by assigning to each of the digits 0 to 9 those bit combinations of the regular code which would in the regular code represent the respective digit plus the digit value 27. For instance, the bit combination of FIG. 2 which represents 0 is the same which in the regular code would represent 27, and the bit combination representing according to KG. 2 the digit 3 is the same bit combination which in the regular code would represent 3 plus 27 equal 30.

As can be seen from FIGS. 1 and 2, in an excess-code system two groups of four bit combinations each comprise partial bit combinations which are characteristic of the particular group and do not appear in any other bit combinations of the system. For instance, in the 3-excess code according to FIG. 1 the group of bit combinations representing the digits 1 to 4 shows in the two highest order positions of code elements the partial bit combination 0L, and similarly the group representing the digits 5 to 8 shows in the same order positions the partial bit combination L0. In the t27-excess code system according to FIG. 2 the group representing the digits from 1 to 4 shows the partial bit combination OLLL while the group representing the digits from 5 to 8 shows the partial bit combination L000. Consequently, according to the invention (in an n-element code system) an n-element bit combination can be checked as to whether it represents digits or other information, e.g. alphabetical information, by checking only whether in such a complete bit combination is included one of the two partial bit combinations characteristic of one or the other of the groups representing the digit values 1 to 4, and 5 to 8, while of course the introduced or processed n-element bit combination must be checked separately for the presence of the complete bit combinations representing 0 or 9. This means that as a whole only four checks have to be carried out for determining any'n-element bit combination represents one of the 10 selected digit representing bit combinations of the entire code system.

It can be seen that in this manner the checking on the meaning of coded digital information is greatly simplified as compared with possible other methods or means serving the same purpose.

The great advantages of the system according to the invention are strikingly evidenced by the diagrammatic illustration of an embodiment of an arrangement according to the invention as shown by FIG. 3.

FIG. 3 does not illustrate a circuit diagram for a calculating machine, but only an arrangement for checking the meaning of processed information, and this checking arrangement could be combined practically with any type of electronic calculating arrangements.

The arrangement according to FIG. 3 has an input section composed of 6 input elements respectively corresponding to the 6 code elements which are the basis of the code illustrated by FIG. 2. By way of example, the input section may be a shift register of generally known type composed of 6 bistable register elements, e.g. flip-flops FF; to FF The consecutive register elements are connected with each other by delay members V, as is well known. A -element bit combination which is to be checked is introduced at the input terminal ZE as 4 a series of pulses and the thus introduced information is shifted by shift pulses applied at the shift terminal T in a manner entirely known to the art.

Each of the bistable register elements has, as is known, a first and a second output which may be also called the normal and complement outputs. As seen in FIG. 3, the right-hand output of each of the register elements PR to FF may be considered, for the purpose of we planation, the normal output at which, when the respective register element is in one of its stable states, a signal appears representing the binary bit L, while no signal appears at this output that would represent the binary bit 0. The opposite applies to the left-hand out put of each of the register elements. Consequently, a bit signal 0 or L will be available at one or the other of the outputs of the individual register elements as indicated in FIG. 3, depending upon the stable state into which the individual register element has been placed by the introduction of the 6-element bit combination into the entire shift register.

Since, as stated above, only four checks have to be carried out in order to establish whether a 6-element bit combination applied to the input means is in conformity with the code according to FIG. 2, only four AND-circuits U M2, M and a are provided in the arrangement, each of these AND-circuits having a plurality of inputs which are respectively connected with the first and second outputs of the register elements FF to FF respectively. As is well known, an AND-circuit is capable of transmitting or delivering a signal only if a signal is applied to all of its inputs. The AND-circuits u and a are assigned to the 6-element bit combinations representing 0 and 9, respectively, and have for this reason 6 inputs. The AND-circuits a and u are assigned to the partial bit combinations of four elements only characteristic of the first and second group of bit combinations representing digit values from 1 to 4, and from 5 to 8, respectively, and have therefore each four inputs. Consequently, these inputs of the AND-circuits u to 10 respectively, which are intended to receive a binary bit L are connected with the output L of that one of the register elements which corresponds by its position in the register to the order position of the respective bit L in the respective AND-circuit. Similarly, those inputs of the AND-circuits which are to receive a binary bit '0, are connected with the corresponding output of the corresponding register element. For instance, in the case of the AND-circuit bi the input M21 is connected with the output 0 of the element FF the input 22 is connected with the output L of the element FFg, the input 1: is connected with the output L of the element FF and the output M is connected with the output L of the element FF Thus, the AND-circuit n is capable of checking on the presence of the partial fixed combination ()LLL characteristic of the bit combinations representing the digits 1 to 4.

The AND-circuit a serves to check on the presence of the second partial bit combination L000 characteristic of the second group of bit combinations representing the digits 5 to 8. Therefore the input 1: is connected with the output L of the element FF the input n is connected with the output 0 of the element FF the input M is connected with the output 0 of the element FF and the input n is connected with the output 0 of the element FF The AND-circuit 1: is assigned to the checking of the complete 6-element bit combination representing the digit 0. Consequently its input a is connected with the output 0 of the element F1 the input u is connected with the output L of the element FF the input a is connected with the output L of the element PF the input 14 is connected with the output 0 of the element FF the input 11 is connected with the output L of the element FF and the input u is connected with the output L of the element FP Analogously, the AND-circuit 11 is assigned'to checking on the presence of G-element bit combination moron representing the digit value 9. Therefore, its input 11 is connected with the output L of the element FF the input 1: is connected with the output of the element FF the input 11 is connected with the output 0 of the element FF the input 11 is connected with the output L of the element FF the input m is connected with the output 0 of the element FF and the input M is connected with the output 0 of the element FP From the above it will be clear that the individual AND-circuits u to 1: will furnish an output signal only if and when the corresponding bit combination or partial bit combination has been introduced into the shift register. Any other bit combination, i.e. any bit combination not in conformity with the code system according to FIG. 2, and introduced into the shift register, will have no effect at the outputs of the AND-circuits M to m.

The output lines u 1: a and 21 of these AND-circuits are connected to a common OR-circuit 0 which is capable of delivering a signal provided that any one of the just mentioned output lines carries a signal. The appearance of a signal at the output of the OR-circuit 0 indicates that the 6-element bit combination is introduced into the shift register was in conformity with the code system according to FIG. 2.

The output of the OR-circuit O is connected with one input of a further AND-circuit 1: to other input whereof a check pulse P may be applied only after a complete 6- element bit combination has been introduced into the shift register. When the AND-circuit n is energized both by an output pulse from the OR-circuit 0 and by a check pulse P then a signal A would be delivered by the AND- circuit a However, for the purpose of convenience, a pulse conversion device I is interposed between the OR- circuit 0 and the first input of the AND-circuit M5. The conversion device operates in a well known manner to the effect that if a pulse or signal is delivered by the OR- eircuit 0 no pulse or signal is delivered by the conversion device to the AND-circuit n while, when no signal is delivered by the OR-circuit '0 the conversion device 1 furnishes a signal or pulse to the first input of the AND- circuit a Consequently, upon application of the check pulse P, a warning signal or error signal A will appear at the output of the AND-circuit 11 if the checking operation described above indicates that a 6-elernent bit combination introduced into the shift register is not in conformity with the code system according to FIG. 2.

Summing up, the operation of the arrangement according to FIG. 3 is as follows. May it be assumed that a bit combination OLLOOO is to be checked. As can be seen this bit combination is not in conformity with the excess code according to FIG. 2. This bit combination is introduced as a series of pulses at the input terminal ZE and stored in the shift register under the action of the shift pulse applied at the shift input T. After five shift pulses the entire bit combination will be stored in the register composed of the flip-flops FF to FP Under these circumstances signals will appear at the following outputs of the register elements: output 0 of FF output L of FF output L of FF output 0 of FF,;, output 0 of FF and output 0 of FP As can be easily found by the diagram of FIG. 3, under these circumstances none of the AND-circuits 1: to M}; will obtain signals at all of its inputs and consequently no signal will be delivered through any one of the output lines u M20, M and M40, and therefore due to the absence of an output signal, a signal will .be produced and delivered by the conversion device L. This signal is then applied to the first input of the AND-circuit u The check pulse P should be timed in such a manner that always after a complete 6- element bit combination has been introduced and stored in the shift register FF to FP the check pulse P is applied to the AND-circuit a so as to issue an error or warning signal provided that also an output signal is delivered from the conversion device I In the present example, such an output signal is delivered by the conversion device J so that now the delivery of the error or warning signal indicates that the bit combination which has been checked is not in conformity with the excess code.

Had the introduced and checked bit combination been in conformity with the excess code according to FIG. 2, then an output signal would have been applied to the conversion device I and no signal would have been applied thereby to the AND-circuit a Consequently upon application of the check pulse P no error signal A would have been delivered which fact indicates that the checked bit combination was in conformity with the excess code representing decimal digits.

It is evident, that the error or rwarning signal A appearing in a device of any suitable kind as symbolized by the block around the letter A could as well be utilized for operating for instance a relay in order to carry out some corrective or other operation in a correspond ing part of the machine with which the arrangement according to FIG. 3 is combined for cooperation. It can be seen that in operation of the arrangement according to FIG. 3 the appearing of a signal A would indicate that the information introduced as signals in terms of the binary code is not constituted by digits represented by the excess-code according to FIG. 3, but consists of other eig. alphabetical information represented by signals in terms of said binary dode.

While for the purpose of explanation in FIG. 3 a shift register has been shown and described into which the signals representing a bit combination are introduced in series, it is evident that other types of registers or input means may be used as well into which the bit combination is introduced in parallel.

It will be understood that each of the elements described above or two or more together, may also find a useful application in other types of method and arrangements for checking the correctness of coded digital information diifering from the types described above.

While the invention has been illustrated and. described as embodied in a method and arrangement for checking the correctness of digital information represented by a binary-decimal excess-code, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without departing in any way from the spirit of the present invention.

Without further analysis the foregoing will so fully reveal the gist of the present invention that others can by applying current knowledge readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of thegeneric or specific aspects of this invention and, therefore, such adaptations should and are intended to be comprehended within the meaning and range of equivalence of the following claims.

What is claimed and desired to be secured by Letters Patent is:

.1. In a circuit arrangement for processing information data represented respectively by bit combinations in terms. of a binary code of 11 code elements, in combination, input means for receiving and storing coded information data and comprising n bistable input elements respectively assigned to the n code elements, each of said input elements having an input and a first and a second output for delivering, respectively, the two different bits alternatively adapted to constitute the particular code element; a plurality of AND-circuit means respectively assigned to different bit combinations selected from a portion of said binary code so as to constitute a binarydecimal excess-code representing digital information, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said input elements which are assigned to deliver the bits. con-- stituting the selectedbit combination assigned to the respective AND-circuit means, each of said plurality of AND-circuit means deliverin-g at its output a signal only when from said input means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; output means connected with the outputs of said plurality of AND-circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal; and means for applying a release signal to said output means, so that the delivery of said output signal indicates that a bit combination representing information data in terms of a code of 11 code elements and applied to said input means contains the selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which constitutes a binary-decimal excess code representing digital information.

2. In a circuit arrangement for processing information data represented respectively by bit combinations in terms of a binary code of n code elements, in combination, shift register means for receiving and storing coded information data and comprising n bistable register elements respectively assigned to the n code elements and delay elements connected between consecutive register elements, each of said register elements having an input and a first and a second output for delivering, respectively, the two different bits alternatively adapted to constitute the particular code element; a plurality of AND-circuit means respectively assigned to different bit combinations selected from a portion of said binary code so as to constitute a binary-decimal excess code representing digital information, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said register elements which are assigned to deliver the bits constituting the selected bit combination assigned to the respective AND-circuit means, each of said plurality of AND-circuit means delivering at its output a signal only when by said register means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; and output means connected with the outputs of said plurality of AND-circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal; and means for applying a release signal to said output means, so that the delivery of said output signal indicates that a bit combination representing information data in terms of a code of n code elements and applied to said register means contains a selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which contributes a binary-decimal excess code representing digital information.

3. In a circuit arrangement for processing information data represented respectively by bit combinations in terms of a binary code of n code elements, in combination, shift register means for receiving and storing coded information data and comprising n bistable register elements respectively assigned to the n code elements and delay elements connected between consecutive register elements, each of said register elements having an input and a first and a second output for delivering, respectively, the two different bits alternatively adapted to constitute the particular code element; a plurality of AND-circuit means respectively assigned to different bit combinations selected from a portion of said binary code so as to constitute a binary-decimal excess code representing digital information, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said register elements which are assigned to deliver the bits constituting the selected bit combination assigned to, the respective AND-circuit means, each of said plurality of AND-circuit means delivering at its output a signal only when from said register means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; output means including OR-circuit means connected with the outputs of said plurality of AND-circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal; and means for applying a release signal to said output means, so that the delivery of said output signal indicates that a bit combination representing information data in terms of a code of n code elements and applied to said register means contains a selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which constitutes a binary-decimal excess code representing digital information.

4. In a circuit arrangement for processing information data represented respectively by bit combinations in terms of a binary code of 12 code elements, in combination, shift register means for receiving and storing coded information data and comprising n bistable register elements respectively assigned to the 11 code elements and delay elements connected between consecutive register elements, each of said register elements having an input and a first and a second output for delivering, respectively, the two different bits alternatively adapted to constitute the particular code element; a plurality of AND-circuit means respectively assigned to different bit combinations selected from a portion of said binary code so as to constitute a binary-decimal excess code representing digital information, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said register elements which are assigned to deliver the bits constituting the selected bit combination assigned to the respective AND-circuit means, each of said plurality of AND-circuit means delivering at its output a signal only when from said register means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; output means including OR-circuit means connected with the outputs of said plurality of AND-circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal, said output means further including an AND-circuit arrangement connected at one input with said OR-circuit means, and at another input with an outside pulse source, for delivering an indicating signal upon simultaneous energization of said AND-circuit arrangement by said output signal and said outside pulse; and an outside pulse source for energizing said AND-circuit by application of said release signal, so that the delivery of said indicating signal indicates that a bit combination representing information data in terms of a code of 11 code elements and applied to said register mean-s contains a selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which constitutes a binary-decimal excess code representing digital information.

5. An arrangement as claimed in claim 4 wherein conversion means are interposed between said OR-circuit means and said AND-circuit arrangement, said conversion means providing a signal energizing said AND-circuit arrangement when no output signal is delivered by sm'd OR-circuit means, and said conversion means providing no signal for energizing said AND-circuit arrangement when an output signal is delivered by said OR-circuit means, so that said indicating signal, when delivered, will indicate that no signal is delivered by any one of said AND-circuit means because the particular bit combination applied to said register means is not in conformity with that portion of the particular code which constitutes a binary-excess code representing digital information.

6. In a circuit arrangement for processing information data represented respectively by bit combinations in terms of a binary code of n code elements, in combination, input means for receiving and storing coded information data and comprising n bistable input elements respectively assigned to the n code elements and delay elements connected between consecutive register elements, each of said input elements having an input and a first and a second output for delivering, respectively, the two different b-its alternatively adapted to constitute the particular code element; four AND-circuit means respectively assigned to four different bit combinations selected from a portion of said binary code so as to constitute a binarydecimal excess code representing digital information, two of said selected bit combination-s representin the digit values and 9, respectively, one of the two other ones of said selected bit combinations being parts of n-element bit combinations according to said binary-decimal excess code rep-resenting digits ranging between 1 and 4 and being a common characteristic thereof, and the remaining one of said selected bit combinations being parts of nelement bit combinations according to said binary-decimal excess code representing digit values ranging between 5 and 8 and being characteristic thereof, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said input elements which are assigned to deliver the bits constituting the selected bit combination assigned to the respective AND- circuit means, each of said plurality of AND-circuit means delivering at its output a signal only when from said input means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND-circuit means; output means connected with the outputs of said plurality of AND-circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal; and means for applying a release signal to said output means, so that the delivery of said output signal indicates that a bit combination representing information data in terms of a code of 11 code elements and applied to said input means contains a selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which constitutes a binary-decimal excess code representing digital information.

7. In a circuit arrangement for processing information data represented respectively by bit combinations in terms of a binary code of 11 code elements, in combination, shift register means for receiving and storing coded information and comprising n bistable register elements respectively assigned to the n code elements and delay elements connected between consecutive register elements, each of said register elements having an input and a first and a second output for delivering, respectively, the two differcut bits alternatively adapted to constitute the particular code element; four AND-circuit means respectively assigned to four ditferent bit combinations selected from a portion of said binary code so as to constitute a binarydecimal excess code representing digital information, two of said selected bit combinations representing the digit values 0 and 9, respectively, one of the two other ones of said selected bit combinations being parts of n-element bit combinations according to said binary-decimal excess code representing digits ranging between 1 and 4- and being a common characteristic thereof, and the remaining one of said selected bit combinations being parts of nelement bit combinations according to said binary-decimal excess code representing digit values ranging between 5 and 8 and being characteristic thereof, said AND-circuit means having each a plurality of inputs respectively connected with those of said outputs of said register elements which are assigned to deliver the bits constituting the selected bit combination assigned to the respective AND- circuit means, each of said plurality of AND-circuit means delivering at its output a signal only when from said register means a bit combination is delivered to said plurality of AND-circuit means which is identical with the selected bit combination assigned to the particular AND- circuit means; output means including OR-circuit means connected with the outputs of said plurality of AND- circuit means for storing an output signal whenever any one of said AND-circuit means delivers a signal and for delivering said output signal upon application thereto of a release signal, said output means :further including an AND-circuit arrangement connected at one input with said OR-circuit means, and at another input with an outside pulse source, for delivering an indicating signal upon simultaneous energization of said AND-circuit arrangement by said output signal and said outside pulse; and an outside pulse source for energizing said AND-circuit by application of said release signal, so that the delivery of said indicating signal indicates that a bit combination representing information data in terms of a code of 11 code elements and applied to said register means contains a selected bit combination assigned to at least one of the AND-circuit means, respectively, and therefore is in conformity with that portion of the particular n-element code which constitutes a binary-decimal excess code representing digital information.

8. An arrangement as claimed in claim 1, wherein said bistable input elements are bistable flip-flop circuits.

9. An arrangement as claimed in claim 1, wherein said output means include control means actuatable by said output signal and adapted to be connected with another machine means so as to cause the latter, when said control means is actuated, to process said information data stored in said input means.

Randlev: A Method to Determine at the Source the Validity of Transmitted Signals, I.B.M. Technical Disclosure Bulletin, vol. 2, No. 5, February 1960, 2 pp.

Claims (1)

1. 6. IN A CIRCUIT ARRANGEMENT FOR PROCESSING INFORMATION DATA REPRESENTED RESPECTIVELY BY BIT COMBINATION IN TERMS OF A BINARY CODE OF N CODE ELEMENTS, IN COMBINATION, INPUT MEANS FOR RECEIVING AND STORING CODED INFORMATION DATA AND COMPRISING N BISTABLE INPUT ELEMENTS RESPECTIVELY ASSIGNED TO THE N CODE ELEMENTS AND DELAY ELEMENTS CONNECTED BETWEEN CONSECUTIVE REGISTER ELEMENTS, EACH OF SAID INPUT ELEMENTS HAVING AN INPUT AND A FIRST AND A SECOND OUTPUT FOR DELIVERING, RESPECTIVELY, THE TWO DIFFERENT BITS ALTERNATIVELY ADAPTED TO CONSTITUTE THE PARTICULAR CODE ELEMENT; FOUR AND-CIRCUIT MEANS RESPECTIVELY ASSIGNED TO FOUR DIFFERENT BIT COMBINATIONS SELECTED FROM A PORTION OF SAID BINARY CODE SO AS TO CONSTITUTE A BINARYDECIMAL EXCESS CODE REPRESENTING DIGITAL INFORMATION, TWO OF SAID SELECTED BIT COMBINATIONS REPRESENTING THE DIGIT VALUES 0 AND 9, RESPECTIVELY, ONE OF THE TWO OTHER ONES OF SAID SELECTED BIT COMBINATIONS BEING PARTS OF N-ELEMENT BIT COMBINATIONS ACCORDING TO SAID BINARY-DECIMAL EXCESS CODE REPRESENTING DIGITS RANGING BETWEEN 1 AND 4 AND BEING A COMMON CHARACTERISTIC THEREOF, AND THE REMAINING ONE OF SAID SELECTED BIT COMBINATIONS BEING PARTS OF NELEMENT BIT COMBINATIONS ACCORDING TO SAID BINARY-DECIMAL EXCESS CODE REPRESENTING DIGIT VALUES RANGING BETWEEN 5 AND 8 AND BEING CHARACTERISTIC THEREOF, SAID AND-CIRCUIT MEANS HAVING EACH A PLURALITY OF INPUTS RESPECTIVELY CONNECTED WITH THOSE OF SAID OUTPUTS OF SAID INPUT ELEMENTS WHICH ARE ASSIGNED TO DELIVER THE BITS CONSTITUTING THE SELECTED BIT COMBINATION ASSIGNED TO THE RESPECTIVE ANDCIRCUIT MEANS, EACH OF SAID PLURALITY OF AND-CIRCUIT MEANS DELIVERING AT ITS OUTPUT A SIGNAL ONLY WHEN FROM SAID INPUTS MEANS A BIT COMBINATION IS DELIVERED TO SAID PLURALITY OF AND-CIRCUIT MEANS WHICH IS IDENTICAL WITH THE SELECTED BIT COMBINATION ASSIGNED TO THE PARTICULAR AND-CIRCUIT MEANS; OUTPUT MEANS CONNECTED WITH THE OUTPUTS OF SAID PLURALITY OF AND-CIRCUIT MEANS FOR STORING AN OUTPUT SIGNAL WHENEVER ANY ONE OF SAID AND-CIRCUIT MEANS DELIVERS A SIGNAL AND FOR DELIVERING SAID OUTPUT SIGNAL UPON APPLICATION THERETO OF A RELEASE SIGNAL; AND MEANS FOR APPLYING A RELEASE SIGNAL TO SAID OUTPUT MEANS, SO THAT THE DELIVERY OF SAID OUTPUT SIGNAL INDICATES THAT A BIT COMBINATION REPRESENTING INFORMATION DATA IN TERMS OF A CODE OF N CODE ELEMENTS AND APPLIED TO SAID INPUT MEANS CONTAINS A SELECTED BIT COMBINATION ASSIGNED TO AT LEAST ONE OF THE AND-CIRCUIT MEANS, RESPECTIVELY, AND THEREFORE IS IN CONFORMITY WITH THAT PORTION OF THE PARTICULAR N-ELEMENT CODE WHICH CONSTITUTES A BINARY-DECIMAL EXCESS CODE REPRESENTING DIGITAL INFORMATION.

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